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// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/ROM32X1.v,v 1.1.1.1 2001-11-04 19:00:00 lampret Exp $

// $Header: /home/marcus/revision_ctrl_test/oc_cvs/cvs/or1k/mp3/lib/xilinx/unisims/ROM32X1.v,v 1.1.1.1 2001-11-04 19:00:00 lampret Exp $

/*

/*

FUNCTION        : ROM 32x1

FUNCTION        : ROM 32x1

*/

*/

`timescale  100 ps / 10 ps

`timescale  100 ps / 10 ps

`celldefine

`celldefine

module ROM32X1 (O, A0, A1, A2, A3, A4);

module ROM32X1 (O, A0, A1, A2, A3, A4);

    parameter cds_action = "ignore";

    parameter cds_action = "ignore";

    parameter INIT = 32'h00000000;

    parameter INIT = 32'h00000000;

    output O;

    output O;

    input  A0, A1, A2, A3, A4;

    input  A0, A1, A2, A3, A4;

    wire dout;

    wire dout;

    wire [4:0] adr;

    wire [4:0] adr;

    reg mem [0:31];

    reg mem [0:31];

    reg  [5:0] count;

    reg  [5:0] count;

    buf b0 (adr[4], A4);

    buf b0 (adr[4], A4);

    buf b1 (adr[3], A3);

    buf b1 (adr[3], A3);

    buf b2 (adr[2], A2);

    buf b2 (adr[2], A2);

    buf b3 (adr[1], A1);

    buf b3 (adr[1], A1);

    buf b4 (adr[0], A0);

    buf b4 (adr[0], A0);

    buf b5 (O, dout);

    buf b5 (O, dout);

    initial begin

    initial begin

        for(count = 0; count < 32; count = count + 1)

        for(count = 0; count < 32; count = count + 1)

            mem[count] = INIT[count];

            mem[count] = INIT[count];

    end

    end

    assign dout = mem[adr];

    assign dout = mem[adr];

    specify

    specify

        (A4 => O) = (1, 1);

        (A4 => O) = (1, 1);

        (A3 => O) = (1, 1);

        (A3 => O) = (1, 1);

        (A2 => O) = (1, 1);

        (A2 => O) = (1, 1);

        (A1 => O) = (1, 1);

        (A1 => O) = (1, 1);

        (A0 => O) = (1, 1);

        (A0 => O) = (1, 1);

    endspecify

    endspecify

endmodule

endmodule

`endcelldefine

`endcelldefine