/* dmmu.c -- Data MMU simulation
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/* dmmu.c -- Data MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* DMMU model, perfectly functional. */
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/* DMMU model, perfectly functional. */
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "dmmu.h"
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#include "dmmu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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#include "misc.h"
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#include "misc.h"
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DEFAULT_DEBUG_CHANNEL(dmmu);
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DEFAULT_DEBUG_CHANNEL(dmmu);
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/* Data MMU */
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/* Data MMU */
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/* Precalculates some values for use during address translation */
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/* Precalculates some values for use during address translation */
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void init_dmmu(void)
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void init_dmmu(void)
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{
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{
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config.dmmu.pagesize_log2 = log2_int(config.dmmu.pagesize);
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config.dmmu.pagesize_log2 = log2_int(config.dmmu.pagesize);
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config.dmmu.page_offset_mask = config.dmmu.pagesize - 1;
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config.dmmu.page_offset_mask = config.dmmu.pagesize - 1;
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config.dmmu.page_mask = ~config.dmmu.page_offset_mask;
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config.dmmu.page_mask = ~config.dmmu.page_offset_mask;
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config.dmmu.vpn_mask = ~((config.dmmu.pagesize * config.dmmu.nsets) - 1);
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config.dmmu.vpn_mask = ~((config.dmmu.pagesize * config.dmmu.nsets) - 1);
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config.dmmu.set_mask = config.dmmu.nsets - 1;
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config.dmmu.set_mask = config.dmmu.nsets - 1;
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config.dmmu.lru_reload = (config.dmmu.set_mask << 6) & SPR_DTLBMR_LRU;
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config.dmmu.lru_reload = (config.dmmu.set_mask << 6) & SPR_DTLBMR_LRU;
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}
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}
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inline uorreg_t *dmmu_find_tlbmr(oraddr_t virtaddr, uorreg_t **dtlbmr_lru)
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inline uorreg_t *dmmu_find_tlbmr(oraddr_t virtaddr, uorreg_t **dtlbmr_lru)
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{
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{
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int set;
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int set;
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int i;
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int i;
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oraddr_t vpn;
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oraddr_t vpn;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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/* Which set to check out? */
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/* Which set to check out? */
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set = DADDR_PAGE(virtaddr) >> config.dmmu.pagesize_log2;
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set = DADDR_PAGE(virtaddr) >> config.dmmu.pagesize_log2;
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set &= config.dmmu.set_mask;
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set &= config.dmmu.set_mask;
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vpn = virtaddr & config.dmmu.vpn_mask;
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vpn = virtaddr & config.dmmu.vpn_mask;
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dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE(0) + set];
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dtlbmr = &cpu_state.sprs[SPR_DTLBMR_BASE(0) + set];
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*dtlbmr_lru = dtlbmr;
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*dtlbmr_lru = dtlbmr;
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/* FIXME: Should this be reversed? */
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/* FIXME: Should this be reversed? */
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for(i = config.dmmu.nways; i; i--, dtlbmr += (128 * 2)) {
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for(i = config.dmmu.nways; i; i--, dtlbmr += (128 * 2)) {
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if(((*dtlbmr & config.dmmu.vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
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if(((*dtlbmr & config.dmmu.vpn_mask) == vpn) && (*dtlbmr & SPR_DTLBMR_V))
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return dtlbmr;
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return dtlbmr;
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}
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}
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return NULL;
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return NULL;
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}
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}
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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oraddr_t dmmu_translate(oraddr_t virtaddr, int write_access)
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{
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{
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int i;
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int i;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbmr_lru;
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uorreg_t *dtlbmr_lru;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
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dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if(dtlbmr) { /* Yes, we did. */
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if(dtlbmr) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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dtlbtr = dtlbmr + 128;
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dtlbtr = dtlbmr + 128;
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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runtime.sim.cycles);
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/* Set LRUs */
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/* Set LRUs */
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for(i = 0; i < config.dmmu.nways; i++, dtlbmr_lru += (128 * 2)) {
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for(i = 0; i < config.dmmu.nways; i++, dtlbmr_lru += (128 * 2)) {
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if(*dtlbmr_lru & SPR_DTLBMR_LRU)
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if(*dtlbmr_lru & SPR_DTLBMR_LRU)
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*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
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*dtlbmr_lru = (*dtlbmr_lru & ~SPR_DTLBMR_LRU) |
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((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
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((*dtlbmr_lru & SPR_DTLBMR_LRU) - 0x40);
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}
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}
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/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
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/* This is not necessary `*dtlbmr &= ~SPR_DTLBMR_LRU;' since SPR_DTLBMR_LRU
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* is always decremented and the number of sets is always a power of two and
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* is always decremented and the number of sets is always a power of two and
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* as such lru_reload has all bits set that get touched during decrementing
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* as such lru_reload has all bits set that get touched during decrementing
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* SPR_DTLBMR_LRU */
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* SPR_DTLBMR_LRU */
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*dtlbmr |= config.dmmu.lru_reload;
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*dtlbmr |= config.dmmu.lru_reload;
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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runtime.sim.mem_cycles += config.dmmu.hitdelay;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if ( (write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
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if ( (write_access && !(*dtlbtr & SPR_DTLBTR_SWE))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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} else {
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} else {
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if ( (write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
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if ( (write_access && !(*dtlbtr & SPR_DTLBTR_UWE))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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|| (!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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except_handle(EXCEPT_DPF, virtaddr);
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except_handle(EXCEPT_DPF, virtaddr);
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}
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}
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TRACE("Returning physical address %"PRIxADDR"\n",
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TRACE("Returning physical address %"PRIxADDR"\n",
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(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(config.dmmu.page_offset_mask)));
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(config.dmmu.page_offset_mask)));
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(config.dmmu.page_offset_mask));
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(config.dmmu.page_offset_mask));
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}
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}
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/* No, we didn't. */
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/* No, we didn't. */
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dmmu_stats.loads_tlbmiss++;
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dmmu_stats.loads_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.dmmu.nways; i++)
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for (i = 0; i < config.dmmu.nways; i++)
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if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)
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if (((cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] & SPR_DTLBMR_LRU) >> 6) < minlru)
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minway = i;
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minway = i;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] &= ~SPR_DTLBMR_VPN;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= vpn << 12;
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for (i = 0; i < config.dmmu.nways; i++) {
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for (i = 0; i < config.dmmu.nways; i++) {
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uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
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uorreg_t lru = cpu_state.sprs[SPR_DTLBMR_BASE(i) + set];
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if (lru & SPR_DTLBMR_LRU) {
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if (lru & SPR_DTLBMR_LRU) {
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lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
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lru = (lru & ~SPR_DTLBMR_LRU) | ((lru & SPR_DTLBMR_LRU) - 0x40);
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cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
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cpu_state.sprs[SPR_DTLBMR_BASE(i) + set] = lru;
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}
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}
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}
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}
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cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
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cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] &= ~SPR_DTLBMR_LRU;
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cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
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cpu_state.sprs[SPR_DTLBMR_BASE(way) + set] |= (config.dmmu.nsets - 1) << 6;
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/* 1 to 1 mapping */
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/* 1 to 1 mapping */
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cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;
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cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] &= ~SPR_DTLBTR_PPN;
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cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= SPR_DTLBMR_V;
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cpu_state.sprs[SPR_DTLBMR_BASE(minway) + set] |= SPR_DTLBMR_V;
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#endif
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#endif
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TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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TRACE("DTLB miss (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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runtime.sim.cycles);
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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runtime.sim.mem_cycles += config.dmmu.missdelay;
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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/* return ((cpu_state.sprs[SPR_DTLBTR_BASE(minway) + set] & SPR_DTLBTR_PPN) >> 12) * config.dmmu.pagesize + (virtaddr % config.dmmu.pagesize); */
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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except_handle(EXCEPT_DTLBMISS, virtaddr);
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return 0;
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return 0;
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}
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}
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/* DESC: try to find EA -> PA transaltion without changing
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/* DESC: try to find EA -> PA transaltion without changing
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* any of precessor states. if this is not passible gives up
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* any of precessor states. if this is not passible gives up
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* (without triggering exceptions)
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* (without triggering exceptions)
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*
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*
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* PRMS: virtaddr - EA for which to find translation
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* PRMS: virtaddr - EA for which to find translation
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*
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*
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* write_access - 0 ignore testing for write access
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* write_access - 0 ignore testing for write access
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* 1 test for write access, if fails
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* 1 test for write access, if fails
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* do not return translation
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* do not return translation
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*
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*
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* through_dc - 1 go through data cache
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* through_dc - 1 go through data cache
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* 0 ignore data cache
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* 0 ignore data cache
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*
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*
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* RTRN: 0 - no DMMU, DMMU disabled or ITLB miss
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* else - appropriate PA (note it DMMU is not present
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* else - appropriate PA (note it DMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
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oraddr_t peek_into_dtlb(oraddr_t virtaddr, int write_access, int through_dc)
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{
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{
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uorreg_t *dtlbmr;
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uorreg_t *dtlbmr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbtr;
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uorreg_t *dtlbmr_lru;
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uorreg_t *dtlbmr_lru;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_DME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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if (through_dc)
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if (through_dc)
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data_ci = (virtaddr >= 0x80000000);
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data_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
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dtlbmr = dmmu_find_tlbmr(virtaddr, &dtlbmr_lru);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if (dtlbmr) { /* Yes, we did. */
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if (dtlbmr) { /* Yes, we did. */
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dmmu_stats.loads_tlbhit++;
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dmmu_stats.loads_tlbhit++;
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dtlbtr = dtlbmr + 128;
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dtlbtr = dtlbmr + 128;
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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TRACE("DTLB hit (virtaddr=%"PRIxADDR") at %lli.\n", virtaddr,
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runtime.sim.cycles);
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runtime.sim.cycles);
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
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if((write_access && !(*dtlbtr & SPR_DTLBTR_SWE)) ||
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(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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(!write_access && !(*dtlbtr & SPR_DTLBTR_SRE)))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return(0);
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return(0);
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} else {
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} else {
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if((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
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if((write_access && !(*dtlbtr & SPR_DTLBTR_UWE)) ||
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(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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(!write_access && !(*dtlbtr & SPR_DTLBTR_URE)))
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/* otherwise exception DPF would be raised */
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/* otherwise exception DPF would be raised */
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return(0);
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return(0);
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}
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}
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if (through_dc) {
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if (through_dc) {
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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data_ci = *dtlbtr & SPR_DTLBTR_CI;
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}
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}
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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return (*dtlbtr & SPR_DTLBTR_PPN) | (virtaddr &
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(config.dmmu.page_offset_mask));
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(config.dmmu.page_offset_mask));
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}
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}
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return(0);
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return(0);
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}
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}
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void dtlb_info(void)
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void dtlb_info(void)
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{
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{
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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PRINTF("DMMU not implemented. Set UPR[DMP].\n");
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return;
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return;
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}
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}
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PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
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PRINTF("Data MMU %dKB: ", config.dmmu.nsets * config.dmmu.entrysize * config.dmmu.nways / 1024);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.dmmu.nways, config.dmmu.nsets, config.dmmu.entrysize);
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}
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}
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/* First check if virtual address is covered by DTLB and if it is:
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/* First check if virtual address is covered by DTLB and if it is:
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- increment DTLB read hit stats,
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- increment DTLB read hit stats,
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- set 'lru' at this way to config.dmmu.ustates - 1 and
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- set 'lru' at this way to config.dmmu.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke DMMU page fault exception
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- check page access attributes and invoke DMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment DTLB read miss stats
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- increment DTLB read miss stats
|
- find lru way and entry and invoke DTLB miss exception handler
|
- find lru way and entry and invoke DTLB miss exception handler
|
- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
|
- set 'lru' with config.dmmu.ustates - 1 and decrement 'lru' of other
|
ways unless they have reached 0
|
ways unless they have reached 0
|
*/
|
*/
|
|
|
void dtlb_status(int start_set)
|
void dtlb_status(int start_set)
|
{
|
{
|
int set;
|
int set;
|
int way;
|
int way;
|
int end_set = config.dmmu.nsets;
|
int end_set = config.dmmu.nsets;
|
|
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_DMP)) {
|
PRINTF("DMMU not implemented. Set UPR[DMP].\n");
|
PRINTF("DMMU not implemented. Set UPR[DMP].\n");
|
return;
|
return;
|
}
|
}
|
|
|
if ((start_set >= 0) && (start_set < end_set))
|
if ((start_set >= 0) && (start_set < end_set))
|
end_set = start_set + 1;
|
end_set = start_set + 1;
|
else
|
else
|
start_set = 0;
|
start_set = 0;
|
|
|
if (start_set < end_set) PRINTF("\nDMMU: ");
|
if (start_set < end_set) PRINTF("\nDMMU: ");
|
/* Scan set(s) and way(s). */
|
/* Scan set(s) and way(s). */
|
for (set = start_set; set < end_set; set++) {
|
for (set = start_set; set < end_set; set++) {
|
PRINTF("\nSet %x: ", set);
|
PRINTF("\nSet %x: ", set);
|
for (way = 0; way < config.dmmu.nways; way++) {
|
for (way = 0; way < config.dmmu.nways; way++) {
|
PRINTF(" way %d: ", way);
|
PRINTF(" way %d: ", way);
|
PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,
|
PRINTF("%s\n", dump_spr(SPR_DTLBMR_BASE(way) + set,
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));
|
cpu_state.sprs[SPR_DTLBMR_BASE(way) + set]));
|
PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,
|
PRINTF("%s\n", dump_spr(SPR_DTLBTR_BASE(way) + set,
|
cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));
|
cpu_state.sprs[SPR_DTLBTR_BASE(way) + set]));
|
}
|
}
|
}
|
}
|
if (start_set < end_set) PRINTF("\n");
|
if (start_set < end_set) PRINTF("\n");
|
}
|
}
|
|
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
/*---------------------------------------------------[ DMMU configuration ]---*/
|
void dmmu_enabled(union param_val val, void *dat)
|
static void dmmu_enabled(union param_val val, void *dat)
|
{
|
{
|
if(val.int_val)
|
if(val.int_val)
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_DMP;
|
else
|
else
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_DMP;
|
config.dmmu.enabled = val.int_val;
|
config.dmmu.enabled = val.int_val;
|
}
|
}
|
|
|
void dmmu_nsets(union param_val val, void *dat)
|
static void dmmu_nsets(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
config.dmmu.nsets = val.int_val;
|
config.dmmu.nsets = val.int_val;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTS;
|
cpu_state.sprs[SPR_DMMUCFGR] |= log2_int(val.int_val) << 3;
|
cpu_state.sprs[SPR_DMMUCFGR] |= log2_int(val.int_val) << 3;
|
} else
|
} else
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
}
|
}
|
|
|
void dmmu_nways(union param_val val, void *dat)
|
static void dmmu_nways(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
config.dmmu.nways = val.int_val;
|
config.dmmu.nways = val.int_val;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] &= ~SPR_DMMUCFGR_NTW;
|
cpu_state.sprs[SPR_DMMUCFGR] |= val.int_val - 1;
|
cpu_state.sprs[SPR_DMMUCFGR] |= val.int_val - 1;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
}
|
}
|
|
|
void dmmu_pagesize(union param_val val, void *dat)
|
static void dmmu_pagesize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.pagesize = val.int_val;
|
config.dmmu.pagesize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void dmmu_entrysize(union param_val val, void *dat)
|
static void dmmu_entrysize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.dmmu.entrysize = val.int_val;
|
config.dmmu.entrysize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void dmmu_ustates(union param_val val, void *dat)
|
static void dmmu_ustates(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if (val.int_val >= 2 && val.int_val <= 4)
|
config.dmmu.ustates = val.int_val;
|
config.dmmu.ustates = val.int_val;
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
CONFIG_ERROR("invalid USTATE.");
|
}
|
}
|
|
|
void dmmu_missdelay(union param_val val, void *dat)
|
static void dmmu_missdelay(union param_val val, void *dat)
|
{
|
{
|
config.dmmu.missdelay = val.int_val;
|
config.dmmu.missdelay = val.int_val;
|
}
|
}
|
|
|
void dmmu_hitdelay(union param_val val, void *dat)
|
static void dmmu_hitdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.hitdelay = val.int_val;
|
config.immu.hitdelay = val.int_val;
|
}
|
}
|
|
|
void reg_dmmu_sec(void)
|
void reg_dmmu_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);
|
struct config_section *sec = reg_config_sec("dmmu", NULL, NULL);
|
|
|
reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);
|
reg_config_param(sec, "enabled", paramt_int, dmmu_enabled);
|
reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);
|
reg_config_param(sec, "nsets", paramt_int, dmmu_nsets);
|
reg_config_param(sec, "nways", paramt_int, dmmu_nways);
|
reg_config_param(sec, "nways", paramt_int, dmmu_nways);
|
reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);
|
reg_config_param(sec, "pagesize", paramt_int, dmmu_pagesize);
|
reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);
|
reg_config_param(sec, "entrysize", paramt_int, dmmu_entrysize);
|
reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);
|
reg_config_param(sec, "ustates", paramt_int, dmmu_ustates);
|
reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);
|
reg_config_param(sec, "missdelay", paramt_int, dmmu_missdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, dmmu_hitdelay);
|
}
|
}
|
|
|
