/* immu.c -- Instruction MMU simulation
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/* immu.c -- Instruction MMU simulation
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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Copyright (C) 1999 Damjan Lampret, lampret@opencores.org
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This file is part of OpenRISC 1000 Architectural Simulator.
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This file is part of OpenRISC 1000 Architectural Simulator.
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
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/* IMMU model, perfectly functional. */
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/* IMMU model, perfectly functional. */
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#include "config.h"
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#include "config.h"
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#ifdef HAVE_INTTYPES_H
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#ifdef HAVE_INTTYPES_H
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#include <inttypes.h>
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#include <inttypes.h>
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#endif
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#endif
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#include "port.h"
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#include "port.h"
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#include "arch.h"
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#include "arch.h"
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#include "immu.h"
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#include "immu.h"
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#include "abstract.h"
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#include "abstract.h"
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#include "opcode/or32.h"
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#include "opcode/or32.h"
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#include "spr_defs.h"
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#include "spr_defs.h"
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#include "execute.h"
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#include "execute.h"
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#include "stats.h"
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#include "stats.h"
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#include "sprs.h"
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#include "sprs.h"
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#include "except.h"
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#include "except.h"
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#include "sim-config.h"
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#include "sim-config.h"
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#include "debug.h"
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#include "debug.h"
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#include "misc.h"
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DEFAULT_DEBUG_CHANNEL(immu);
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DEFAULT_DEBUG_CHANNEL(immu);
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/* Insn MMU */
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/* Insn MMU */
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/* Precalculates some values for use during address translation */
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/* Precalculates some values for use during address translation */
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void init_immu(void)
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void init_immu(void)
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{
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{
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config.immu.pagesize_log2 = log2(config.immu.pagesize);
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config.immu.pagesize_log2 = log2_int(config.immu.pagesize);
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config.immu.page_offset_mask = config.immu.pagesize - 1;
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config.immu.page_offset_mask = config.immu.pagesize - 1;
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config.immu.page_mask = ~config.immu.page_offset_mask;
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config.immu.page_mask = ~config.immu.page_offset_mask;
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config.immu.vpn_mask = ~((config.immu.pagesize * config.immu.nsets) - 1);
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config.immu.vpn_mask = ~((config.immu.pagesize * config.immu.nsets) - 1);
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config.immu.set_mask = config.immu.nsets - 1;
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config.immu.set_mask = config.immu.nsets - 1;
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config.immu.lru_reload = (config.immu.set_mask << 6) & SPR_ITLBMR_LRU;
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config.immu.lru_reload = (config.immu.set_mask << 6) & SPR_ITLBMR_LRU;
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}
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}
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inline uorreg_t *immu_find_tlbmr(oraddr_t virtaddr, uorreg_t **itlbmr_lru)
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inline uorreg_t *immu_find_tlbmr(oraddr_t virtaddr, uorreg_t **itlbmr_lru)
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{
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{
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int set;
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int set;
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int i;
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int i;
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oraddr_t vpn;
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oraddr_t vpn;
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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/* Which set to check out? */
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/* Which set to check out? */
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set = IADDR_PAGE(virtaddr) >> config.immu.pagesize_log2;
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set = IADDR_PAGE(virtaddr) >> config.immu.pagesize_log2;
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set &= config.immu.set_mask;
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set &= config.immu.set_mask;
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vpn = virtaddr & config.immu.vpn_mask;
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vpn = virtaddr & config.immu.vpn_mask;
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itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE(0) + set];
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itlbmr = &cpu_state.sprs[SPR_ITLBMR_BASE(0) + set];
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*itlbmr_lru = itlbmr;
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*itlbmr_lru = itlbmr;
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/* Scan all ways and try to find a matching way. */
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/* Scan all ways and try to find a matching way. */
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/* FIXME: Should this be reversed? */
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/* FIXME: Should this be reversed? */
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for(i = config.immu.nways; i; i--, itlbmr += (128 * 2)) {
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for(i = config.immu.nways; i; i--, itlbmr += (128 * 2)) {
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if(((*itlbmr & config.immu.vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
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if(((*itlbmr & config.immu.vpn_mask) == vpn) && (*itlbmr & SPR_ITLBMR_V))
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return itlbmr;
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return itlbmr;
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}
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}
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return NULL;
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return NULL;
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}
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}
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oraddr_t immu_translate(oraddr_t virtaddr)
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oraddr_t immu_translate(oraddr_t virtaddr)
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{
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{
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int i;
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int i;
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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uorreg_t *itlbtr;
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uorreg_t *itlbtr;
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uorreg_t *itlbmr_lru;
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uorreg_t *itlbmr_lru;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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insn_ci = (virtaddr >= 0x80000000);
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insn_ci = (virtaddr >= 0x80000000);
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return virtaddr;
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return virtaddr;
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}
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}
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru);
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if(itlbmr) { /* Yes, we did. */
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if(itlbmr) { /* Yes, we did. */
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immu_stats.fetch_tlbhit++;
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immu_stats.fetch_tlbhit++;
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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TRACE("ITLB hit (virtaddr=%"PRIxADDR").\n", virtaddr);
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itlbtr = itlbmr + 128;
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itlbtr = itlbmr + 128;
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/* Set LRUs */
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/* Set LRUs */
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for(i = 0; i < config.immu.nways; i++, itlbmr_lru += (128 * 2)) {
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for(i = 0; i < config.immu.nways; i++, itlbmr_lru += (128 * 2)) {
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if(*itlbmr_lru & SPR_ITLBMR_LRU)
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if(*itlbmr_lru & SPR_ITLBMR_LRU)
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*itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
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*itlbmr_lru = (*itlbmr_lru & ~SPR_ITLBMR_LRU) |
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((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
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((*itlbmr_lru & SPR_ITLBMR_LRU) - 0x40);
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}
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}
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/* This is not necessary `*itlbmr &= ~SPR_ITLBMR_LRU;' since SPR_DTLBMR_LRU
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/* This is not necessary `*itlbmr &= ~SPR_ITLBMR_LRU;' since SPR_DTLBMR_LRU
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* is always decremented and the number of sets is always a power of two and
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* is always decremented and the number of sets is always a power of two and
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* as such lru_reload has all bits set that get touched during decrementing
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* as such lru_reload has all bits set that get touched during decrementing
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* SPR_DTLBMR_LRU */
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* SPR_DTLBMR_LRU */
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*itlbmr |= config.immu.lru_reload;
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*itlbmr |= config.immu.lru_reload;
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/* Check if page is cache inhibited */
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/* Check if page is cache inhibited */
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insn_ci = *itlbtr & SPR_ITLBTR_CI;
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insn_ci = *itlbtr & SPR_ITLBTR_CI;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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runtime.sim.mem_cycles += config.immu.hitdelay;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (!(*itlbtr & SPR_ITLBTR_SXE))
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if (!(*itlbtr & SPR_ITLBTR_SXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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} else {
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} else {
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if (!(*itlbtr & SPR_ITLBTR_UXE))
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if (!(*itlbtr & SPR_ITLBTR_UXE))
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except_handle(EXCEPT_IPF, virtaddr);
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except_handle(EXCEPT_IPF, virtaddr);
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}
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}
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TRACE("Returning physical address %"PRIxADDR"\n",
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TRACE("Returning physical address %"PRIxADDR"\n",
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(*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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(*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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(config.immu.page_offset_mask)));
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(config.immu.page_offset_mask)));
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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(config.immu.page_offset_mask));
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(config.immu.page_offset_mask));
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}
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}
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/* No, we didn't. */
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/* No, we didn't. */
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immu_stats.fetch_tlbmiss++;
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immu_stats.fetch_tlbmiss++;
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#if 0
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#if 0
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for (i = 0; i < config.immu.nways; i++)
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for (i = 0; i < config.immu.nways; i++)
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if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_LRU) >> 6) < minlru)
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if (((cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] & SPR_ITLBMR_LRU) >> 6) < minlru)
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minway = i;
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minway = i;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] &= ~SPR_ITLBMR_VPN;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] &= ~SPR_ITLBMR_VPN;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= vpn << 12;
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for (i = 0; i < config.immu.nways; i++) {
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for (i = 0; i < config.immu.nways; i++) {
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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uorreg_t lru = cpu_state.sprs[SPR_ITLBMR_BASE(i) + set];
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if (lru & SPR_ITLBMR_LRU) {
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if (lru & SPR_ITLBMR_LRU) {
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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lru = (lru & ~SPR_ITLBMR_LRU) | ((lru & SPR_ITLBMR_LRU) - 0x40);
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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cpu_state.sprs[SPR_ITLBMR_BASE(i) + set] = lru;
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}
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}
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}
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}
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] &= ~SPR_ITLBMR_LRU;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set] |= (config.immu.nsets - 1) << 6;
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/* 1 to 1 mapping */
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/* 1 to 1 mapping */
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] &= ~SPR_ITLBTR_PPN;
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] &= ~SPR_ITLBTR_PPN;
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] |= vpn << 12;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= SPR_ITLBMR_V;
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cpu_state.sprs[SPR_ITLBMR_BASE(minway) + set] |= SPR_ITLBMR_V;
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#endif
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#endif
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/* if tlb refill implemented in HW */
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/* if tlb refill implemented in HW */
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/* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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/* return ((cpu_state.sprs[SPR_ITLBTR_BASE(minway) + set] & SPR_ITLBTR_PPN) >> 12) * config.immu.pagesize + (virtaddr % config.immu.pagesize); */
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runtime.sim.mem_cycles += config.immu.missdelay;
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runtime.sim.mem_cycles += config.immu.missdelay;
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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except_handle(EXCEPT_ITLBMISS, virtaddr);
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return 0;
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return 0;
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}
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}
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/* DESC: try to find EA -> PA transaltion without changing
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/* DESC: try to find EA -> PA transaltion without changing
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* any of precessor states. if this is not passible gives up
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* any of precessor states. if this is not passible gives up
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* (without triggering exceptions).
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* (without triggering exceptions).
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*
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*
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* PRMS: virtaddr - EA for which to find translation
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* PRMS: virtaddr - EA for which to find translation
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*
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*
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* RTRN: 0 - no IMMU, IMMU disabled or ITLB miss
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* else - appropriate PA (note it IMMU is not present
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* else - appropriate PA (note it IMMU is not present
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* PA === EA)
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* PA === EA)
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*/
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*/
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oraddr_t peek_into_itlb(oraddr_t virtaddr)
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oraddr_t peek_into_itlb(oraddr_t virtaddr)
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{
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{
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uorreg_t *itlbmr;
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uorreg_t *itlbmr;
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uorreg_t *itlbtr;
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uorreg_t *itlbtr;
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uorreg_t *itlbmr_lru;
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uorreg_t *itlbmr_lru;
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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if (!(cpu_state.sprs[SPR_SR] & SPR_SR_IME) ||
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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return(virtaddr);
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return(virtaddr);
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}
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}
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru);
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itlbmr = immu_find_tlbmr(virtaddr, &itlbmr_lru);
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/* Did we find our tlb entry? */
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/* Did we find our tlb entry? */
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if(itlbmr) { /* Yes, we did. */
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if(itlbmr) { /* Yes, we did. */
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itlbtr = itlbmr + 128;
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itlbtr = itlbmr + 128;
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/* Test for page fault */
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/* Test for page fault */
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (cpu_state.sprs[SPR_SR] & SPR_SR_SM) {
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if (!(*itlbtr & SPR_ITLBTR_SXE)) {
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if (!(*itlbtr & SPR_ITLBTR_SXE)) {
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
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return(0);
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}
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}
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} else {
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} else {
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if (!(*itlbtr & SPR_ITLBTR_UXE)) {
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if (!(*itlbtr & SPR_ITLBTR_UXE)) {
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/* no luck, giving up */
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/* no luck, giving up */
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return(0);
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return(0);
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}
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}
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}
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}
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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return (*itlbtr & SPR_ITLBTR_PPN) | (virtaddr &
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(config.immu.page_offset_mask));
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(config.immu.page_offset_mask));
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}
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}
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return(0);
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return(0);
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}
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}
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void itlb_info(void)
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void itlb_info(void)
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{
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{
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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PRINTF("Insn MMU %dKB: ", config.immu.nsets * config.immu.entrysize * config.immu.nways / 1024);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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PRINTF("%d ways, %d sets, entry size %d bytes\n", config.immu.nways, config.immu.nsets, config.immu.entrysize);
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}
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}
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/* First check if virtual address is covered by ITLB and if it is:
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/* First check if virtual address is covered by ITLB and if it is:
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- increment ITLB read hit stats,
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- increment ITLB read hit stats,
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- set 'lru' at this way to config.immu.ustates - 1 and
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- set 'lru' at this way to config.immu.ustates - 1 and
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decrement 'lru' of other ways unless they have reached 0,
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decrement 'lru' of other ways unless they have reached 0,
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- check page access attributes and invoke IMMU page fault exception
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- check page access attributes and invoke IMMU page fault exception
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handler if necessary
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handler if necessary
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and if not:
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and if not:
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- increment ITLB read miss stats
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- increment ITLB read miss stats
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- find lru way and entry and invoke ITLB miss exception handler
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- find lru way and entry and invoke ITLB miss exception handler
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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- set 'lru' with config.immu.ustates - 1 and decrement 'lru' of other
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ways unless they have reached 0
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ways unless they have reached 0
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*/
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*/
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void itlb_status(int start_set)
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void itlb_status(int start_set)
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{
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{
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int set;
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int set;
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int way;
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int way;
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int end_set = config.immu.nsets;
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int end_set = config.immu.nsets;
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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if (!(cpu_state.sprs[SPR_UPR] & SPR_UPR_IMP)) {
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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PRINTF("IMMU not implemented. Set UPR[IMP].\n");
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return;
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return;
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}
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}
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if ((start_set >= 0) && (start_set < end_set))
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if ((start_set >= 0) && (start_set < end_set))
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end_set = start_set + 1;
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end_set = start_set + 1;
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else
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else
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start_set = 0;
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start_set = 0;
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if (start_set < end_set) PRINTF("\nIMMU: ");
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if (start_set < end_set) PRINTF("\nIMMU: ");
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/* Scan set(s) and way(s). */
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/* Scan set(s) and way(s). */
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for (set = start_set; set < end_set; set++) {
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for (set = start_set; set < end_set; set++) {
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PRINTF("\nSet %x: ", set);
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PRINTF("\nSet %x: ", set);
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for (way = 0; way < config.immu.nways; way++) {
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for (way = 0; way < config.immu.nways; way++) {
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PRINTF(" way %d: ", way);
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PRINTF(" way %d: ", way);
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PRINTF("%s\n", dump_spr(SPR_ITLBMR_BASE(way) + set,
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PRINTF("%s\n", dump_spr(SPR_ITLBMR_BASE(way) + set,
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set]));
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cpu_state.sprs[SPR_ITLBMR_BASE(way) + set]));
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PRINTF("%s\n", dump_spr(SPR_ITLBTR_BASE(way) + set,
|
PRINTF("%s\n", dump_spr(SPR_ITLBTR_BASE(way) + set,
|
cpu_state.sprs[SPR_ITLBTR_BASE(way) + set]));
|
cpu_state.sprs[SPR_ITLBTR_BASE(way) + set]));
|
}
|
}
|
}
|
}
|
if (start_set < end_set) PRINTF("\n");
|
if (start_set < end_set) PRINTF("\n");
|
}
|
}
|
|
|
/*---------------------------------------------------[ IMMU configuration ]---*/
|
/*---------------------------------------------------[ IMMU configuration ]---*/
|
void immu_enabled(union param_val val, void *dat)
|
void immu_enabled(union param_val val, void *dat)
|
{
|
{
|
if(val.int_val)
|
if(val.int_val)
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
|
cpu_state.sprs[SPR_UPR] |= SPR_UPR_IMP;
|
else
|
else
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
|
cpu_state.sprs[SPR_UPR] &= ~SPR_UPR_IMP;
|
config.immu.enabled = val.int_val;
|
config.immu.enabled = val.int_val;
|
}
|
}
|
|
|
void immu_nsets(union param_val val, void *dat)
|
void immu_nsets(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
if (is_power2(val.int_val) && val.int_val <= 256) {
|
config.immu.nsets = val.int_val;
|
config.immu.nsets = val.int_val;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTS;
|
cpu_state.sprs[SPR_IMMUCFGR] |= log2(val.int_val) << 3;
|
cpu_state.sprs[SPR_IMMUCFGR] |= log2_int(val.int_val) << 3;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
CONFIG_ERROR("value of power of two and lower or equal than 256 expected.");
|
}
|
}
|
|
|
void immu_nways(union param_val val, void *dat)
|
void immu_nways(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
if (val.int_val >= 1 && val.int_val <= 4) {
|
config.immu.nways = val.int_val;
|
config.immu.nways = val.int_val;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
|
cpu_state.sprs[SPR_IMMUCFGR] &= ~SPR_IMMUCFGR_NTW;
|
cpu_state.sprs[SPR_IMMUCFGR] |= val.int_val - 1;
|
cpu_state.sprs[SPR_IMMUCFGR] |= val.int_val - 1;
|
}
|
}
|
else
|
else
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
CONFIG_ERROR("value 1, 2, 3 or 4 expected.");
|
}
|
}
|
|
|
void immu_pagesize(union param_val val, void *dat)
|
void immu_pagesize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.immu.pagesize = val.int_val;
|
config.immu.pagesize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void immu_entrysize(union param_val val, void *dat)
|
void immu_entrysize(union param_val val, void *dat)
|
{
|
{
|
if (is_power2(val.int_val))
|
if (is_power2(val.int_val))
|
config.immu.entrysize = val.int_val;
|
config.immu.entrysize = val.int_val;
|
else
|
else
|
CONFIG_ERROR("value of power of two expected.");
|
CONFIG_ERROR("value of power of two expected.");
|
}
|
}
|
|
|
void immu_ustates(union param_val val, void *dat)
|
void immu_ustates(union param_val val, void *dat)
|
{
|
{
|
if (val.int_val >= 2 && val.int_val <= 4)
|
if (val.int_val >= 2 && val.int_val <= 4)
|
config.immu.ustates = val.int_val;
|
config.immu.ustates = val.int_val;
|
else
|
else
|
CONFIG_ERROR("invalid USTATE.");
|
CONFIG_ERROR("invalid USTATE.");
|
}
|
}
|
|
|
void immu_missdelay(union param_val val, void *dat)
|
void immu_missdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.missdelay = val.int_val;
|
config.immu.missdelay = val.int_val;
|
}
|
}
|
|
|
void immu_hitdelay(union param_val val, void *dat)
|
void immu_hitdelay(union param_val val, void *dat)
|
{
|
{
|
config.immu.hitdelay = val.int_val;
|
config.immu.hitdelay = val.int_val;
|
}
|
}
|
|
|
void reg_immu_sec(void)
|
void reg_immu_sec(void)
|
{
|
{
|
struct config_section *sec = reg_config_sec("immu", NULL, NULL);
|
struct config_section *sec = reg_config_sec("immu", NULL, NULL);
|
|
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
reg_config_param(sec, "enabled", paramt_int, immu_enabled);
|
reg_config_param(sec, "nsets", paramt_int, immu_nsets);
|
reg_config_param(sec, "nsets", paramt_int, immu_nsets);
|
reg_config_param(sec, "nways", paramt_int, immu_nways);
|
reg_config_param(sec, "nways", paramt_int, immu_nways);
|
reg_config_param(sec, "pagesize", paramt_int, immu_pagesize);
|
reg_config_param(sec, "pagesize", paramt_int, immu_pagesize);
|
reg_config_param(sec, "entrysize", paramt_int, immu_entrysize);
|
reg_config_param(sec, "entrysize", paramt_int, immu_entrysize);
|
reg_config_param(sec, "ustates", paramt_int, immu_ustates);
|
reg_config_param(sec, "ustates", paramt_int, immu_ustates);
|
reg_config_param(sec, "missdelay", paramt_int, immu_missdelay);
|
reg_config_param(sec, "missdelay", paramt_int, immu_missdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, immu_hitdelay);
|
reg_config_param(sec, "hitdelay", paramt_int, immu_hitdelay);
|
}
|
}
|
|
|
