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/* sim.cfg -- Simulator configuration script file
/* sim.cfg -- Simulator configuration script file
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
   Copyright (C) 2001-2002, Marko Mlinar, markom@opencores.org
This file is part of OpenRISC 1000 Architectural Simulator.
This file is part of OpenRISC 1000 Architectural Simulator.
It contains the default configuration and help about configuring
It contains the default configuration and help about configuring
the simulator.
the simulator.
This program is free software; you can redistribute it and/or modify
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
the Free Software Foundation; either version 2 of the License, or
(at your option) any later version.
(at your option) any later version.
This program is distributed in the hope that it will be useful,
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
GNU General Public License for more details.
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
You should have received a copy of the GNU General Public License
along with this program; if not, write to the Free Software
along with this program; if not, write to the Free Software
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
/* INTRODUCTION
/* INTRODUCTION
   The ork1sim has various parameters, that are set in configuration files
   The ork1sim has various parameters, that are set in configuration files
   like this one. The user can switch between configurations at startup by
   like this one. The user can switch between configurations at startup by
   specifying the required configuration file with the -f  option.
   specifying the required configuration file with the -f  option.
   If no configuration file is specified or1ksim searches for the default
   If no configuration file is specified or1ksim searches for the default
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
   configuration file sim.cfg. First it searches for './sim.cfg'. If this
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
   file is not found, it searches for '~/or1k/sim.cfg'. If this file is
   not found too, it reverts to the built-in default configuration.
   not found too, it reverts to the built-in default configuration.
   NOTE: Users should not rely on the built-in configuration, since the
   NOTE: Users should not rely on the built-in configuration, since the
         default configuration may differ between version.
         default configuration may differ between version.
         Rather create a configuration file that sets all critical values.
         Rather create a configuration file that sets all critical values.
   This file may contain (standard C) comments only - no // support.
   This file may contain (standard C) comments only - no // support.
   Configure files may be be included, using:
   Configure files may be be included, using:
   include "file_name_to_include"
   include "file_name_to_include"
   Like normal configuration files, the included file is divided into
   Like normal configuration files, the included file is divided into
   sections. Each section is described in detail also.
   sections. Each section is described in detail also.
   Some section have subsections. One example of such a subsection is:
   Some section have subsections. One example of such a subsection is:
   device 
   device 
     instance specific parameters...
     instance specific parameters...
   enddevice
   enddevice
   which creates a device instance.
   which creates a device instance.
*/
*/
/* MEMORY SECTION
/* MEMORY SECTION
   This section specifies how the memory is generated and the blocks
   This section specifies how the memory is generated and the blocks
   it consists of.
   it consists of.
   type = random/unknown/pattern
   type = random/unknown/pattern
      Specifies the initial memory values.
      Specifies the initial memory values.
      'random' generates random memory using seed 'random_seed'.
      'random' generates random memory using seed 'random_seed'.
      'pattern' fills memory with 'pattern'.
      'pattern' fills memory with 'pattern'.
      'unknown' does not specify how memory should be generated,
      'unknown' does not specify how memory should be generated,
      leaving the memory in a undefined state. This is the fastest
      leaving the memory in a undefined state. This is the fastest
      option.
      option.
   random_seed = 
   random_seed = 
      random seed for randomizer, used if type = 'random'.
      random seed for randomizer, used if type = 'random'.
   pattern = 
   pattern = 
      pattern to fill memory, used if type = 'pattern'.
      pattern to fill memory, used if type = 'pattern'.
   nmemories = 
   nmemories = 
      number of memory instances connected
      number of memory instances connected
   baseaddr = 
   baseaddr = 
      memory start address
      memory start address
   size = 
   size = 
      memory size
      memory size
   name = ""
   name = ""
      memory block name
      memory block name
   ce = 
   ce = 
      chip enable index of the memory instance
      chip enable index of the memory instance
   mc = 
   mc = 
      memory controller this memory is connected to
      memory controller this memory is connected to
   delayr = 
   delayr = 
      cycles, required for read access, -1 if instance does not support reading
      cycles, required for read access, -1 if instance does not support reading
   delayw = 
   delayw = 
      cycles, required for write access, -1 if instance does not support writing
      cycles, required for write access, -1 if instance does not support writing
   log = ""
   log = ""
      filename, where to log memory accesses to, no log, if log command is not specified
      filename, where to log memory accesses to, no log, if log command is not specified
*/
*/
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  name = "FLASH"
  name = "FLASH"
  ce = 0
  ce = 0
  mc = 0
  mc = 0
  baseaddr = 0xf0000000
  baseaddr = 0xf0000000
  size = 0x00800000
  size = 0x00800000
  delayr = 10
  delayr = 10
  delayw = -1
  delayw = -1
end
end
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  name = "RAM"
  name = "RAM"
  ce = 1
  ce = 1
  mc = 0
  mc = 0
  baseaddr = 0x00000000
  baseaddr = 0x00000000
  size = 0x00400000
  size = 0x00400000
  delayr = 1
  delayr = 1
  delayw = 2
  delayw = 2
end
end
section memory
section memory
  /*random_seed = 12345
  /*random_seed = 12345
  type = random*/
  type = random*/
  pattern = 0x00
  pattern = 0x00
  type = unknown /* Fastest */
  type = unknown /* Fastest */
  name = "SRAM"
  name = "SRAM"
  mc = 0
  mc = 0
  ce = 2
  ce = 2
  baseaddr = 0x08000000
  baseaddr = 0x08000000
  size = 0x00400000
  size = 0x00400000
  delayr = 1
  delayr = 1
  delayw = 2
  delayw = 2
end
end
/* IMMU SECTION
/* IMMU SECTION
    This section configures the Instruction Memory Manangement Unit
    This section configures the Instruction Memory Manangement Unit
    enabled = 0/1
    enabled = 0/1
       '0': disabled
       '0': disabled
       '1': enabled
       '1': enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of ITLB sets; must be power of two
       number of ITLB sets; must be power of two
    nways = 
    nways = 
       number of ITLB ways
       number of ITLB ways
    pagesize = 
    pagesize = 
       instruction page size; must be power of two
       instruction page size; must be power of two
    entrysize = 
    entrysize = 
       instruction entry size in bytes
       instruction entry size in bytes
    ustates = 
    ustates = 
       number of ITLB usage states (2, 3, 4 etc., max is 4)
       number of ITLB usage states (2, 3, 4 etc., max is 4)
    hitdelay = 
    hitdelay = 
       number of cycles immu hit costs
       number of cycles immu hit costs
    missdelay = 
    missdelay = 
       number of cycles immu miss costs
       number of cycles immu miss costs
*/
*/
section immu
section immu
  enabled = 1
  enabled = 1
  nsets = 64
  nsets = 64
  nways = 1
  nways = 1
  pagesize = 8192
  pagesize = 8192
  hitdelay = 0
  hitdelay = 0
  missdelay = 0
  missdelay = 0
end
end
/* DMMU SECTION
/* DMMU SECTION
    This section configures the Data Memory Manangement Unit
    This section configures the Data Memory Manangement Unit
    enabled = 0/1
    enabled = 0/1
       '0': disabled
       '0': disabled
       '1': enabled
       '1': enabled
       (NOTE: UPR bit is set)
       (NOTE: UPR bit is set)
    nsets = 
    nsets = 
       number of DTLB sets; must be power of two
       number of DTLB sets; must be power of two
    nways = 
    nways = 
       number of DTLB ways
       number of DTLB ways
    pagesize = 
    pagesize = 
       data page size; must be power of two
       data page size; must be power of two
    entrysize = 
    entrysize = 
       data entry size in bytes
       data entry size in bytes
    ustates = 
    ustates = 
       number of DTLB usage states (2, 3, 4 etc., max is 4)
       number of DTLB usage states (2, 3, 4 etc., max is 4)
    hitdelay = 
    hitdelay = 
       number of cycles dmmu hit costs
       number of cycles dmmu hit costs
    missdelay = 
    missdelay = 
       number of cycles dmmu miss costs
       number of cycles dmmu miss costs
*/
*/
section dmmu
section dmmu
  enabled = 1
  enabled = 1
  nsets = 64
  nsets = 64
  nways = 1
  nways = 1
  pagesize = 8192
  pagesize = 8192
  hitdelay = 0
  hitdelay = 0
  missdelay = 0
  missdelay = 0
end
end
/* IC SECTION
/* IC SECTION
   This section configures the Instruction Cache
   This section configures the Instruction Cache
   enabled = 0/1
   enabled = 0/1
       '0': disabled
       '0': disabled
       '1': enabled
       '1': enabled
      (NOTE: UPR bit is set)
      (NOTE: UPR bit is set)
   nsets = 
   nsets = 
      number of IC sets; must be power of two
      number of IC sets; must be power of two
   nways = 
   nways = 
      number of IC ways
      number of IC ways
   blocksize = 
   blocksize = 
      IC block size in bytes; must be power of two
      IC block size in bytes; must be power of two
   ustates = 
   ustates = 
      number of IC usage states (2, 3, 4 etc., max is 4)
      number of IC usage states (2, 3, 4 etc., max is 4)
   hitdelay = 
   hitdelay = 
      number of cycles ic hit costs
      number of cycles ic hit costs
    missdelay = 
    missdelay = 
      number of cycles ic miss costs
      number of cycles ic miss costs
*/
*/
section ic
section ic
  enabled = 1
  enabled = 1
  nsets = 256
  nsets = 256
  nways = 1
  nways = 1
  blocksize = 16
  blocksize = 16
  hitdelay = 0
  hitdelay = 0
  missdelay = 0
  missdelay = 0
end
end
/* DC SECTION
/* DC SECTION
   This section configures the Data Cache
   This section configures the Data Cache
   enabled = 0/1
   enabled = 0/1
       '0': disabled
       '0': disabled
       '1': enabled
       '1': enabled
      (NOTE: UPR bit is set)
      (NOTE: UPR bit is set)
   nsets = 
   nsets = 
      number of DC sets; must be power of two
      number of DC sets; must be power of two
   nways = 
   nways = 
      number of DC ways
      number of DC ways
   blocksize = 
   blocksize = 
      DC block size in bytes; must be power of two
      DC block size in bytes; must be power of two
   ustates = 
   ustates = 
      number of DC usage states (2, 3, 4 etc., max is 4)
      number of DC usage states (2, 3, 4 etc., max is 4)
   load_hitdelay = 
   load_hitdelay = 
      number of cycles dc load hit costs
      number of cycles dc load hit costs
   load_missdelay = 
   load_missdelay = 
      number of cycles dc load miss costs
      number of cycles dc load miss costs
   store_hitdelay = 
   store_hitdelay = 
      number of cycles dc load hit costs
      number of cycles dc load hit costs
   store_missdelay = 
   store_missdelay = 
      number of cycles dc load miss costs
      number of cycles dc load miss costs
*/
*/
section dc
section dc
  enabled = 1
  enabled = 1
  nsets = 256
  nsets = 256
  nways = 1
  nways = 1
  blocksize = 16
  blocksize = 16
  load_hitdelay = 0
  load_hitdelay = 0
  load_missdelay = 0
  load_missdelay = 0
  store_hitdelay = 0
  store_hitdelay = 0
  store_missdelay = 0
  store_missdelay = 0
end
end
/* SIM SECTION
/* SIM SECTION
  This section specifies how or1ksim should behave.
  This section specifies how or1ksim should behave.
  verbose = 0/1
  verbose = 0/1
       '0': don't print extra messages
       '0': don't print extra messages
       '1': print extra messages
       '1': print extra messages
  debug = 0-9
  debug = 0-9
      0  : no debug messages
      0  : no debug messages
      1-9: debug message level.
      1-9: debug message level.
           higher numbers produce more messages
           higher numbers produce more messages
  profile = 0/1
  profile = 0/1
      '0': don't generate profiling file 'sim.profile'
      '0': don't generate profiling file 'sim.profile'
      '1': don't generate profiling file 'sim.profile'
      '1': don't generate profiling file 'sim.profile'
  prof_fn = ""
  prof_fn = ""
      optional filename for the profiling file.
      optional filename for the profiling file.
      valid only if 'profile' is set
      valid only if 'profile' is set
  mprofile = 0/1
  mprofile = 0/1
      '0': don't generate memory profiling file 'sim.mprofile'
      '0': don't generate memory profiling file 'sim.mprofile'
      '1': generate memory profiling file 'sim.mprofile'
      '1': generate memory profiling file 'sim.mprofile'
  mprof_fn = ""
  mprof_fn = ""
      optional filename for the memory profiling file.
      optional filename for the memory profiling file.
      valid only if 'mprofile' is set
      valid only if 'mprofile' is set
  history = 0/1
  history = 0/1
      '0': don't track execution flow
      '0': don't track execution flow
      '1': track execution flow
      '1': track execution flow
      Execution flow can be tracked for the simulator's
      Execution flow can be tracked for the simulator's
      'hist' command. Useful for back-trace debugging.
      'hist' command. Useful for back-trace debugging.
  iprompt = 0/1
  iprompt = 0/1
     '0': start in  (so what do we start in ???)
     '0': start in  (so what do we start in ???)
     '1': start in interactive prompt.
     '1': start in interactive prompt.
  exe_log = 0/1
  exe_log = 0/1
      '0': don't generate execution log.
      '0': don't generate execution log.
      '1': generate execution log.
      '1': generate execution log.
  exe_log = default/hardware/simple/software
  exe_log = default/hardware/simple/software
      type of execution log, default is used when not specified
      type of execution log, default is used when not specified
  exe_log_start = 
  exe_log_start = 
      index of first instruction to start logging, default = 0
      index of first instruction to start logging, default = 0
  exe_log_end = 
  exe_log_end = 
      index of last instruction to end logging; not limited, if omitted
      index of last instruction to end logging; not limited, if omitted
  exe_log_marker = 
  exe_log_marker = 
       specifies number of instructions before horizontal marker is
       specifies number of instructions before horizontal marker is
      printed; if zero, markers are disabled (default)
      printed; if zero, markers are disabled (default)
  exe_log_fn = ""
  exe_log_fn = ""
      filename for the exection log file.
      filename for the exection log file.
      valid only if 'exe_log' is set
      valid only if 'exe_log' is set
  clkcycle = [ps|ns|us|ms]
  clkcycle = [ps|ns|us|ms]
      specifies time measurement for one cycle
      specifies time measurement for one cycle
*/
*/
section sim
section sim
  /* verbose = 1 */
  /* verbose = 1 */
  debug = 0
  debug = 0
  profile = 0
  profile = 0
  prof_fn = "sim.profile"
  prof_fn = "sim.profile"
  history = 1
  history = 1
  /* iprompt = 0 */
  /* iprompt = 0 */
  exe_log = 0
  exe_log = 0
  exe_log_type = software
  exe_log_type = software
  exe_log_start = 0
  exe_log_start = 0
/*  exe_log_end = 20000000*/
/*  exe_log_end = 20000000*/
  exe_log_marker = 10000
  exe_log_marker = 10000
  exe_log_fn = "executed.log"
  exe_log_fn = "executed.log"
  clkcycle = 100ns
  clkcycle = 100ns
end
end
/* SECTION VAPI
/* SECTION VAPI
    This section configures the Verification API, used for Advanced
    This section configures the Verification API, used for Advanced
    Core Verification.
    Core Verification.
    enabled = 0/1
    enabled = 0/1
        '0': disbable VAPI server
        '0': disbable VAPI server
        '1': enable/start VAPI server
        '1': enable/start VAPI server
    server_port = 
    server_port = 
        TCP/IP port to start VAPI server on
        TCP/IP port to start VAPI server on
    log_enabled = 0/1
    log_enabled = 0/1
       '0': disable VAPI requests logging
       '0': disable VAPI requests logging
       '1': enable VAPI requests logging
       '1': enable VAPI requests logging
    hide_device_id = 0/1
    hide_device_id = 0/1
       '0': don't log device id (for compatability with old version)
       '0': don't log device id (for compatability with old version)
       '1': log device id
       '1': log device id
    vapi_fn = 
    vapi_fn = 
       filename for the log file.
       filename for the log file.
       valid only if log_enabled is set
       valid only if log_enabled is set
*/
*/
section VAPI
section VAPI
  enabled = 0
  enabled = 0
  server_port = 9998
  server_port = 9998
  log_enabled = 0
  log_enabled = 0
  vapi_log_fn = "vapi.log"
  vapi_log_fn = "vapi.log"
end
end
/* CPU SECTION
/* CPU SECTION
   This section specifies various CPU parameters.
   This section specifies various CPU parameters.
   ver = 
   ver = 
   rev = 
   rev = 
      specifies version and revision of the CPU used
      specifies version and revision of the CPU used
   upr = 
   upr = 
      changes the upr register
      changes the upr register
   sr = 
   sr = 
      sets the initial Supervision Register value
      sets the initial Supervision Register value
   superscalar = 0/1
   superscalar = 0/1
      '0': CPU is scalar
      '0': CPU is scalar
      '1': CPU is superscalar
      '1': CPU is superscalar
      (modify cpu/or32/execute.c to tune superscalar model)
      (modify cpu/or32/execute.c to tune superscalar model)
   hazards = 0/1
   hazards = 0/1
      '0': don't track data hazards in superscalar CPU
      '0': don't track data hazards in superscalar CPU
      '1': track data hazards in superscalar CPU
      '1': track data hazards in superscalar CPU
      If tracked, data hazards can be displayed using the
      If tracked, data hazards can be displayed using the
      simulator's 'r' command.
      simulator's 'r' command.
   dependstats = 0/1
   dependstats = 0/1
      '0': don't calculate inter-instruction dependencies.
      '0': don't calculate inter-instruction dependencies.
      '1': calculate inter-instruction dependencies.
      '1': calculate inter-instruction dependencies.
      If calculated, inter-instruction dependencies can be
      If calculated, inter-instruction dependencies can be
      displayed using the simulator's 'stat' command.
      displayed using the simulator's 'stat' command.
   sbuf_len = 
   sbuf_len = 
      length of store buffer (<= 256), 0 = disabled
      length of store buffer (<= 256), 0 = disabled
*/
*/
section cpu
section cpu
  ver = 0x1200
  ver = 0x1200
  rev = 0x0001
  rev = 0x0001
  /* upr = */
  /* upr = */
  superscalar = 0
  superscalar = 0
  hazards = 0
  hazards = 0
  dependstats = 0
  dependstats = 0
  sbuf_len = 0
  sbuf_len = 0
end
end
/* PM SECTION
/* PM SECTION
   This section specifies Power Management parameters
   This section specifies Power Management parameters
   enabled = 0/1
   enabled = 0/1
      '0': disable power management
      '0': disable power management
      '1': enable power management
      '1': enable power management
*/
*/
section pm
section pm
  enabled = 0
  enabled = 0
end
end
/* BPB SECTION
/* BPB SECTION
   This section specifies how branch prediction should behave.
   This section specifies how branch prediction should behave.
   enabled = 0/1
   enabled = 0/1
     '0': disable branch prediction
     '0': disable branch prediction
     '1': enable branch prediction
     '1': enable branch prediction
   btic = 0/1
   btic = 0/1
     '0': disable branch target instruction cache model
     '0': disable branch target instruction cache model
     '1': enable branch target instruction cache model
     '1': enable branch target instruction cache model
   sbp_bf_fwd = 0/1
   sbp_bf_fwd = 0/1
     Static branch prediction for 'l.bf'
     Static branch prediction for 'l.bf'
     '0': don't use forward prediction
     '0': don't use forward prediction
     '1': use forward prediction
     '1': use forward prediction
   sbp_bnf_fwd = 0/1
   sbp_bnf_fwd = 0/1
     Static branch prediction for 'l.bnf'
     Static branch prediction for 'l.bnf'
     '0': don't use forward prediction
     '0': don't use forward prediction
     '1': use forward prediction
     '1': use forward prediction
   hitdelay = 
   hitdelay = 
       number of cycles bpb hit costs
       number of cycles bpb hit costs
   missdelay = 
   missdelay = 
       number of cycles bpb miss costs
       number of cycles bpb miss costs
*/
*/
section bpb
section bpb
  enabled = 0
  enabled = 0
  btic = 0
  btic = 0
  sbp_bf_fwd = 0
  sbp_bf_fwd = 0
  sbp_bnf_fwd = 0
  sbp_bnf_fwd = 0
  hitdelay = 0
  hitdelay = 0
  missdelay = 0
  missdelay = 0
end
end
/* DEBUG SECTION
/* DEBUG SECTION
   This sections specifies how the debug unit should behave.
   This sections specifies how the debug unit should behave.
   enabled = 0/1
   enabled = 0/1
      '0': disable debug unit
      '0': disable debug unit
      '1': enable debug unit
      '1': enable debug unit
   gdb_enabled = 0/1
   gdb_enabled = 0/1
      '0': don't start gdb server
      '0': don't start gdb server
      '1': start gdb server at port 'server_port'
      '1': start gdb server at port 'server_port'
   server_port = 
   server_port = 
      TCP/IP port to start gdb server on
      TCP/IP port to start gdb server on
      valid only if gdb_enabled is set
      valid only if gdb_enabled is set
   vapi_id = 
   vapi_id = 
      Used to create "fake" vapi log file containing the JTAG proxy messages.
      Used to create "fake" vapi log file containing the JTAG proxy messages.
*/
*/
section debug
section debug
  enabled = 0
  enabled = 0
  gdb_enabled = 0
  gdb_enabled = 0
  server_port = 9999
  server_port = 9999
end
end
/* MC SECTION
/* MC SECTION
   This section configures the memory controller
   This section configures the memory controller
   enabled = 0/1
   enabled = 0/1
     '0': disable memory controller
     '0': disable memory controller
     '1': enable memory controller
     '1': enable memory controller
   baseaddr = 
   baseaddr = 
      address of first MC register
      address of first MC register
   POC = 
   POC = 
      Power On Configuration register
      Power On Configuration register
   index = 
   index = 
      Index of this memory controller amongst all the memory controllers
      Index of this memory controller amongst all the memory controllers
*/
*/
section mc
section mc
  enabled = 1
  enabled = 1
  baseaddr = 0x93000000
  baseaddr = 0x93000000
  POC = 0x00000008                 /* Power on configuration register */
  POC = 0x00000008                 /* Power on configuration register */
  index = 0
  index = 0
end
end
/* UART SECTION
/* UART SECTION
   This section configures the UARTs
   This section configures the UARTs
     enabled = <0|1>
     enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
     baseaddr = 
     baseaddr = 
        address of first UART register for this device
        address of first UART register for this device
     channel = :
     channel = :
        The channel parameter indicates the source of received UART characters
        The channel parameter indicates the source of received UART characters
        and the sink for transmitted UART characters.
        and the sink for transmitted UART characters.
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
        The  can be either "file", "xterm", "tcp", "fd", or "tty"
        (without quotes).
        (without quotes).
          A) To send/receive characters from a pair of files, use a file
          A) To send/receive characters from a pair of files, use a file
             channel:
             channel:
               channel=file:,
               channel=file:,
          B) To create an interactive terminal window, use an xterm channel:
          B) To create an interactive terminal window, use an xterm channel:
               channel=xterm:[]*
               channel=xterm:[]*
          C) To create a bidirectional tcp socket which one could, for example,
          C) To create a bidirectional tcp socket which one could, for example,
             access via telnet, use a tcp channel:
             access via telnet, use a tcp channel:
               channel=tcp:
               channel=tcp:
          D) To cause the UART to read/write from existing numeric file
          D) To cause the UART to read/write from existing numeric file
             descriptors, use an fd channel:
             descriptors, use an fd channel:
               channel=fd:,
               channel=fd:,
          E) To connect the UART to a physical serial port, create a tty
          E) To connect the UART to a physical serial port, create a tty
             channel:
             channel:
               channel=tty:device=/dev/ttyS0,baud=9600
               channel=tty:device=/dev/ttyS0,baud=9600
     irq = 
     irq = 
        irq number for this device
        irq number for this device
     16550 = 0/1
     16550 = 0/1
        '0': this device is a UART16450
        '0': this device is a UART16450
        '1': this device is a UART16550
        '1': this device is a UART16550
     jitter = 
     jitter = 
        in msecs... time to block, -1 to disable it
        in msecs... time to block, -1 to disable it
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section uart
section uart
  enabled = 1
  enabled = 1
  baseaddr = 0x90000000
  baseaddr = 0x90000000
  irq = 2
  irq = 2
  channel = "file:uart0.rx,uart0.tx"
  channel = "file:uart0.rx,uart0.tx"
  jitter = -1                     /* async behaviour */
  jitter = -1                     /* async behaviour */
  16550 = 1
  16550 = 1
end
end
/* DMA SECTION
/* DMA SECTION
   This section configures the DMAs
   This section configures the DMAs
     enabled = <0|1>
     enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
     baseaddr = 
     baseaddr = 
        address of first DMA register for this device
        address of first DMA register for this device
     irq = 
     irq = 
        irq number for this device
        irq number for this device
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section dma
section dma
  enabled = 1
  enabled = 1
  baseaddr = 0x9a000000
  baseaddr = 0x9a000000
  irq = 11
  irq = 11
end
end
/* ETHERNET SECTION
/* ETHERNET SECTION
   This section configures the ETHERNETs
   This section configures the ETHERNETs
     enabled = <0|1>
     enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
     baseaddr = 
     baseaddr = 
        address of first ethernet register for this device
        address of first ethernet register for this device
     dma = 
     dma = 
        which controller is this ethernet "connected" to
        which controller is this ethernet "connected" to
     irq = 
     irq = 
        ethernet mac IRQ level
        ethernet mac IRQ level
     rtx_type = 
     rtx_type = 
        use 0 - file interface, 1 - socket interface
        use 0 - file interface, 1 - socket interface
     rx_channel = 
     rx_channel = 
        DMA channel used for RX
        DMA channel used for RX
     tx_channel = 
     tx_channel = 
        DMA channel used for TX
        DMA channel used for TX
     rxfile = ""
     rxfile = ""
        filename, where to read data from
        filename, where to read data from
     txfile = ""
     txfile = ""
        filename, where to write data to
        filename, where to write data to
     sockif = ""
     sockif = ""
        interface name of ethernet socket
        interface name of ethernet socket
     vapi_id = 
     vapi_id = 
        VAPI id of this instance
        VAPI id of this instance
*/
*/
section ethernet
section ethernet
  enabled = 1
  enabled = 1
  baseaddr = 0x92000000
  baseaddr = 0x92000000
  dma = 0
  dma = 0
  irq = 4
  irq = 4
  rtx_type = 1
  rtx_type = 1
  tx_channel = 0
  tx_channel = 0
  rx_channel = 1
  rx_channel = 1
  rxfile = "eth0.rx"
  rxfile = "eth0.rx"
  txfile = "eth0.tx"
  txfile = "eth0.tx"
  sockif = "eth0"
  sockif = "eth0"
end
end
/* GPIO SECTION
/* GPIO SECTION
   This section configures the GPIOs
   This section configures the GPIOs
     enabled = <0|1>
     enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
     baseaddr = 
     baseaddr = 
        address of first GPIO register for this device
        address of first GPIO register for this device
     irq = 
     irq = 
        irq number for this device
        irq number for this device
     base_vapi_id = 
     base_vapi_id = 
        first VAPI id of this instance
        first VAPI id of this instance
        GPIO uses 8 consecutive VAPI IDs
        GPIO uses 8 consecutive VAPI IDs
*/
*/
section gpio
section gpio
  enabled = 1
  enabled = 1
  baseaddr = 0x91000000
  baseaddr = 0x91000000
  irq = 3
  irq = 3
  base_vapi_id = 0x0200
  base_vapi_id = 0x0200
end
end
/* VGA SECTION
/* VGA SECTION
    This section configures the VGA/LCD controller
    This section configures the VGA/LCD controller
      enabled = <0|1>
      enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
      baseaddr = 
      baseaddr = 
        address of first VGA register
        address of first VGA register
      irq = 
      irq = 
        irq number for this device
        irq number for this device
      refresh_rate = 
      refresh_rate = 
        number of cycles between screen dumps
        number of cycles between screen dumps
      filename = ""
      filename = ""
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
        template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
*/
section vga
section vga
  enabled = 1
  enabled = 1
  baseaddr = 0x97100000
  baseaddr = 0x97100000
  irq = 8
  irq = 8
  refresh_rate = 100000
  refresh_rate = 100000
  filename = "primary"
  filename = "primary"
end
end
/* TICK TIMER SECTION
/* TICK TIMER SECTION
    This section configures tick timer
    This section configures tick timer
    enabled = 0/1
    enabled = 0/1
      whether tick timer is enabled
      whether tick timer is enabled
    irq = 
    irq = 
      irq number
      irq number
*/
*/
/*
/*
section tick
section tick
  enabled = 1
  enabled = 1
  irq = 0
  irq = 0
end
end
*/
*/
/* FB SECTION
/* FB SECTION
    This section configures the frame buffer
    This section configures the frame buffer
    enabled = <0|1>
    enabled = <0|1>
      Enable/disable the peripheral.  By default if it is enabled.
      Enable/disable the peripheral.  By default if it is enabled.
    baseaddr = 
    baseaddr = 
      base address of frame buffer
      base address of frame buffer
    paladdr = 
    paladdr = 
      base address of first palette entry
      base address of first palette entry
    refresh_rate = 
    refresh_rate = 
      number of cycles between screen dumps
      number of cycles between screen dumps
    filename = ""
    filename = ""
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
      template name for generated names (e.g. "primary" produces "primary0023.bmp")
*/
*/
section fb
section fb
  enabled = 1
  enabled = 1
  baseaddr = 0x97000000
  baseaddr = 0x97000000
  refresh_rate = 1000000
  refresh_rate = 1000000
  filename = "primary"
  filename = "primary"
end
end
/* KBD SECTION
/* KBD SECTION
    This section configures the PS/2 compatible keyboard
    This section configures the PS/2 compatible keyboard
    baseaddr = 
    baseaddr = 
      base address of the keyboard device
      base address of the keyboard device
    rxfile = ""
    rxfile = ""
      filename, where to read data from
      filename, where to read data from
*/
*/
section kbd
section kbd
  enabled = 1
  enabled = 1
  irq = 5
  irq = 5
  baseaddr = 0x94000000
  baseaddr = 0x94000000
  rxfile = "kbd.rx"
  rxfile = "kbd.rx"
end
end
/* ATA SECTION
/* ATA SECTION
    This section configures the ATA/ATAPI host controller
    This section configures the ATA/ATAPI host controller
      baseaddr = 
      baseaddr = 
        address of first ATA register
        address of first ATA register
      enabled = <0|1>
      enabled = <0|1>
        Enable/disable the peripheral.  By default if it is enabled.
        Enable/disable the peripheral.  By default if it is enabled.
      irq = 
      irq = 
        irq number for this device
        irq number for this device
      dev_id = 1/2/3
      dev_id = 1/2/3
        Which OCIDEC version to imitate
        Which OCIDEC version to imitate
      rev = 
      rev = 
        Revision of OCIDEC
        Revision of OCIDEC
      pio_mode0_t1 = <0-255>
      pio_mode0_t1 = <0-255>
        PIO T1 reset value
        PIO T1 reset value
      pio_mode0_t2 = <0-255>
      pio_mode0_t2 = <0-255>
        PIO T2 reset value
        PIO T2 reset value
      pio_mode0_t4 = <0-255>
      pio_mode0_t4 = <0-255>
        PIO T4 reset value
        PIO T4 reset value
      pio_mode0_teoc = <0-255>
      pio_mode0_teoc = <0-255>
        PIO Teoc reset value
        PIO Teoc reset value
      dma_mode0_tm = <0-255>
      dma_mode0_tm = <0-255>
        DMA Tm reset value
        DMA Tm reset value
      dma_mode0_td = <0-255>
      dma_mode0_td = <0-255>
        DMA Td reset value
        DMA Td reset value
      dma_mode0_teoc = <0-255>
      dma_mode0_teoc = <0-255>
        DMA Teoc reset value
        DMA Teoc reset value
      Device specific
      Device specific
        type = 
        type = 
          ata device 0 type
          ata device 0 type
          0: NO_CONNECT: none (not connected)
          0: NO_CONNECT: none (not connected)
          1: FILE      : simulated harddisk
          1: FILE      : simulated harddisk
          2: LOCAL     : local system harddisk
          2: LOCAL     : local system harddisk
        file = ""
        file = ""
          filename for simulated ATA device
          filename for simulated ATA device
          valid only if dev_type0 == 1
          valid only if dev_type0 == 1
        size = 
        size = 
          size of simulated hard-disk (in MBytes)
          size of simulated hard-disk (in MBytes)
          valid only if dev_type0 == 1
          valid only if dev_type0 == 1
        packet = 
        packet = 
          0: simulated ATA device does NOT implement PACKET command feature set
          0: simulated ATA device does NOT implement PACKET command feature set
          1: simulated ATA device does implement PACKET command feature set
          1: simulated ATA device does implement PACKET command feature set
 
 
 
        firmware = 
 
          Firmware to report in `Identify device command'
 
 
 
        heads = 
 
          Number of default heads (-1)
 
 
 
        sectors = 
 
          Number of default sectors per track
 
 
 
        mwdma = 
 
          The highest multiword DMA mode; 2, 1, 0, -1 (No DMA)
 
 
 
        pio = 
 
          The highest supported pio mode; 4, 3, 2, 1, 0
 
 
   FIXME: irq number
   FIXME: irq number
*/
*/
section ata
section ata
  enabled = 1
  enabled = 1
  baseaddr = 0x9e000000
  baseaddr = 0x9e000000
  irq = 15
  irq = 15
  dev_id = 1
  dev_id = 1
  rev = 0
  rev = 0
  pio_mode0_t1 = 6
  pio_mode0_t1 = 6
  pio_mode0_t2 = 28
  pio_mode0_t2 = 28
  pio_mode0_t4 = 2
  pio_mode0_t4 = 2
  pio_mode0_teoc = 23
  pio_mode0_teoc = 23
  dma_mode0_tm = 4
  dma_mode0_tm = 4
  dma_mode0_td = 21
  dma_mode0_td = 21
  dma_mode0_teoc = 21
  dma_mode0_teoc = 21
  device 0
  device 0
    type   = 1
    type   = 1
    file   = "/tmp/sim_atadev0"
    file   = "/tmp/sim_atadev0"
    size   = 1
    size   = 1
    packet = 0
    packet = 0
 
 
 
    heads  = 7
 
    sectors = 32
 
 
 
    firmware = "02207031"
 
    mwdma = 2
 
    pio = 4
  enddevice
  enddevice
  device 1
  device 1
    type   = 0
    type   = 0
    file   = ""
    file   = ""
    size   = 0
    size   = 0
    packet = 0
    packet = 0
  enddevice
  enddevice
end
end
/* CUC SECTION
/* CUC SECTION
    This section configures the OpenRISC Custom Unit Compiler
    This section configures the OpenRISC Custom Unit Compiler
    memory_order = none/weak/strong/exact
    memory_order = none/weak/strong/exact
      none   different memory ordering, even if there are dependencies,
      none   different memory ordering, even if there are dependencies,
             burst can be made, width can change
             burst can be made, width can change
      weak   different memory ordering, if there cannot be dependencies
      weak   different memory ordering, if there cannot be dependencies
             burst can be made, width can change
             burst can be made, width can change
      strong same memory ordering, burst can be made, width can change
      strong same memory ordering, burst can be made, width can change
      exact  exacltly the same memory ordering and widths
      exact  exacltly the same memory ordering and widths
    calling_convention = 0/1
    calling_convention = 0/1
      whether programs follow OpenRISC calling conventions
      whether programs follow OpenRISC calling conventions
    enable_bursts = 0/1
    enable_bursts = 0/1
      whether burst are detected
      whether burst are detected
    no_multicycle = 0/1
    no_multicycle = 0/1
      if selected no multicycle logic paths will be generated
      if selected no multicycle logic paths will be generated
    timings_fn = ""
    timings_fn = ""
*/
*/
section cuc
section cuc
  memory_order = weak
  memory_order = weak
  calling_convention = 1
  calling_convention = 1
  enable_bursts = 1
  enable_bursts = 1
  no_multicycle = 1
  no_multicycle = 1
  timings_fn = "virtex.tim"
  timings_fn = "virtex.tim"
end
end
 
 

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