/*
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/*
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ata.c -- ATA driver
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ata.c -- ATA driver
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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Copyright (C) 2002 Richard Herveille, rherveille@opencores.org
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This file is part of OpenRISC 1000 Reference Platform Monitor (ORPmon)
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This file is part of OpenRISC 1000 Reference Platform Monitor (ORPmon)
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This program is free software; you can redistribute it and/or modify
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version
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(at your option) any later version
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This program is distributed in the hope that it will be useful,
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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*/
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#include <string.h>
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#include <string.h>
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/* get prototype for 'printf'
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/* get prototype for 'printf'
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get IN_CLOCK (from 'board.h')
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get IN_CLOCK (from 'board.h')
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*/
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*/
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#include "common.h"
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#include "common.h"
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#include "ata.h"
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#include "ata.h"
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/*
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/*
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static constants (yuck, yuck, yuck)
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static constants (yuck, yuck, yuck)
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*/
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*/
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static int usage[2] = {0, 0};
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static int usage[2] = {0, 0};
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static int hardsect_size[2] = {512, 512};
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static int hardsect_size[2] = {512, 512};
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static int current_pio_mode = 9999;
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static int current_pio_mode = 9999;
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|
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/*
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/*
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local defines
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local defines
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*/
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*/
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#define TYPE(devid) (devid >> 4)
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#define TYPE(devid) (devid >> 4)
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#define REV(devid) (devid & 0xf)
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#define REV(devid) (devid & 0xf)
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#define BASE(inode) ( (unsigned long) (MAJOR(inode->i_rdev) << 24) )
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#define BASE(inode) ( (unsigned long) (MAJOR(inode->i_rdev) << 24) )
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#define DEVICE(inode) ( MINOR(inode->i_rdev) )
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#define DEVICE(inode) ( MINOR(inode->i_rdev) )
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#define IN_CLK_MHZ (IN_CLK / 1000000)
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#define IN_CLK_MHZ (IN_CLK / 1000000)
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#define TO_TICKS(time) ( ((time + (IN_CLK_MHZ >> 1)) / IN_CLK_MHZ) -1 )
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#define TO_TICKS(time) ( ((time + (IN_CLK_MHZ >> 1)) / IN_CLK_MHZ) -1 )
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/*
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/*
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A T A _ O P E N
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A T A _ O P E N
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opens ata device;
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opens ata device;
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- identifies ata-device-id
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- identifies ata-device-id
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- programs ata-host
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- programs ata-host
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MAJOR: atahost identification (base address)
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MAJOR: atahost identification (base address)
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MINOR: atadevice identification (MSB=0: device0, MSB=1: device1)
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MINOR: atadevice identification (MSB=0: device0, MSB=1: device1)
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*/
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*/
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int ata_open(struct inode *inode, struct file *filp)
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int ata_open(struct inode *inode, struct file *filp)
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{
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{
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unsigned int atahost, device;
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unsigned int atahost, device;
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unsigned short buf[256];
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unsigned short buf[256];
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unsigned short dev_pio;
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unsigned short dev_pio;
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unsigned long sectors;
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unsigned long sectors;
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char txt[41];
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char txt[41];
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printf( "Checking device-id\n" );
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printf( "Checking device-id\n" );
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/* check device-id (MINOR number) */
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/* check device-id (MINOR number) */
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if ( (device = DEVICE(inode)) > 1 )
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if ( (device = DEVICE(inode)) > 1 )
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return EOPENIDEV;
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return EOPENIDEV;
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printf( "Searching for hostcontroller: " );
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printf( "Searching for hostcontroller: " );
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/* get atahost id */
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/* get atahost id */
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atahost = ata_ioctl(inode, filp, ATA_IOCTL_IDENTIFY_HOST, 0);
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atahost = ata_ioctl(inode, filp, ATA_IOCTL_IDENTIFY_HOST, 0);
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if (atahost)
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if (atahost)
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{
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{
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printf( "OCIDEC-%1d, revision 0x%02X found at 0x%08lX.\n", TYPE(atahost), REV(atahost), BASE(inode) );
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printf( "OCIDEC-%1d, revision 0x%02X found at 0x%08lX.\n", TYPE(atahost), REV(atahost), BASE(inode) );
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}
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}
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else
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else
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{
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{
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printf( "No OCIDEC device found.\n" );
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printf( "No OCIDEC device found.\n" );
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return EOPENIHOST;
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return EOPENIHOST;
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}
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}
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/* check if the host has been opened already */
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/* check if the host has been opened already */
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if (!usage[device]++)
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if (!usage[device]++)
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{
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{
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printf( "Opening device for the first time\n" );
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printf( "Opening device for the first time\n" );
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/* no, take device out of reset */
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/* no, take device out of reset */
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, CLR | ARG_HW_RST);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, CLR | ARG_HW_RST);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, CLR | ARG_SW_RST);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, CLR | ARG_SW_RST);
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/* program PIO timing registers (set to PIO mode 0) */
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/* program PIO timing registers (set to PIO mode 0) */
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO0);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO0);
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/* enable host controller (for old OCIDEC cores) */
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/* enable host controller (for old OCIDEC cores) */
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ata_ioctl(inode, filp, ATA_IOCTL_ENABLE_HOST, 0);
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ata_ioctl(inode, filp, ATA_IOCTL_ENABLE_HOST, 0);
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}
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}
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/* select requested device */
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/* select requested device */
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ata_ioctl(inode, filp, ATA_IOCTL_SELECT_DEVICE, 0);
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ata_ioctl(inode, filp, ATA_IOCTL_SELECT_DEVICE, 0);
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printf( "Executing IdentifyDevice command\n" );
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printf( "Executing IdentifyDevice command\n" );
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/* identify requested ata-devices */
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/* identify requested ata-devices */
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ata_ioctl(inode, filp, ATA_IOCTL_EXEC_CMD, IDENTIFY_DEVICE);
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ata_ioctl(inode, filp, ATA_IOCTL_EXEC_CMD, IDENTIFY_DEVICE);
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/* read block from ata-device */
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/* read block from ata-device */
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buf[0] = 256;
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buf[0] = 256;
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ata_ioctl(inode, filp, ATA_IOCTL_READ, (unsigned long) buf);
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ata_ioctl(inode, filp, ATA_IOCTL_READ, (unsigned long) buf);
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/* check if a valid device was found */
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/* check if a valid device was found */
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/* bit 15 in identify_device word0 must be '0',
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/* bit 15 in identify_device word0 must be '0',
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or be equal to 0x848a (CFA feature set) */
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or be equal to 0x848a (CFA feature set) */
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if ( (buf[0] & 0x8000) && (buf[0] != 0x848a) )
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if ( (buf[0] & 0x8000) && (buf[0] != 0x848a) )
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{
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{
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ata_release(inode, filp);
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ata_release(inode, filp);
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return EOPENNODEV;
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return EOPENNODEV;
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}
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}
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/* Then check specific configuration word */
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/* Then check specific configuration word */
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if (buf[0] == 0x848a)
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if (buf[0] == 0x848a)
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printf( "Found CompactFLASH device.\n" );
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printf( "Found CompactFLASH device.\n" );
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else
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else
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switch(buf[2]) {
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switch(buf[2]) {
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case 0x37c8:
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case 0x37c8:
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/* device does require SET_FEATURES
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/* device does require SET_FEATURES
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IDENTIFY_DEVICE response is incomplete */
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IDENTIFY_DEVICE response is incomplete */
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case 0x738c:
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case 0x738c:
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/* device does require SET_FEATURES
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/* device does require SET_FEATURES
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IDENTIFY_DEVICE response is complete */
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IDENTIFY_DEVICE response is complete */
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ata_ioctl(inode, filp, ATA_IOCTL_SET_FEATURES, 0); //FIXME
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ata_ioctl(inode, filp, ATA_IOCTL_SET_FEATURES, 0); //FIXME
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break;
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break;
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case 0x8c73:
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case 0x8c73:
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/* device does not require SET_FEATURES
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/* device does not require SET_FEATURES
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IDENTIFY_DEVICE response is incomplete */
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IDENTIFY_DEVICE response is incomplete */
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case 0xc837:
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case 0xc837:
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/* device does not require SET_FEATURES
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/* device does not require SET_FEATURES
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IDENTIFY_DEVICE response is complete */
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IDENTIFY_DEVICE response is complete */
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break;
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break;
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default:
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default:
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ata_release(inode, filp);
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ata_release(inode, filp);
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return EOPENNODEV;
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return EOPENNODEV;
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}
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}
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/* checks ok */
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/* checks ok */
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/* display device model, serialnumber, and firmware revision */
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/* display device model, serialnumber, and firmware revision */
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memcpy(txt, &buf[27], 40);
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memcpy(txt, &buf[27], 40);
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txt[40] = '\0';
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txt[40] = '\0';
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printf( "Model : %s\n", txt );
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printf( "Model : %s\n", txt );
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memcpy(txt, &buf[10], 20);
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memcpy(txt, &buf[10], 20);
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txt[20] = '\0';
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txt[20] = '\0';
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printf( "Serial : %s\n", txt );
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printf( "Serial : %s\n", txt );
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memcpy( txt, &buf[23], 8);
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memcpy( txt, &buf[23], 8);
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txt[8] = '\0';
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txt[8] = '\0';
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printf( "Firmware rev: %s\n", txt );
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printf( "Firmware rev: %s\n", txt );
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/* display size in MBytes */
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/* display size in MBytes */
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sectors = (buf[61] << 16) | buf[60];
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sectors = (buf[61] << 16) | buf[60];
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printf( " %ld MBytes ", sectors >> 11 ); /* assuming 512bytes per sector */
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printf( " %ld MBytes ", sectors >> 11 ); /* assuming 512bytes per sector */
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/* get supported pio modes */
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/* get supported pio modes */
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dev_pio = buf[64];
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dev_pio = buf[64];
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/* program ocidec timing registers to highest possible pio mode */
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/* program ocidec timing registers to highest possible pio mode */
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if (dev_pio & PIO4)
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if (dev_pio & PIO4)
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{
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{
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printf("PIO-4 supported\n");
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printf("PIO-4 supported\n");
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO4);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO4);
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}
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}
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else if (dev_pio & PIO3)
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else if (dev_pio & PIO3)
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{
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{
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printf("PIO-3 supported\n");
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printf("PIO-3 supported\n");
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO3);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO3);
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}
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}
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else
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else
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{
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{
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printf("PIO-2 supported\n");
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printf("PIO-2 supported\n");
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO2);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_PIO, ARG_PIO2);
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}
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}
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return 0;
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return 0;
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}
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}
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/*
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/*
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A T A _ R E L E A S E
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A T A _ R E L E A S E
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closes ata device;
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closes ata device;
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*/
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*/
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int ata_release(struct inode *inode, struct file *filp)
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int ata_release(struct inode *inode, struct file *filp)
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{
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{
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/* decrease usage count */
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/* decrease usage count */
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if (!--usage[DEVICE(inode)])
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if (!--usage[DEVICE(inode)])
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{
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{
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/* reset atahost */
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/* reset atahost */
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, SET | ARG_HW_RST);
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ata_ioctl(inode, filp, ATA_IOCTL_SET_RST, SET | ARG_HW_RST);
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}
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}
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return 0;
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return 0;
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}
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}
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/*
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/*
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A T A _ R E A D _ D P O R T
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A T A _ R E A D _ D P O R T
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|
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closes ata device;
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closes ata device;
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*/
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*/
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int ata_read_dport(unsigned long base)
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int ata_read_dport(unsigned long base)
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{
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{
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/* device ready to transfer data ?? */
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/* device ready to transfer data ?? */
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while ( !ata_dev_datrdy(base) );
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while ( !ata_dev_datrdy(base) );
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return REG32(base + ATA_DR);
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return REG32(base + ATA_DR);
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}
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}
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/*
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/*
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A T A _ I O C T L
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A T A _ I O C T L
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*/
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*/
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int ata_ioctl(struct inode *inode, struct file *filp, unsigned command, unsigned long argument)
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int ata_ioctl(struct inode *inode, struct file *filp, unsigned command, unsigned long argument)
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{
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{
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unsigned long base = BASE(inode);
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unsigned long base = BASE(inode);
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switch (command)
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switch (command)
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{
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{
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case ATA_IOCTL_ENABLE_HOST:
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case ATA_IOCTL_ENABLE_HOST:
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/* enables the ATA host controller (sets IDE_EN bit) */
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/* enables the ATA host controller (sets IDE_EN bit) */
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{
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{
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REG32(base + ATA_CTRL) |= ATA_IDE_EN;
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REG32(base + ATA_CTRL) |= ATA_IDE_EN;
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return 0;
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return 0;
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}
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}
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case ATA_IOCTL_EXEC_CMD:
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case ATA_IOCTL_EXEC_CMD:
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/* sends a command to the ATA device */
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/* sends a command to the ATA device */
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{
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{
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while( ata_dev_busy(base) ); // wait for device ready
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while( ata_dev_busy(base) ); // wait for device ready
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ata_cmd(base) = argument & 0xff;
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ata_cmd(base) = argument & 0xff;
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return 0;
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return 0;
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}
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}
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case ATA_IOCTL_READ:
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case ATA_IOCTL_READ:
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{
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{
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unsigned short *buf_ptr = (short *)argument;
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unsigned short *buf_ptr = (short *)argument;
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int n, cnt;
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int n, cnt;
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|
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cnt = buf_ptr[0];
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cnt = buf_ptr[0];
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for (n=0; n < cnt; n++)
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for (n=0; n < cnt; n++)
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{
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{
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while( !ata_dev_datrdy(base) ); // wait for data
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while( !ata_dev_datrdy(base) ); // wait for data
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*buf_ptr++ = ata_read_dport(base); // read data
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*buf_ptr++ = ata_read_dport(base); // read data
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}
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}
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|
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return 0;
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return 0;
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}
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}
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|
|
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case ATA_IOCTL_IDENTIFY_HOST:
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case ATA_IOCTL_IDENTIFY_HOST:
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/* reads OCIDEC status register configuration bits */
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/* reads OCIDEC status register configuration bits */
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return (REG32(base + ATA_STAT) >> 24);
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return (REG32(base + ATA_STAT) >> 24);
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|
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case ATA_IOCTL_SELECT_DEVICE:
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case ATA_IOCTL_SELECT_DEVICE:
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/* selects ATA device */
|
/* selects ATA device */
|
{
|
{
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while( ata_dev_busy(base) ); // wait for device ready
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while( ata_dev_busy(base) ); // wait for device ready
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|
|
/* sets the DEV bit in the device/head register */
|
/* sets the DEV bit in the device/head register */
|
if ( DEVICE(inode) )
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if ( DEVICE(inode) )
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REG32(base + ATA_DHR) |= ATA_DHR_DEV; /* select device1 */
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REG32(base + ATA_DHR) |= ATA_DHR_DEV; /* select device1 */
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else
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else
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REG32(base + ATA_DHR) &= ~ATA_DHR_DEV; /* select device0 */
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REG32(base + ATA_DHR) &= ~ATA_DHR_DEV; /* select device0 */
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|
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return 0;
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return 0;
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}
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}
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|
|
|
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case ATA_IOCTL_SET_FTE:
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case ATA_IOCTL_SET_FTE:
|
{
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{
|
/* set FTE bits */
|
/* set FTE bits */
|
if ( MINOR(inode->i_rdev) )
|
if ( MINOR(inode->i_rdev) )
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if (argument)
|
if (argument)
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REG32(base + ATA_CTRL) |= ATA_IORDY_FTE0;
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REG32(base + ATA_CTRL) |= ATA_IORDY_FTE0;
|
else
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else
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REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE0;
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REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE0;
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else
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else
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if (argument)
|
if (argument)
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REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
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REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
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else
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else
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REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
case ATA_IOCTL_SET_PIO:
|
case ATA_IOCTL_SET_PIO:
|
/* programs the PIO timing registers */
|
/* programs the PIO timing registers */
|
{
|
{
|
unsigned long timing;
|
unsigned long timing;
|
unsigned short buf[256];
|
unsigned short buf[256];
|
|
|
/* do we need to read the identify_device block ?? */
|
/* do we need to read the identify_device block ?? */
|
if (argument & (ARG_PIO4 | ARG_PIO3) )
|
if (argument & (ARG_PIO4 | ARG_PIO3) )
|
{
|
{
|
/* identify requested ata-devices */
|
/* identify requested ata-devices */
|
ata_ioctl(inode, filp, ATA_IOCTL_EXEC_CMD, IDENTIFY_DEVICE);
|
ata_ioctl(inode, filp, ATA_IOCTL_EXEC_CMD, IDENTIFY_DEVICE);
|
|
|
/* read block from ata-device */
|
/* read block from ata-device */
|
buf[0] = 256;
|
buf[0] = 256;
|
ata_ioctl(inode, filp, ATA_IOCTL_READ, (unsigned long) buf);
|
ata_ioctl(inode, filp, ATA_IOCTL_READ, (unsigned long) buf);
|
}
|
}
|
|
|
/* program register transfer timing registers */
|
/* program register transfer timing registers */
|
/* set the slowest pio mode for register transfers */
|
/* set the slowest pio mode for register transfers */
|
if (argument < current_pio_mode)
|
if (argument < current_pio_mode)
|
{
|
{
|
switch (argument)
|
switch (argument)
|
{
|
{
|
case ARG_PIO4:
|
case ARG_PIO4:
|
if ( (buf[53] & 0x01) && buf[68] )
|
if ( (buf[53] & 0x01) && buf[68] )
|
timing = ata_calc_pio_timing(buf[68], PIO4_RT1, PIO4_RT2, PIO4_RT4, PIO4_RT2I, PIO4_RT9);
|
timing = ata_calc_pio_timing(buf[68], PIO4_RT1, PIO4_RT2, PIO4_RT4, PIO4_RT2I, PIO4_RT9);
|
else
|
else
|
timing = ata_calc_pio_timing(PIO4_RT0, PIO4_RT1, PIO4_RT2, PIO4_RT4, PIO4_RT2I, PIO4_RT9);
|
timing = ata_calc_pio_timing(PIO4_RT0, PIO4_RT1, PIO4_RT2, PIO4_RT4, PIO4_RT2I, PIO4_RT9);
|
break;
|
break;
|
|
|
case ARG_PIO3:
|
case ARG_PIO3:
|
if ( (buf[53] & 0x01) && buf[68] )
|
if ( (buf[53] & 0x01) && buf[68] )
|
timing = ata_calc_pio_timing(buf[68], PIO3_RT1, PIO3_RT2, PIO3_RT4, PIO3_RT2I, PIO3_RT9);
|
timing = ata_calc_pio_timing(buf[68], PIO3_RT1, PIO3_RT2, PIO3_RT4, PIO3_RT2I, PIO3_RT9);
|
else
|
else
|
timing = ata_calc_pio_timing(PIO3_RT0, PIO3_RT1, PIO3_RT2, PIO3_RT4, PIO3_RT2I, PIO3_RT9);
|
timing = ata_calc_pio_timing(PIO3_RT0, PIO3_RT1, PIO3_RT2, PIO3_RT4, PIO3_RT2I, PIO3_RT9);
|
break;
|
break;
|
|
|
case ARG_PIO2:
|
case ARG_PIO2:
|
timing = ata_calc_pio_timing(PIO2_RT0, PIO2_RT1, PIO2_RT2, PIO2_RT4, PIO2_RT2I, PIO2_RT9);
|
timing = ata_calc_pio_timing(PIO2_RT0, PIO2_RT1, PIO2_RT2, PIO2_RT4, PIO2_RT2I, PIO2_RT9);
|
break;
|
break;
|
|
|
case ARG_PIO1:
|
case ARG_PIO1:
|
timing = ata_calc_pio_timing(PIO1_RT0, PIO1_RT1, PIO1_RT2, PIO1_RT4, PIO1_RT2I, PIO1_RT9);
|
timing = ata_calc_pio_timing(PIO1_RT0, PIO1_RT1, PIO1_RT2, PIO1_RT4, PIO1_RT2I, PIO1_RT9);
|
break;
|
break;
|
|
|
default: /* PIO mode 0 */
|
default: /* PIO mode 0 */
|
timing = ata_calc_pio_timing(PIO0_RT0, PIO0_RT1, PIO0_RT2, PIO0_RT4, PIO0_RT2I, PIO0_RT9);
|
timing = ata_calc_pio_timing(PIO0_RT0, PIO0_RT1, PIO0_RT2, PIO0_RT4, PIO0_RT2I, PIO0_RT9);
|
break;
|
break;
|
}
|
}
|
|
|
/* program IORDY bit */
|
/* program IORDY bit */
|
if (argument & (ARG_PIO4 | ARG_PIO3) )
|
if (argument & (ARG_PIO4 | ARG_PIO3) )
|
REG32(base + ATA_CTRL) |= ATA_IORDY;
|
REG32(base + ATA_CTRL) |= ATA_IORDY;
|
else
|
else
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY;
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY;
|
|
|
/* program register transfer timing registers */
|
/* program register transfer timing registers */
|
REG32(base + ATA_PCTR) = timing;
|
REG32(base + ATA_PCTR) = timing;
|
|
|
current_pio_mode = argument;
|
current_pio_mode = argument;
|
}
|
}
|
|
|
/* Program data transfer timing registers */
|
/* Program data transfer timing registers */
|
if ( TYPE(ata_ioctl(inode, filp, ATA_IOCTL_IDENTIFY_HOST, 0)) > 1 )
|
if ( TYPE(ata_ioctl(inode, filp, ATA_IOCTL_IDENTIFY_HOST, 0)) > 1 )
|
{
|
{
|
switch (argument)
|
switch (argument)
|
{
|
{
|
case ARG_PIO4:
|
case ARG_PIO4:
|
if ( (buf[53] & 0x01) && buf[68] )
|
if ( (buf[53] & 0x01) && buf[68] )
|
timing = ata_calc_pio_timing(buf[68], PIO4_DT1, PIO4_DT2, PIO4_DT4, PIO4_DT2I, PIO4_DT9);
|
timing = ata_calc_pio_timing(buf[68], PIO4_DT1, PIO4_DT2, PIO4_DT4, PIO4_DT2I, PIO4_DT9);
|
else
|
else
|
timing = ata_calc_pio_timing(PIO4_DT0, PIO4_DT1, PIO4_DT2, PIO4_DT4, PIO4_DT2I, PIO4_DT9);
|
timing = ata_calc_pio_timing(PIO4_DT0, PIO4_DT1, PIO4_DT2, PIO4_DT4, PIO4_DT2I, PIO4_DT9);
|
break;
|
break;
|
|
|
case ARG_PIO3:
|
case ARG_PIO3:
|
if ( (buf[53] & 0x01) && buf[68] )
|
if ( (buf[53] & 0x01) && buf[68] )
|
timing = ata_calc_pio_timing(buf[68], PIO3_DT1, PIO3_DT2, PIO3_DT4, PIO3_DT2I, PIO3_DT9);
|
timing = ata_calc_pio_timing(buf[68], PIO3_DT1, PIO3_DT2, PIO3_DT4, PIO3_DT2I, PIO3_DT9);
|
else
|
else
|
timing = ata_calc_pio_timing(PIO3_DT0, PIO3_DT1, PIO3_DT2, PIO3_DT4, PIO3_DT2I, PIO3_DT9);
|
timing = ata_calc_pio_timing(PIO3_DT0, PIO3_DT1, PIO3_DT2, PIO3_DT4, PIO3_DT2I, PIO3_DT9);
|
break;
|
break;
|
|
|
case ARG_PIO2:
|
case ARG_PIO2:
|
timing = ata_calc_pio_timing(PIO2_DT0, PIO2_DT1, PIO2_DT2, PIO2_DT4, PIO2_DT2I, PIO2_DT9);
|
timing = ata_calc_pio_timing(PIO2_DT0, PIO2_DT1, PIO2_DT2, PIO2_DT4, PIO2_DT2I, PIO2_DT9);
|
break;
|
break;
|
|
|
case ARG_PIO1:
|
case ARG_PIO1:
|
timing = ata_calc_pio_timing(PIO1_DT0, PIO1_DT1, PIO1_DT2, PIO1_DT4, PIO1_DT2I, PIO1_DT9);
|
timing = ata_calc_pio_timing(PIO1_DT0, PIO1_DT1, PIO1_DT2, PIO1_DT4, PIO1_DT2I, PIO1_DT9);
|
break;
|
break;
|
|
|
default: /* PIO mode 0 */
|
default: /* PIO mode 0 */
|
timing = ata_calc_pio_timing(PIO0_DT0, PIO0_DT1, PIO0_DT2, PIO0_DT4, PIO0_DT2I, PIO0_DT9);
|
timing = ata_calc_pio_timing(PIO0_DT0, PIO0_DT1, PIO0_DT2, PIO0_DT4, PIO0_DT2I, PIO0_DT9);
|
break;
|
break;
|
}
|
}
|
|
|
/* program data transfer timing registers, set IORDY bit */
|
/* program data transfer timing registers, set IORDY bit */
|
if ( MINOR(inode->i_rdev) )
|
if ( MINOR(inode->i_rdev) )
|
{
|
{
|
REG32(base + ATA_PFTR1) = timing;
|
REG32(base + ATA_PFTR1) = timing;
|
|
|
/* program IORDY bit */
|
/* program IORDY bit */
|
if ( argument & (ARG_PIO4 | ARG_PIO3) )
|
if ( argument & (ARG_PIO4 | ARG_PIO3) )
|
REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
|
REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
|
else
|
else
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
}
|
}
|
else
|
else
|
{
|
{
|
REG32(base + ATA_PFTR0) = timing;
|
REG32(base + ATA_PFTR0) = timing;
|
|
|
/* program IORDY bit */
|
/* program IORDY bit */
|
if ( argument & (ARG_PIO4 | ARG_PIO3) )
|
if ( argument & (ARG_PIO4 | ARG_PIO3) )
|
REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
|
REG32(base + ATA_CTRL) |= ATA_IORDY_FTE1;
|
else
|
else
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
REG32(base + ATA_CTRL) &= ~ATA_IORDY_FTE1;
|
}
|
}
|
|
|
/* enable data transfer timing */
|
/* enable data transfer timing */
|
ata_ioctl(inode, filp, ATA_IOCTL_SET_FTE, 1);
|
ata_ioctl(inode, filp, ATA_IOCTL_SET_FTE, 1);
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
case ATA_IOCTL_SET_RST:
|
case ATA_IOCTL_SET_RST:
|
/* sets or clears reset bits */
|
/* sets or clears reset bits */
|
if (argument & SET)
|
if (argument & SET)
|
switch (argument & ~SET) {
|
switch (argument & ~SET) {
|
case ARG_HW_RST: /* ata hardware reset */
|
case ARG_HW_RST: /* ata hardware reset */
|
REG32(base + ATA_CTRL) |= ATA_RST;
|
REG32(base + ATA_CTRL) |= ATA_RST;
|
return 0;
|
return 0;
|
|
|
case ARG_SW_RST: /* ata software reset */
|
case ARG_SW_RST: /* ata software reset */
|
REG32(base + ATA_DCR) |= ATA_DCR_RST;
|
REG32(base + ATA_DCR) |= ATA_DCR_RST;
|
return 0;
|
return 0;
|
|
|
case ARG_DEV_RST: /* ata device reset */
|
case ARG_DEV_RST: /* ata device reset */
|
REG32(base + ATA_CR) = DEVICE_RESET;
|
REG32(base + ATA_CR) = DEVICE_RESET;
|
return 0;
|
return 0;
|
|
|
default:
|
default:
|
return EIOCTLIARG;
|
return EIOCTLIARG;
|
}
|
}
|
else
|
else
|
{
|
{
|
switch(argument & ~SET) {
|
switch(argument & ~SET) {
|
case ARG_HW_RST: /* ata hardware reset */
|
case ARG_HW_RST: /* ata hardware reset */
|
REG32(base + ATA_CTRL) &= ~ATA_RST;
|
REG32(base + ATA_CTRL) &= ~ATA_RST;
|
return 0;
|
return 0;
|
|
|
case ARG_SW_RST: /* ata software reset */
|
case ARG_SW_RST: /* ata software reset */
|
REG32(base + ATA_DCR) &= ~ATA_DCR_RST;
|
REG32(base + ATA_DCR) &= ~ATA_DCR_RST;
|
return 0;
|
return 0;
|
|
|
case ARG_DEV_RST: /* ata device reset */
|
case ARG_DEV_RST: /* ata device reset */
|
return 0;
|
return 0;
|
|
|
default:
|
default:
|
return EIOCTLIARG;
|
return EIOCTLIARG;
|
}
|
}
|
}
|
}
|
|
|
|
|
default:
|
default:
|
printf( "FIXME: Unsupported IOCTL call %1d\n", command );
|
printf( "FIXME: Unsupported IOCTL call %1d\n", command );
|
return EINVAL;
|
return EINVAL;
|
}
|
}
|
}
|
}
|
|
|
|
|
unsigned long ata_calc_pio_timing(short t0, short t1, short t2, short t4, short t2i, short t9)
|
unsigned long ata_calc_pio_timing(short t0, short t1, short t2, short t4, short t2i, short t9)
|
{
|
{
|
int teoc;
|
int teoc;
|
|
|
teoc = t0 - t1 - t2;
|
teoc = t0 - t1 - t2;
|
|
|
if (teoc < 0)
|
if (teoc < 0)
|
teoc = 0;
|
teoc = 0;
|
|
|
if (t9 > teoc)
|
if (t9 > teoc)
|
teoc = t9;
|
teoc = t9;
|
|
|
if (t2i > teoc)
|
if (t2i > teoc)
|
teoc = t2i;
|
teoc = t2i;
|
|
|
t1 = TO_TICKS(t1);
|
t1 = TO_TICKS(t1);
|
t2 = TO_TICKS(t2);
|
t2 = TO_TICKS(t2);
|
t4 = TO_TICKS(t4);
|
t4 = TO_TICKS(t4);
|
teoc = TO_TICKS(teoc);
|
teoc = TO_TICKS(teoc);
|
|
|
return (teoc << ATA_TEOC) | (t4 << ATA_T4) | (t2 << ATA_T2) | (t1 << ATA_T1);
|
return (teoc << ATA_TEOC) | (t4 << ATA_T4) | (t2 << ATA_T2) | (t1 << ATA_T1);
|
}
|
}
|
|
|
|
|
/*
|
/*
|
A T A _ R E Q U E S T
|
A T A _ R E Q U E S T
|
*/
|
*/
|
int ata_request(struct inode *inode, struct file *filp, struct request *request)
|
int ata_request(struct inode *inode, struct file *filp, struct request *request)
|
{
|
{
|
unsigned int device = MINOR(inode->i_rdev);
|
unsigned int device = MINOR(inode->i_rdev);
|
unsigned long base = BASE(inode);
|
unsigned long base = BASE(inode);
|
unsigned int sector_size;
|
unsigned int sector_size;
|
|
|
/* get the sector size for the current device */
|
/* get the sector size for the current device */
|
sector_size = hardsect_size[device] >> 1;
|
sector_size = hardsect_size[device] >> 1;
|
|
|
/* set the device */
|
/* set the device */
|
ata_ioctl(inode, filp, ATA_IOCTL_SELECT_DEVICE, device);
|
ata_ioctl(inode, filp, ATA_IOCTL_SELECT_DEVICE, device);
|
|
|
/* get the base address */
|
/* get the base address */
|
base = BASE(inode);
|
base = BASE(inode);
|
|
|
switch (request->cmd) {
|
switch (request->cmd) {
|
case READ:
|
case READ:
|
{
|
{
|
register unsigned long i, n;
|
register unsigned long i, n;
|
register unsigned short rd_data;
|
register unsigned short rd_data;
|
register char *buf_ptr;
|
register char *buf_ptr;
|
|
|
/* program ata-device registers */
|
/* program ata-device registers */
|
REG32(base + ATA_DHR) = ((request->sector >> 24) & ATA_DHR_H) | ATA_DHR_LBA;
|
REG32(base + ATA_DHR) = ((request->sector >> 24) & ATA_DHR_H) | ATA_DHR_LBA;
|
REG32(base + ATA_CHR) = (request->sector >> 16) & 0xff;
|
REG32(base + ATA_CHR) = (request->sector >> 16) & 0xff;
|
REG32(base + ATA_CLR) = (request->sector >> 8) & 0xff;
|
REG32(base + ATA_CLR) = (request->sector >> 8) & 0xff;
|
REG32(base + ATA_SNR) = request->sector & 0xff;
|
REG32(base + ATA_SNR) = request->sector & 0xff;
|
|
|
REG32(base + ATA_SCR) = request->nr_sectors;
|
REG32(base + ATA_SCR) = request->nr_sectors;
|
|
|
/* send 'read_sector(s)' command */
|
/* send 'read_sector(s)' command */
|
REG32(base + ATA_CR) = READ_SECTORS;
|
REG32(base + ATA_CR) = READ_SECTORS;
|
|
|
/* check status & error registers */
|
/* check status & error registers */
|
if ( ata_astatus(base) & ATA_SR_ERR)
|
if ( ata_astatus(base) & ATA_SR_ERR)
|
return -1;
|
return -1;
|
|
|
/* read data from devices and store it in the buffer */
|
/* read data from devices and store it in the buffer */
|
buf_ptr = request->buffer;
|
buf_ptr = request->buffer;
|
|
|
for (n=0; n < request->nr_sectors; n++)
|
for (n=0; n < request->nr_sectors; n++)
|
for (i=0; i < sector_size; i++)
|
for (i=0; i < sector_size; i++)
|
{
|
{
|
rd_data = ata_read_dport(base);
|
rd_data = ata_read_dport(base);
|
|
|
/* the data is byte reversed, swap high & low bytes */
|
/* the data is byte reversed, swap high & low bytes */
|
*buf_ptr++ = rd_data;
|
*buf_ptr++ = rd_data;
|
*buf_ptr++ = rd_data >> 8;
|
*buf_ptr++ = rd_data >> 8;
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
|
|
case WRITE:
|
case WRITE:
|
/* check if device may be written to */
|
/* check if device may be written to */
|
if (filp->f_mode & FMODE_WRITE)
|
if (filp->f_mode & FMODE_WRITE)
|
{
|
{
|
/* do the write stuff */
|
/* do the write stuff */
|
}
|
}
|
else
|
else
|
return EINVAL;
|
return EINVAL;
|
|
|
|
|
default:
|
default:
|
return EINVAL;
|
return EINVAL;
|
}
|
}
|
|
|
return 0;
|
return 0;
|
}
|
}
|
|
|
