Notes on running this design on an RC200:
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Notes on running this design on an RC200:
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Building the hardware
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Building the hardware
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* Synthesise using Synplicity and the script: syn/synplicity/rc200.tcl.
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* Synthesise using Synplicity and the script: syn/synplicity/rc200.tcl.
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* Place-and-route the resulting edif (rc200soc.edf) along with
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* Place-and-route the resulting edif (rc200soc.edf) along with
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the constraint file: backend/xilinx/rc200soc.ucf
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the constraint file: backend/xilinx/rc200soc.ucf
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* Note: I found that with ISE 7.1.04i, and Synplify Pro 8.0 I was unable meet
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* Note: I found that with ISE 7.1.04i, and Synplify Pro 8.0 I was unable meet
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the timing for a 50 MHz clock (as selected in the UCF). In practice though
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the timing for a 50 MHz clock (as selected in the UCF). In practice though
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the error margin is narrow enough for the design to probably work anyway.
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the error margin is narrow enough for the design to probably work anyway.
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Building the software
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Building the software
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* In the jtag server source, comment out the dbg_test() procedure call in
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* In the jtag server source, comment out the dbg_test() procedure call in
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main(). This prevents initialisation of devices not present in this
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main(). This prevents initialisation of devices not present in this
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design.
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design.
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* If the or1200_defines.v file is not changed to enable the trace buffer
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* If the or1200_defines.v file is not changed to enable the trace buffer
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(OR1200_DU_TB_IMPLEMENTED), change the gdb source by commenting out the
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(OR1200_DU_TB_IMPLEMENTED), change the gdb source by commenting out the
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call to or1k_read_trace() in remote-or1k.c:or1k_wait().
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call to or1k_read_trace() in remote-or1k.c:or1k_wait().
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* Modify the board.h file for orpmon or hello-uart programs to reflect
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* Modify the board.h file for orpmon or hello-uart programs to reflect
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