; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */
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; /* @(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI */
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; macros: Do_install and init_TLB
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; macros: Do_install and init_TLB
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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; /* pswmacro.ah,v 1.2 2000/09/22 13:59:41 joel Exp */
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; /* pswmacro.ah,v 1.2 2000/09/22 13:59:41 joel Exp */
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;* File information and includes.
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;* File information and includes.
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.file "macro.ah"
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.file "macro.ah"
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.ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"
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.ident "@(#)pswmacro.ah 1.1 96/05/23 08:56:58, TEI"
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.macro CONST32, RegName, RegValue
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.macro CONST32, RegName, RegValue
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const RegName, RegValue
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const RegName, RegValue
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consth RegName, RegValue
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consth RegName, RegValue
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.endm
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.endm
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.macro CONSTX, RegName, RegValue
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.macro CONSTX, RegName, RegValue
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.if (RegValue) <= 0x0000ffff
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.if (RegValue) <= 0x0000ffff
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const RegName, RegValue
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const RegName, RegValue
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.else
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.else
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const RegName, RegValue
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const RegName, RegValue
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consth RegName, RegValue
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consth RegName, RegValue
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.endif
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.endif
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.endm
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.endm
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.macro PRODEV, RegName
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.macro PRODEV, RegName
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srl RegName, RegName, 24
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srl RegName, RegName, 24
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.endm
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.endm
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;
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;
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;* MACRO TO INSTALL VECTOR TABLE ENTRIES
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;* MACRO TO INSTALL VECTOR TABLE ENTRIES
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;
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;
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;* Assumes vector table address in v0
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;* Assumes vector table address in v0
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.macro _setvec, trapnum, trapaddr
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.macro _setvec, trapnum, trapaddr
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mfsr v0, vab ;
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mfsr v0, vab ;
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const v2, trapnum ;
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const v2, trapnum ;
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sll v1, v2, 2 ;
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sll v1, v2, 2 ;
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add v1, v1, v0 ; v0 has location of vector tab
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add v1, v1, v0 ; v0 has location of vector tab
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const v2, trapaddr ;
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const v2, trapaddr ;
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consth v2, trapaddr ;
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consth v2, trapaddr ;
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store 0, 0, v2, v1 ;
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store 0, 0, v2, v1 ;
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nop ;
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nop ;
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.endm
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.endm
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.macro syscall, name
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.macro syscall, name
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const tav, HIF_@name ;
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const tav, HIF_@name ;
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asneq V_SYSCALL, gr1, gr1 ;
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asneq V_SYSCALL, gr1, gr1 ;
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nop ;
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nop ;
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nop ;
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nop ;
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.endm
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.endm
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;* MACRO TO INSTALL VECTOR TABLE ENTRIES
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;* MACRO TO INSTALL VECTOR TABLE ENTRIES
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.macro Do_Install, V_Number, V_Address
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.macro Do_Install, V_Number, V_Address
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const lr4, V_Address
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const lr4, V_Address
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consth lr4, V_Address
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consth lr4, V_Address
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const lr3, V_Number * 4
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const lr3, V_Number * 4
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consth lr3, V_Number * 4
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consth lr3, V_Number * 4
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call lr0, V_Install
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call lr0, V_Install
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nop
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nop
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.endm
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.endm
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.macro Do_InstallX, V_Number, V_Address
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.macro Do_InstallX, V_Number, V_Address
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const lr4, V_Address
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const lr4, V_Address
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consth lr4, V_Address
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consth lr4, V_Address
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const lr3, V_Number * 4
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const lr3, V_Number * 4
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consth lr3, V_Number * 4
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consth lr3, V_Number * 4
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call lr0, V_InstallX
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call lr0, V_InstallX
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nop
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nop
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.endm
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.endm
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; push a register onto the stack
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; push a register onto the stack
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.macro pushreg, reg, sp
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.macro pushreg, reg, sp
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sub sp, sp, 4 ; adjust stack pointer
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sub sp, sp, 4 ; adjust stack pointer
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store 0, 0, reg, sp ; push register
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store 0, 0, reg, sp ; push register
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.endm
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.endm
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.macro push, sp, reg
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.macro push, sp, reg
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sub sp, sp, 4
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sub sp, sp, 4
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store 0, 0, reg, sp
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store 0, 0, reg, sp
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.endm
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.endm
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; pop the register from stack
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; pop the register from stack
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.macro popreg, reg, sp
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.macro popreg, reg, sp
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load 0, 0, reg, sp ; pop register
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load 0, 0, reg, sp ; pop register
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add sp, sp, 4 ; adjust stack pointer
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add sp, sp, 4 ; adjust stack pointer
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.endm
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.endm
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.macro pop, reg, sp
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.macro pop, reg, sp
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load 0, 0, reg, sp
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load 0, 0, reg, sp
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add sp, sp, 4
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add sp, sp, 4
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.endm
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.endm
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; push a special register onto stack
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; push a special register onto stack
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.macro pushspcl, spcl, tmpreg, sp
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.macro pushspcl, spcl, tmpreg, sp
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sub sp, sp, 4 ; adjust stack pointer
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sub sp, sp, 4 ; adjust stack pointer
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mfsr tmpreg, spcl ; get spcl reg
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mfsr tmpreg, spcl ; get spcl reg
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store 0, 0, tmpreg, sp ; push onto stack
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store 0, 0, tmpreg, sp ; push onto stack
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.endm
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.endm
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.macro pushsr, sp, reg, sreg
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.macro pushsr, sp, reg, sreg
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mfsr reg, sreg
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mfsr reg, sreg
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sub sp, sp, 4
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sub sp, sp, 4
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store 0, 0, reg, sp
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store 0, 0, reg, sp
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.endm
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.endm
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; pop a special register from stack
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; pop a special register from stack
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.macro popspcl, spcl, tmpreg, sp
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.macro popspcl, spcl, tmpreg, sp
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load 0, 0, tmpreg, sp ; pop from stack
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load 0, 0, tmpreg, sp ; pop from stack
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add sp, sp, 4 ; adjust stack pointer
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add sp, sp, 4 ; adjust stack pointer
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mtsr spcl, tmpreg ; set spcl reg
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mtsr spcl, tmpreg ; set spcl reg
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.endm
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.endm
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.macro popsr, sreg, reg, sp
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.macro popsr, sreg, reg, sp
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load 0, 0, reg, sp
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load 0, 0, reg, sp
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add sp, sp, 4
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add sp, sp, 4
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mtsr sreg, reg
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mtsr sreg, reg
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.endm
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.endm
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;
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;
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; save freeze mode registers on memory stack.
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; save freeze mode registers on memory stack.
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;
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;
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.macro SaveFZState, tmp1, tmp2
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.macro SaveFZState, tmp1, tmp2
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; save freeze mode registers.
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; save freeze mode registers.
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pushspcl pc0, tmp1, msp
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pushspcl pc0, tmp1, msp
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pushspcl pc1, tmp1, msp
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pushspcl pc1, tmp1, msp
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pushspcl alu, tmp1, msp
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pushspcl alu, tmp1, msp
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pushspcl cha, tmp1, msp
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pushspcl cha, tmp1, msp
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pushspcl chd, tmp1, msp
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pushspcl chd, tmp1, msp
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pushspcl chc, tmp1, msp
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pushspcl chc, tmp1, msp
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pushspcl ops, tmp1, msp
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pushspcl ops, tmp1, msp
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; turn freeze off
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; turn freeze off
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const tmp2, FZ
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const tmp2, FZ
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mfsr tmp1, cps
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mfsr tmp1, cps
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andn tmp1, tmp1, tmp2
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andn tmp1, tmp1, tmp2
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mtsr cps, tmp1
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mtsr cps, tmp1
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.endm
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.endm
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; restore freeze mode registers from memory stack.
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; restore freeze mode registers from memory stack.
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.macro RestoreFZState, tmp1, tmp2
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.macro RestoreFZState, tmp1, tmp2
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; turn freeze on
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; turn freeze on
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const tmp2, (FZ|DI|DA)
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const tmp2, (FZ|DI|DA)
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mfsr tmp1, cps
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mfsr tmp1, cps
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or tmp1, tmp1, tmp2
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or tmp1, tmp1, tmp2
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mtsr cps, tmp1
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mtsr cps, tmp1
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; restore freeze mode registers.
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; restore freeze mode registers.
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popspcl ops, tmp1, msp
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popspcl ops, tmp1, msp
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popspcl chc, tmp1, msp
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popspcl chc, tmp1, msp
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popspcl chd, tmp1, msp
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popspcl chd, tmp1, msp
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popspcl cha, tmp1, msp
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popspcl cha, tmp1, msp
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popspcl alu, tmp1, msp
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popspcl alu, tmp1, msp
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popspcl pc1, tmp1, msp
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popspcl pc1, tmp1, msp
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popspcl pc0, tmp1, msp
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popspcl pc0, tmp1, msp
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.endm
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.endm
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;
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;
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;*
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;*
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;
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;
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.equ WS, 512 ; window size
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.equ WS, 512 ; window size
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.equ RALLOC, 4 * 4 ; stack alloc for C
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.equ RALLOC, 4 * 4 ; stack alloc for C
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.equ SIGCTX_UM_SIZE, 40 * 4 ;
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.equ SIGCTX_UM_SIZE, 40 * 4 ;
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.equ SIGCTX_RFB, (38) * 4 ; user mode saved
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.equ SIGCTX_RFB, (38) * 4 ; user mode saved
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.equ SIGCTX_SM_SIZE, 12 * 4 ;
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.equ SIGCTX_SM_SIZE, 12 * 4 ;
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.equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_SIG, (11)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_GR1, (10)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_RAB, (9)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC0, (8)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC1, (7)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_PC2, (6)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_CHC, (3)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_OPS, (1)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;
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.equ SIGCTX_TAV, (0)*4 + SIGCTX_UM_SIZE ;
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.macro sup_sv
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.macro sup_sv
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add it2, trapreg, 0 ; transfer signal #
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add it2, trapreg, 0 ; transfer signal #
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sub msp, msp, 4 ;
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sub msp, msp, 4 ;
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store 0, 0, it2, msp ; save signal number
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store 0, 0, it2, msp ; save signal number
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sub msp, msp, 4 ; push gr1
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sub msp, msp, 4 ; push gr1
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store 0, 0, gr1, msp ;
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store 0, 0, gr1, msp ;
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sub msp, msp, 4 ; push rab
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sub msp, msp, 4 ; push rab
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store 0, 0, rab, msp ;
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store 0, 0, rab, msp ;
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const it0, WS ; Window size
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const it0, WS ; Window size
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sub rab, rfb, it0 ; set rab = rfb-512
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sub rab, rfb, it0 ; set rab = rfb-512
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pushsr msp, it0, PC0 ; save program counter0
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pushsr msp, it0, PC0 ; save program counter0
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pushsr msp, it0, PC1 ; save program counter1
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pushsr msp, it0, PC1 ; save program counter1
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pushsr msp, it0, PC2 ; save program counter2
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pushsr msp, it0, PC2 ; save program counter2
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pushsr msp, it0, CHA ; save channel address
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pushsr msp, it0, CHA ; save channel address
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pushsr msp, it0, CHD ; save channel data
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pushsr msp, it0, CHD ; save channel data
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pushsr msp, it0, CHC ; save channel control
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pushsr msp, it0, CHC ; save channel control
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pushsr msp, it0, ALU ; save alu
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pushsr msp, it0, ALU ; save alu
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pushsr msp, it0, OPS ; save ops
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pushsr msp, it0, OPS ; save ops
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sub msp, msp, 4 ;
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sub msp, msp, 4 ;
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store 0, 0, tav, msp ; push tav
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store 0, 0, tav, msp ; push tav
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mtsrim chc, 0 ; no loadm/storem
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mtsrim chc, 0 ; no loadm/storem
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mfsr it0, ops ; get ops value
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mfsr it0, ops ; get ops value
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const it1, (TD | DI) ; disable interrupts
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const it1, (TD | DI) ; disable interrupts
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consth it1, (TD | DI) ; disable interrupts
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consth it1, (TD | DI) ; disable interrupts
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or it0, it0, it1 ; set bits
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or it0, it0, it1 ; set bits
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mtsr ops, it0 ; set new ops
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mtsr ops, it0 ; set new ops
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const it0, _sigcode ; signal handler
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const it0, _sigcode ; signal handler
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consth it0, _sigcode ; signal handler
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consth it0, _sigcode ; signal handler
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mtsr pc1, it0 ; store pc1
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mtsr pc1, it0 ; store pc1
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add it1, it0, 4 ; next addr
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add it1, it0, 4 ; next addr
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mtsr pc0, it1 ; store pc1 location
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mtsr pc0, it1 ; store pc1 location
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iret ; return
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iret ; return
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nop ; ALIGN
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nop ; ALIGN
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.endm
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.endm
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.macro sig_return
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.macro sig_return
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mfsr it0, cps ; get processor status
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mfsr it0, cps ; get processor status
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const it1, FZ|DA ; Freeze + traps disable
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const it1, FZ|DA ; Freeze + traps disable
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or it0, it0, it1 ; to set FZ+DA
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or it0, it0, it1 ; to set FZ+DA
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mtsr cps, it0 ; in freeze mode
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mtsr cps, it0 ; in freeze mode
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load 0, 0, tav, msp ; restore tav
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load 0, 0, tav, msp ; restore tav
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add msp, msp, 4 ;
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add msp, msp, 4 ;
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popsr OPS,it0, msp ;
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popsr OPS,it0, msp ;
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popsr ALU,it0, msp ;
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popsr ALU,it0, msp ;
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popsr CHC,it0, msp ;
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popsr CHC,it0, msp ;
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popsr CHD,it0, msp ;
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popsr CHD,it0, msp ;
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popsr CHA,it0, msp ;
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popsr CHA,it0, msp ;
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popsr PC2,it0, msp ;
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popsr PC2,it0, msp ;
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popsr PC1,it0, msp ;
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popsr PC1,it0, msp ;
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popsr PC0,it0, msp ;
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popsr PC0,it0, msp ;
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load 0, 0, rab, msp ;
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load 0, 0, rab, msp ;
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add msp, msp, 4 ;
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add msp, msp, 4 ;
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load 0, 0, it0, msp ;
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load 0, 0, it0, msp ;
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add gr1, it0, 0 ; pop rsp
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add gr1, it0, 0 ; pop rsp
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add msp, msp, 8 ; discount signal #
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add msp, msp, 8 ; discount signal #
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iret
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iret
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.endm
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.endm
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.macro repair_R_stack
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.macro repair_R_stack
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add v0, msp, SIGCTX_GR1 ; interrupted gr1
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add v0, msp, SIGCTX_GR1 ; interrupted gr1
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load 0, 0, v2, v0 ;
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load 0, 0, v2, v0 ;
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add v0, msp, SIGCTX_RFB ;
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add v0, msp, SIGCTX_RFB ;
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load 0, 0, v3, v0 ; interupted rfb
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load 0, 0, v3, v0 ; interupted rfb
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const v1, WS ;
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const v1, WS ;
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sub v1, v3, v1 ; rfb-512
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sub v1, v3, v1 ; rfb-512
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cpltu v0, v2, v1 ; test gr1 < rfb-512
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cpltu v0, v2, v1 ; test gr1 < rfb-512
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jmpf v0, $1 ;
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jmpf v0, $1 ;
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|
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add gr1, rab, 0 ;
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add gr1, rab, 0 ;
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add v2, v1, 0 ; set LB = rfb-512
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add v2, v1, 0 ; set LB = rfb-512
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$1:
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$1:
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;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
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;* if gr1 < rfb-512 yes LB = rfb-512 signalled during spill
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;* if no, LB=gr1 interrupted cache < 126 registers
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;* if no, LB=gr1 interrupted cache < 126 registers
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cpleu v0, v2, rfb ; test LB<=rfb
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cpleu v0, v2, rfb ; test LB<=rfb
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jmpf v0, $2 ;
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jmpf v0, $2 ;
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nop ;
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nop ;
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add v2, rfb, 0 ;
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add v2, rfb, 0 ;
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$2:
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$2:
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cpeq v0, v3, rfb ; fill rfb->rfb
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cpeq v0, v3, rfb ; fill rfb->rfb
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jmpt v0, $3 ; if rfb==rfb
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jmpt v0, $3 ; if rfb==rfb
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const tav, (0x80<<2) ; prepare for fill
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const tav, (0x80<<2) ; prepare for fill
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or tav, tav, v2 ;
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or tav, tav, v2 ;
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|
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mtsr IPA, tav ; IPA=LA<<2
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mtsr IPA, tav ; IPA=LA<<2
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sub tav, v3, gr98 ; cache fill LA->rfb
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sub tav, v3, gr98 ; cache fill LA->rfb
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srl tav, tav, 2 ; convert to words
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srl tav, tav, 2 ; convert to words
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sub tav, tav, 1 ;
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sub tav, tav, 1 ;
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|
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mtsr cr, tav ;
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mtsr cr, tav ;
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loadm 0, 0, gr0, v2 ; fill from LA->rfb
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loadm 0, 0, gr0, v2 ; fill from LA->rfb
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$3:
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$3:
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add rfb, v3, 0 ; move rfb upto rfb
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add rfb, v3, 0 ; move rfb upto rfb
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sub rab, v1, 0 ; assign rab to rfb-512
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sub rab, v1, 0 ; assign rab to rfb-512
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|
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add v0, msp, SIGCTX_GR1 ;
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add v0, msp, SIGCTX_GR1 ;
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load 0, 0, v2, v0 ; v0 = interrupted gr1
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load 0, 0, v2, v0 ; v0 = interrupted gr1
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add gr1, v2, 0 ; move gr1 upto gr1
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add gr1, v2, 0 ; move gr1 upto gr1
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nop ;
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nop ;
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.endm
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.endm
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|
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.macro repair_regs
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.macro repair_regs
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mtsrim cr, 29 - 1 ; to restore locals
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mtsrim cr, 29 - 1 ; to restore locals
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loadm 0, 0, v0, msp ;
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loadm 0, 0, v0, msp ;
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add msp, msp, 29*4 ;
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add msp, msp, 29*4 ;
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popsr Q, tav, msp ;
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popsr Q, tav, msp ;
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|
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popsr IPC, tav, msp ;
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popsr IPC, tav, msp ;
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popsr IPB, tav, msp ;
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popsr IPB, tav, msp ;
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popsr IPA, tav, msp ;
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popsr IPA, tav, msp ;
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pop FPStat3, msp ; floating point regs
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pop FPStat3, msp ; floating point regs
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|
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pop FPStat2, msp ; floating point regs
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pop FPStat2, msp ; floating point regs
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pop FPStat1, msp ; floating point regs
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pop FPStat1, msp ; floating point regs
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pop FPStat0, msp ; floating point regs
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pop FPStat0, msp ; floating point regs
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|
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add msp, msp, 3*4 ; R-stack repaired
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add msp, msp, 3*4 ; R-stack repaired
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.endm
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.endm
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;
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;
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;*HIF related...
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;*HIF related...
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;
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;
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|
|
|
|
|
|
|
|
; send the message in bufaddr to Montip.
|
; send the message in bufaddr to Montip.
|
.macro SendMessageToMontip, bufaddr
|
.macro SendMessageToMontip, bufaddr
|
const lr2, bufaddr
|
const lr2, bufaddr
|
$1:
|
$1:
|
call lr0, _msg_send
|
call lr0, _msg_send
|
consth lr2, bufaddr
|
consth lr2, bufaddr
|
cpeq gr96, gr96, 0
|
cpeq gr96, gr96, 0
|
jmpf gr96, $1
|
jmpf gr96, $1
|
const lr2, bufaddr
|
const lr2, bufaddr
|
.endm
|
.endm
|
|
|
; build a HIF_CALL message in bufaddr to send to montip.
|
; build a HIF_CALL message in bufaddr to send to montip.
|
.macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2
|
.macro BuildHIFCALLMsg, bufaddr, tmp1, tmp2
|
const tmp1, bufaddr
|
const tmp1, bufaddr
|
consth tmp1, bufaddr
|
consth tmp1, bufaddr
|
const tmp2, HIF_CALL_MSGCODE
|
const tmp2, HIF_CALL_MSGCODE
|
store 0, 0, tmp2, tmp1 ; msg code
|
store 0, 0, tmp2, tmp1 ; msg code
|
add tmp1, tmp1, 4
|
add tmp1, tmp1, 4
|
const tmp2, HIF_CALL_MSGLEN
|
const tmp2, HIF_CALL_MSGLEN
|
store 0, 0, tmp2, tmp1 ; msg len
|
store 0, 0, tmp2, tmp1 ; msg len
|
add tmp1, tmp1, 4
|
add tmp1, tmp1, 4
|
store 0, 0, gr121, tmp1 ; service number
|
store 0, 0, gr121, tmp1 ; service number
|
add tmp1, tmp1, 4
|
add tmp1, tmp1, 4
|
store 0, 0, lr2, tmp1 ; lr2
|
store 0, 0, lr2, tmp1 ; lr2
|
add tmp1, tmp1, 4
|
add tmp1, tmp1, 4
|
store 0, 0, lr3, tmp1 ; lr3
|
store 0, 0, lr3, tmp1 ; lr3
|
add tmp1, tmp1, 4
|
add tmp1, tmp1, 4
|
store 0, 0, lr4, tmp1 ; lr4
|
store 0, 0, lr4, tmp1 ; lr4
|
.endm
|
.endm
|
|
|
;
|
;
|
;*
|
;*
|
;* All the funky AMD style macros go in here...simply for
|
;* All the funky AMD style macros go in here...simply for
|
;* compatility
|
;* compatility
|
;
|
;
|
;
|
;
|
.macro IMPORT, symbol
|
.macro IMPORT, symbol
|
.extern symbol
|
.extern symbol
|
.endm
|
.endm
|
|
|
.macro GLOBAL, symbol
|
.macro GLOBAL, symbol
|
.global symbol
|
.global symbol
|
.endm
|
.endm
|
|
|
.macro USESECT, name, type
|
.macro USESECT, name, type
|
.sect name, type
|
.sect name, type
|
.use name
|
.use name
|
.endm
|
.endm
|
|
|
.macro SECTION, name, type
|
.macro SECTION, name, type
|
.sect name, type
|
.sect name, type
|
.endm
|
.endm
|
|
|
.macro FUNC, fname, lineno
|
.macro FUNC, fname, lineno
|
.global fname
|
.global fname
|
fname:
|
fname:
|
.endm
|
.endm
|
|
|
.macro ENDFUNC, fname, lineno
|
.macro ENDFUNC, fname, lineno
|
.endm
|
.endm
|
|
|
;*************************************LONG
|
;*************************************LONG
|
.macro LONG, varname
|
.macro LONG, varname
|
varname:
|
varname:
|
.block 4
|
.block 4
|
.endm
|
.endm
|
|
|
;*************************************UNSIGNED LONG
|
;*************************************UNSIGNED LONG
|
.macro ULONG, varname
|
.macro ULONG, varname
|
varname:
|
varname:
|
.block 4
|
.block 4
|
.endm
|
.endm
|
|
|
;*************************************SHORT
|
;*************************************SHORT
|
.macro SHORT, varname
|
.macro SHORT, varname
|
varname:
|
varname:
|
.block 2
|
.block 2
|
.endm
|
.endm
|
|
|
;*************************************CHAR
|
;*************************************CHAR
|
.macro CHAR, varname
|
.macro CHAR, varname
|
varname:
|
varname:
|
.block 1
|
.block 1
|
.endm
|
.endm
|
|
|
;*************************************LONGARRAY
|
;*************************************LONGARRAY
|
.macro LONGARRAY, name, count
|
.macro LONGARRAY, name, count
|
name:
|
name:
|
.block count*4
|
.block count*4
|
.endm
|
.endm
|
|
|
;*************************************SHORTARRAY
|
;*************************************SHORTARRAY
|
|
|
.macro SHORTARRAY, name, count
|
.macro SHORTARRAY, name, count
|
name:
|
name:
|
.block count*2
|
.block count*2
|
.endm
|
.endm
|
|
|
;*************************************CHARARRAY
|
;*************************************CHARARRAY
|
|
|
.macro CHARARRAY, name, count
|
.macro CHARARRAY, name, count
|
name:
|
name:
|
.block count
|
.block count
|
.endm
|
.endm
|
|
|
|
|
;*************************************VOID_FPTR
|
;*************************************VOID_FPTR
|
|
|
.macro VOID_FPTR, name
|
.macro VOID_FPTR, name
|
name:
|
name:
|
.block 4
|
.block 4
|
.endm
|
.endm
|
|
|
