/*
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/*
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* This file contains information pertaining to the Hitachi SH
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* This file contains information pertaining to the Hitachi SH
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* processor.
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* processor.
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*
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*
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* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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* Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
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* Bernd Becker (becker@faw.uni-ulm.de)
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* Bernd Becker (becker@faw.uni-ulm.de)
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*
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*
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* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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* COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
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*
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*
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* This program is distributed in the hope that it will be useful,
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*
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*
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*
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* COPYRIGHT (c) 1998-2001.
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* COPYRIGHT (c) 1998-2001.
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* On-Line Applications Research Corporation (OAR).
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* On-Line Applications Research Corporation (OAR).
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*
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*
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* The license and distribution terms for this file may be
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* found in the file LICENSE in this distribution or at
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* http://www.OARcorp.com/rtems/license.html.
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* http://www.OARcorp.com/rtems/license.html.
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*
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*
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* cpu.c,v 1.6 2001/10/15 17:58:07 joel Exp
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* cpu.c,v 1.6 2001/10/15 17:58:07 joel Exp
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*/
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*/
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#include <rtems/system.h>
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#include <rtems/system.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/isr.h>
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#include <rtems/score/sh_io.h>
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#include <rtems/score/sh_io.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/cpu.h>
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#include <rtems/score/sh.h>
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#include <rtems/score/sh.h>
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/* referenced in start.S */
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/* referenced in start.S */
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extern proc_ptr vectab[] ;
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extern proc_ptr vectab[] ;
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proc_ptr vectab[256] ;
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proc_ptr vectab[256] ;
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extern proc_ptr _Hardware_isr_Table[];
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extern proc_ptr _Hardware_isr_Table[];
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/* _CPU_Initialize
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/* _CPU_Initialize
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*
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*
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* This routine performs processor dependent initialization.
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* This routine performs processor dependent initialization.
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*
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*
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* INPUT PARAMETERS:
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* INPUT PARAMETERS:
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* cpu_table - CPU table to initialize
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* cpu_table - CPU table to initialize
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* thread_dispatch - address of disptaching routine
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* thread_dispatch - address of disptaching routine
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*/
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*/
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void _CPU_Initialize(
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void _CPU_Initialize(
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rtems_cpu_table *cpu_table,
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rtems_cpu_table *cpu_table,
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void (*thread_dispatch) /* ignored on this CPU */
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void (*thread_dispatch) /* ignored on this CPU */
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)
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)
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{
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{
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register unsigned32 level = 0;
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register unsigned32 level = 0;
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/*
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/*
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* The thread_dispatch argument is the address of the entry point
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* The thread_dispatch argument is the address of the entry point
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* for the routine called at the end of an ISR once it has been
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* for the routine called at the end of an ISR once it has been
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* decided a context switch is necessary. On some compilation
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* decided a context switch is necessary. On some compilation
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* systems it is difficult to call a high-level language routine
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* systems it is difficult to call a high-level language routine
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* from assembly. This allows us to trick these systems.
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* from assembly. This allows us to trick these systems.
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*
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*
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* If you encounter this problem save the entry point in a CPU
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* If you encounter this problem save the entry point in a CPU
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* dependent variable.
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* dependent variable.
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*/
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*/
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_CPU_Thread_dispatch_pointer = thread_dispatch;
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_CPU_Thread_dispatch_pointer = thread_dispatch;
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/*
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/*
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* If there is not an easy way to initialize the FP context
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* If there is not an easy way to initialize the FP context
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* during Context_Initialize, then it is usually easier to
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* during Context_Initialize, then it is usually easier to
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* save an "uninitialized" FP context here and copy it to
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* save an "uninitialized" FP context here and copy it to
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* the task's during Context_Initialize.
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* the task's during Context_Initialize.
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*/
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*/
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/* FP context initialization support goes here */
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/* FP context initialization support goes here */
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/* FIXME: When not to use SH4_FPSCR_PR ? */
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/* FIXME: When not to use SH4_FPSCR_PR ? */
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#ifdef __SH4__
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#ifdef __SH4__
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_CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
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_CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM | SH4_FPSCR_PR;
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#endif
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#endif
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#ifdef __SH3E__
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#ifdef __SH3E__
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/* FIXME: Wild guess :) */
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/* FIXME: Wild guess :) */
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_CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
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_CPU_Null_fp_context.fpscr = SH4_FPSCR_DN | SH4_FPSCR_RM;
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#endif
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#endif
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_CPU_Table = *cpu_table;
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_CPU_Table = *cpu_table;
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/* enable interrupts */
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/* enable interrupts */
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_CPU_ISR_Set_level( level);
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_CPU_ISR_Set_level( level);
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}
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}
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/*PAGE
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/*PAGE
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*
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*
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* _CPU_ISR_Get_level
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* _CPU_ISR_Get_level
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*/
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*/
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unsigned32 _CPU_ISR_Get_level( void )
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unsigned32 _CPU_ISR_Get_level( void )
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{
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{
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/*
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/*
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* This routine returns the current interrupt level.
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* This routine returns the current interrupt level.
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*/
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*/
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register unsigned32 _mask ;
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register unsigned32 _mask ;
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sh_get_interrupt_level( _mask );
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sh_get_interrupt_level( _mask );
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return ( _mask);
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return ( _mask);
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}
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}
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/*PAGE
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/*PAGE
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*
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*
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* _CPU_ISR_install_raw_handler
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* _CPU_ISR_install_raw_handler
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*/
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*/
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void _CPU_ISR_install_raw_handler(
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void _CPU_ISR_install_raw_handler(
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unsigned32 vector,
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr new_handler,
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proc_ptr *old_handler
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proc_ptr *old_handler
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)
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)
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{
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{
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/*
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/*
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* This is where we install the interrupt handler into the "raw" interrupt
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* This is where we install the interrupt handler into the "raw" interrupt
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* table used by the CPU to dispatch interrupt handlers.
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* table used by the CPU to dispatch interrupt handlers.
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*/
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*/
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volatile proc_ptr *vbr ;
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volatile proc_ptr *vbr ;
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#if SH_PARANOID_ISR
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#if SH_PARANOID_ISR
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unsigned32 level ;
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unsigned32 level ;
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sh_disable_interrupts( level );
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sh_disable_interrupts( level );
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#endif
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#endif
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/* get vbr */
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/* get vbr */
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asm ( "stc vbr,%0" : "=r" (vbr) );
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asm ( "stc vbr,%0" : "=r" (vbr) );
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*old_handler = vbr[vector] ;
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*old_handler = vbr[vector] ;
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vbr[vector] = new_handler ;
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vbr[vector] = new_handler ;
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#if SH_PARANOID_ISR
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#if SH_PARANOID_ISR
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sh_enable_interrupts( level );
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sh_enable_interrupts( level );
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#endif
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#endif
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}
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}
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/*PAGE
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/*PAGE
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*
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*
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* _CPU_ISR_install_vector
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* _CPU_ISR_install_vector
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*
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*
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* This kernel routine installs the RTEMS handler for the
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* This kernel routine installs the RTEMS handler for the
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* specified vector.
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* specified vector.
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*
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*
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* Input parameters:
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* Input parameters:
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* vector - interrupt vector number
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* vector - interrupt vector number
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* old_handler - former ISR for this vector number
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* old_handler - former ISR for this vector number
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* new_handler - replacement ISR for this vector number
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* new_handler - replacement ISR for this vector number
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*
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*
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* Output parameters: NONE
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* Output parameters: NONE
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*
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*
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*/
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*/
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#if defined(__sh1__) || defined(__sh2__)
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#if defined(__sh1__) || defined(__sh2__)
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void _CPU_ISR_install_vector(
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void _CPU_ISR_install_vector(
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unsigned32 vector,
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unsigned32 vector,
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proc_ptr new_handler,
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proc_ptr new_handler,
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proc_ptr *old_handler
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proc_ptr *old_handler
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)
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)
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{
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{
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proc_ptr ignored ;
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proc_ptr ignored ;
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#if 0
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#if 0
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if(( vector <= 113) && ( vector >= 11))
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if(( vector <= 113) && ( vector >= 11))
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{
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{
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#endif
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#endif
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*old_handler = _ISR_Vector_table[ vector ];
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*old_handler = _ISR_Vector_table[ vector ];
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/*
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/*
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* If the interrupt vector table is a table of pointer to isr entry
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* If the interrupt vector table is a table of pointer to isr entry
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* points, then we need to install the appropriate RTEMS interrupt
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* points, then we need to install the appropriate RTEMS interrupt
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* handler for this vector number.
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* handler for this vector number.
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*/
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*/
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_CPU_ISR_install_raw_handler(vector,
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_CPU_ISR_install_raw_handler(vector,
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_Hardware_isr_Table[vector],
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_Hardware_isr_Table[vector],
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&ignored );
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&ignored );
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/*
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/*
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* We put the actual user ISR address in '_ISR_Vector_table'.
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* We put the actual user ISR address in '_ISR_Vector_table'.
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* This will be used by __ISR_Handler so the user gets control.
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* This will be used by __ISR_Handler so the user gets control.
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*/
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*/
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_ISR_Vector_table[ vector ] = new_handler;
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_ISR_Vector_table[ vector ] = new_handler;
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#if 0
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#if 0
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}
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}
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#endif
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#endif
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}
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}
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#endif /* _CPU_ISR_install_vector */
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#endif /* _CPU_ISR_install_vector */
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/*PAGE
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/*PAGE
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*
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*
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* _CPU_Thread_Idle_body
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* _CPU_Thread_Idle_body
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*
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*
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* NOTES:
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* NOTES:
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*
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*
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* 1. This is the same as the regular CPU independent algorithm.
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* 1. This is the same as the regular CPU independent algorithm.
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*
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*
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* 2. If you implement this using a "halt", "idle", or "shutdown"
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* instruction, then don't forget to put it in an infinite loop.
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* instruction, then don't forget to put it in an infinite loop.
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*
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*
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* 3. Be warned. Some processors with onboard DMA have been known
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* 3. Be warned. Some processors with onboard DMA have been known
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* to stop the DMA if the CPU were put in IDLE mode. This might
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* also be a problem with other on-chip peripherals. So use this
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* also be a problem with other on-chip peripherals. So use this
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* hook with caution.
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* hook with caution.
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*/
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*/
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#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
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#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
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void _CPU_Thread_Idle_body( void )
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void _CPU_Thread_Idle_body( void )
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{
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{
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for( ; ; )
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for( ; ; )
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{
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{
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asm volatile("nop");
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asm volatile("nop");
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}
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}
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/* insert your "halt" instruction here */ ;
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/* insert your "halt" instruction here */ ;
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}
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}
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#endif
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#endif
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#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
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#if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
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unsigned8 _bit_set_table[16] =
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unsigned8 _bit_set_table[16] =
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{ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
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{ 4, 4, 4, 4, 4, 4, 4, 4, 3, 3, 3, 3, 2, 2, 1,0};
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#endif
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#endif
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void _CPU_Context_Initialize(
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void _CPU_Context_Initialize(
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Context_Control *_the_context,
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Context_Control *_the_context,
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void *_stack_base,
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void *_stack_base,
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unsigned32 _size,
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unsigned32 _size,
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unsigned32 _isr,
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unsigned32 _isr,
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void (*_entry_point)(void),
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void (*_entry_point)(void),
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int _is_fp )
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int _is_fp )
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{
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{
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_the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
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_the_context->r15 = (unsigned32*) ((unsigned32) (_stack_base) + (_size) );
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#if defined(__sh1__) || defined(__sh2__)
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#if defined(__sh1__) || defined(__sh2__)
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_the_context->sr = (_isr << 4) & 0x00f0 ;
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_the_context->sr = (_isr << 4) & 0x00f0 ;
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#else
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#else
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_the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0);
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_the_context->sr = SH4_SR_MD | ((_isr << 4) & 0x00f0);
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#endif
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#endif
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_the_context->pr = (unsigned32*) _entry_point ;
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_the_context->pr = (unsigned32*) _entry_point ;
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#if 0 && SH_HAS_FPU
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#if 0 && SH_HAS_FPU
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/* Disable FPU if it is non-fp task */
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/* Disable FPU if it is non-fp task */
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if(!_is_fp)
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if(!_is_fp)
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_the_context->sr |= SH4_SR_FD;
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_the_context->sr |= SH4_SR_FD;
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#endif
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#endif
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}
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}
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