@c
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@c
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@c COPYRIGHT (c) 1988-2002.
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c All rights reserved.
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@c
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@c
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@c cpumodel.t,v 1.1 2002/07/30 21:43:53 joel Exp
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@c cpumodel.t,v 1.1 2002/07/30 21:43:53 joel Exp
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@c
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@c
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@chapter CPU Model Dependent Features
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@chapter CPU Model Dependent Features
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@section Introduction
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@section Introduction
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Microprocessors are generally classified into
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Microprocessors are generally classified into
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families with a variety of CPU models or implementations within
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families with a variety of CPU models or implementations within
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that family. Within a processor family, there is a high level
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that family. Within a processor family, there is a high level
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of binary compatibility. This family may be based on either an
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of binary compatibility. This family may be based on either an
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architectural specification or on maintaining compatibility with
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architectural specification or on maintaining compatibility with
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a popular processor. Recent microprocessor families such as the
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a popular processor. Recent microprocessor families such as the
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ARM, SPARC, and PA-RISC are based on an architectural specification
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ARM, SPARC, and PA-RISC are based on an architectural specification
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which is independent or any particular CPU model or
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which is independent or any particular CPU model or
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implementation. Older families such as the M68xxx and the iX86
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implementation. Older families such as the M68xxx and the iX86
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evolved as the manufacturer strived to produce higher
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evolved as the manufacturer strived to produce higher
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performance processor models which maintained binary
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performance processor models which maintained binary
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compatibility with older models.
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compatibility with older models.
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RTEMS takes advantage of the similarity of the
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RTEMS takes advantage of the similarity of the
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various models within a CPU family. Although the models do vary
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various models within a CPU family. Although the models do vary
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in significant ways, the high level of compatibility makes it
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in significant ways, the high level of compatibility makes it
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possible to share the bulk of the CPU dependent executive code
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possible to share the bulk of the CPU dependent executive code
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across the entire family. Each processor family supported by
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across the entire family. Each processor family supported by
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RTEMS has a list of features which vary between CPU models
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RTEMS has a list of features which vary between CPU models
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within a family. For example, the most common model dependent
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within a family. For example, the most common model dependent
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feature regardless of CPU family is the presence or absence of a
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feature regardless of CPU family is the presence or absence of a
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floating point unit or coprocessor. When defining the list of
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floating point unit or coprocessor. When defining the list of
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features present on a particular CPU model, one simply notes
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features present on a particular CPU model, one simply notes
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that floating point hardware is or is not present and defines a
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that floating point hardware is or is not present and defines a
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single constant appropriately. Conditional compilation is
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single constant appropriately. Conditional compilation is
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utilized to include the appropriate source code for this CPU
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utilized to include the appropriate source code for this CPU
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model's feature set. It is important to note that this means
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model's feature set. It is important to note that this means
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that RTEMS is thus compiled using the appropriate feature set
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that RTEMS is thus compiled using the appropriate feature set
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and compilation flags optimal for this CPU model used. The
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and compilation flags optimal for this CPU model used. The
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alternative would be to generate a binary which would execute on
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alternative would be to generate a binary which would execute on
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all family members using only the features which were always
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all family members using only the features which were always
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present.
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present.
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This chapter presents the set of features which vary
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This chapter presents the set of features which vary
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across ARM implementations and are of importance to RTEMS.
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across ARM implementations and are of importance to RTEMS.
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The set of CPU model feature macros are defined in the file
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The set of CPU model feature macros are defined in the file
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cpukit/score/cpu/arm/rtems/score/arm.h based upon the particular CPU
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cpukit/score/cpu/arm/rtems/score/arm.h based upon the particular CPU
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model defined on the compilation command line.
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model defined on the compilation command line.
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@section CPU Model Name
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@section CPU Model Name
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The macro @code{CPU_MODEL_NAME} is a string which designates
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The macro @code{CPU_MODEL_NAME} is a string which designates
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the architectural level of this CPU model. The following is
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the architectural level of this CPU model. The following is
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a list of the settings for this string based upon @code{gcc}
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a list of the settings for this string based upon @code{gcc}
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CPU model predefines:
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CPU model predefines:
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@example
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@example
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__ARM_ARCH4__ "ARMv4"
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__ARM_ARCH4__ "ARMv4"
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__ARM_ARCH4T__ "ARMv4T"
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__ARM_ARCH4T__ "ARMv4T"
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__ARM_ARCH5__ "ARMv5"
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__ARM_ARCH5__ "ARMv5"
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__ARM_ARCH5T__ "ARMv5T"
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__ARM_ARCH5T__ "ARMv5T"
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__ARM_ARCH5E__ "ARMv5E"
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__ARM_ARCH5E__ "ARMv5E"
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__ARM_ARCH5TE__ "ARMv5TE"
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__ARM_ARCH5TE__ "ARMv5TE"
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@end example
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@end example
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@section Count Leading Zeroes Instruction
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@section Count Leading Zeroes Instruction
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The macro @code{ARM_HAS_CLZ} is set to 1 to indicate that
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The macro @code{ARM_HAS_CLZ} is set to 1 to indicate that
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the architectural version has the @code{clz} instruction.
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the architectural version has the @code{clz} instruction.
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On ARM architectural version 5 and above, the count
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On ARM architectural version 5 and above, the count
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leading zeroes instruction (@code{clz}) is available and
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leading zeroes instruction (@code{clz}) is available and
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can be used to speed up the find first bit operation.
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can be used to speed up the find first bit operation.
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The use of this instruction significantly speeds up the
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The use of this instruction significantly speeds up the
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scheduling associated with a thread blocking.
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scheduling associated with a thread blocking.
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@section Floating Point Unit
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@section Floating Point Unit
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The macro ARM_HAS_FPU is set to 1 to indicate that
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The macro ARM_HAS_FPU is set to 1 to indicate that
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this CPU model has a hardware floating point unit and 0
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this CPU model has a hardware floating point unit and 0
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otherwise. It does not matter whether the hardware floating
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otherwise. It does not matter whether the hardware floating
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point support is incorporated on-chip or is an external
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point support is incorporated on-chip or is an external
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coprocessor.
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coprocessor.
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