@c
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@c
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@c COPYRIGHT (c) 1988-2002.
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@c COPYRIGHT (c) 1988-2002.
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@c On-Line Applications Research Corporation (OAR).
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@c On-Line Applications Research Corporation (OAR).
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@c All rights reserved.
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@c All rights reserved.
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@c
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@c
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@c cpumodel.t,v 1.7 2002/01/17 21:47:46 joel Exp
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@c cpumodel.t,v 1.7 2002/01/17 21:47:46 joel Exp
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@c
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@c
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@chapter CPU Model Dependent Features
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@chapter CPU Model Dependent Features
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@section Introduction
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@section Introduction
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Microprocessors are generally classified into
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Microprocessors are generally classified into
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families with a variety of CPU models or implementations within
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families with a variety of CPU models or implementations within
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that family. Within a processor family, there is a high level
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that family. Within a processor family, there is a high level
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of binary compatibility. This family may be based on either an
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of binary compatibility. This family may be based on either an
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architectural specification or on maintaining compatibility with
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architectural specification or on maintaining compatibility with
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a popular processor. Recent microprocessor families such as the
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a popular processor. Recent microprocessor families such as the
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PowerPC, SPARC, and PA-RISC are based on an architectural specification
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PowerPC, SPARC, and PA-RISC are based on an architectural specification
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which is independent or any particular CPU model or
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which is independent or any particular CPU model or
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implementation. Older families such as the M68xxx and the iX86
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implementation. Older families such as the M68xxx and the iX86
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evolved as the manufacturer strived to produce higher
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evolved as the manufacturer strived to produce higher
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performance processor models which maintained binary
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performance processor models which maintained binary
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compatibility with older models.
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compatibility with older models.
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RTEMS takes advantage of the similarity of the
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RTEMS takes advantage of the similarity of the
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various models within a CPU family. Although the models do vary
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various models within a CPU family. Although the models do vary
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in significant ways, the high level of compatibility makes it
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in significant ways, the high level of compatibility makes it
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possible to share the bulk of the CPU dependent executive code
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possible to share the bulk of the CPU dependent executive code
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across the entire family.
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across the entire family.
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@section CPU Model Feature Flags
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@section CPU Model Feature Flags
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Each processor family supported by RTEMS has a
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Each processor family supported by RTEMS has a
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list of features which vary between CPU models
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list of features which vary between CPU models
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within a family. For example, the most common model dependent
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within a family. For example, the most common model dependent
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feature regardless of CPU family is the presence or absence of a
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feature regardless of CPU family is the presence or absence of a
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floating point unit or coprocessor. When defining the list of
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floating point unit or coprocessor. When defining the list of
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features present on a particular CPU model, one simply notes
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features present on a particular CPU model, one simply notes
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that floating point hardware is or is not present and defines a
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that floating point hardware is or is not present and defines a
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single constant appropriately. Conditional compilation is
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single constant appropriately. Conditional compilation is
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utilized to include the appropriate source code for this CPU
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utilized to include the appropriate source code for this CPU
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model's feature set. It is important to note that this means
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model's feature set. It is important to note that this means
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that RTEMS is thus compiled using the appropriate feature set
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that RTEMS is thus compiled using the appropriate feature set
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and compilation flags optimal for this CPU model used. The
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and compilation flags optimal for this CPU model used. The
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alternative would be to generate a binary which would execute on
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alternative would be to generate a binary which would execute on
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all family members using only the features which were always
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all family members using only the features which were always
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present.
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present.
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This section presents the set of features which vary
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This section presents the set of features which vary
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across PowerPC implementations and are of importance to RTEMS.
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across PowerPC implementations and are of importance to RTEMS.
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The set of CPU model feature macros are defined in the file
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The set of CPU model feature macros are defined in the file
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c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
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c/src/exec/score/cpu/ppc/ppc.h based upon the particular CPU
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model defined on the compilation command line.
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model defined on the compilation command line.
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@subsection CPU Model Name
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@subsection CPU Model Name
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The macro CPU_MODEL_NAME is a string which designates
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The macro CPU_MODEL_NAME is a string which designates
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the name of this CPU model. For example, for the PowerPC 603e
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the name of this CPU model. For example, for the PowerPC 603e
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model, this macro is set to the string "PowerPC 603e".
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model, this macro is set to the string "PowerPC 603e".
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@subsection Floating Point Unit
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@subsection Floating Point Unit
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The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
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The macro PPC_HAS_FPU is set to 1 to indicate that this CPU model
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has a hardware floating point unit and 0 otherwise.
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has a hardware floating point unit and 0 otherwise.
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@subsection Alignment
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@subsection Alignment
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The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
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The macro PPC_ALIGNMENT is set to the PowerPC model's worst case alignment
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requirement for data types on a byte boundary. This value is used
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requirement for data types on a byte boundary. This value is used
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to derive the alignment restrictions for memory allocated from
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to derive the alignment restrictions for memory allocated from
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regions and partitions.
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regions and partitions.
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@subsection Cache Alignment
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@subsection Cache Alignment
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The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is
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The macro PPC_CACHE_ALIGNMENT is set to the line size of the cache. It is
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used to align the entry point of critical routines so that as much code
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used to align the entry point of critical routines so that as much code
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as possible can be retrieved with the initial read into cache. This
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as possible can be retrieved with the initial read into cache. This
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is done for the interrupt handler as well as the context switch routines.
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is done for the interrupt handler as well as the context switch routines.
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In addition, the "shortcut" data structure used by the PowerPC implementation
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In addition, the "shortcut" data structure used by the PowerPC implementation
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to ease access to data elements frequently accessed by RTEMS routines
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to ease access to data elements frequently accessed by RTEMS routines
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implemented in assembly language is aligned using this value.
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implemented in assembly language is aligned using this value.
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@subsection Maximum Interrupts
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@subsection Maximum Interrupts
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The macro PPC_INTERRUPT_MAX is set to the number of exception sources
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The macro PPC_INTERRUPT_MAX is set to the number of exception sources
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supported by this PowerPC model.
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supported by this PowerPC model.
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@subsection Has Double Precision Floating Point
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@subsection Has Double Precision Floating Point
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The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
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The macro PPC_HAS_DOUBLE is set to 1 to indicate that the PowerPC model
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has support for double precision floating point numbers. This is
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has support for double precision floating point numbers. This is
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important because the floating point registers need only be four bytes
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important because the floating point registers need only be four bytes
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wide (not eight) if double precision is not supported.
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wide (not eight) if double precision is not supported.
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@subsection Critical Interrupts
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@subsection Critical Interrupts
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The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
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The macro PPC_HAS_RFCI is set to 1 to indicate that the PowerPC model
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has the Critical Interrupt capability as defined by the IBM 403 models.
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has the Critical Interrupt capability as defined by the IBM 403 models.
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@subsection Use Multiword Load/Store Instructions
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@subsection Use Multiword Load/Store Instructions
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The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
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The macro PPC_USE_MULTIPLE is set to 1 to indicate that multiword load and
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store instructions should be used to perform context switch operations.
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store instructions should be used to perform context switch operations.
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The relative efficiency of multiword load and store instructions versus
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The relative efficiency of multiword load and store instructions versus
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an equivalent set of single word load and store instructions varies based
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an equivalent set of single word load and store instructions varies based
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upon the PowerPC model.
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upon the PowerPC model.
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@subsection Instruction Cache Size
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@subsection Instruction Cache Size
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The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
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The macro PPC_I_CACHE is set to the size in bytes of the instruction cache.
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@subsection Data Cache Size
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@subsection Data Cache Size
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The macro PPC_D_CACHE is set to the size in bytes of the data cache.
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The macro PPC_D_CACHE is set to the size in bytes of the data cache.
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@subsection Debug Model
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@subsection Debug Model
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The macro PPC_DEBUG_MODEL is set to indicate the debug support features
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The macro PPC_DEBUG_MODEL is set to indicate the debug support features
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present in this CPU model. The following debug support feature sets
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present in this CPU model. The following debug support feature sets
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are currently supported:
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are currently supported:
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@table @b
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@table @b
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@item @code{PPC_DEBUG_MODEL_STANDARD}
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@item @code{PPC_DEBUG_MODEL_STANDARD}
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indicates that the single-step trace enable (SE) and branch trace
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indicates that the single-step trace enable (SE) and branch trace
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enable (BE) bits in the MSR are supported by this CPU model.
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enable (BE) bits in the MSR are supported by this CPU model.
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@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
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@item @code{PPC_DEBUG_MODEL_SINGLE_STEP_ONLY}
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indicates that only the single-step trace enable (SE) bit in the MSR
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indicates that only the single-step trace enable (SE) bit in the MSR
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is supported by this CPU model.
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is supported by this CPU model.
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@item @code{PPC_DEBUG_MODEL_IBM4xx}
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@item @code{PPC_DEBUG_MODEL_IBM4xx}
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indicates that the debug exception enable (DE) bit in the MSR is supported
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indicates that the debug exception enable (DE) bit in the MSR is supported
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by this CPU model. At this time, this particular debug feature set
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by this CPU model. At this time, this particular debug feature set
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has only been seen in the IBM 4xx series.
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has only been seen in the IBM 4xx series.
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@end table
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@end table
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@subsection Low Power Model
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@subsection Low Power Model
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The macro PPC_LOW_POWER_MODE is set to indicate the low power model
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The macro PPC_LOW_POWER_MODE is set to indicate the low power model
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supported by this CPU model. The following low power modes are currently
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supported by this CPU model. The following low power modes are currently
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supported.
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supported.
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@table @b
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@table @b
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@item @code{PPC_LOW_POWER_MODE_NONE}
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@item @code{PPC_LOW_POWER_MODE_NONE}
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indicates that this CPU model has no low power mode support.
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indicates that this CPU model has no low power mode support.
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@item @code{PPC_LOW_POWER_MODE_STANDARD}
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@item @code{PPC_LOW_POWER_MODE_STANDARD}
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indicates that this CPU model follows the low power model defined for
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indicates that this CPU model follows the low power model defined for
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the PPC603e.
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the PPC603e.
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@end table
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@end table
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