OpenRISC Test Application for XESS XSV800 board
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OpenRISC Test Application for XESS XSV800 board
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===============================================
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Introduction
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Introduction
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++++++++++++
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++++++++++++
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This is OpenRISC Test Application. It contains OpenRISC 1200 and a set of
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This is OpenRISC Test Application. It contains OpenRISC 1200 and a set of
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OpenCores peripherals. The whole test application SoC (System-on-Chip) is
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OpenCores peripherals. The whole test application SoC (System-on-Chip) is
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designed with the XSV board in mind. Peripherals include UART16550, VGA CRT
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designed with the XSV board in mind. Peripherals include UART16550, VGA CRT
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controller, Audio controller, debug interface, Ethernet 10/100 MAC, SRAM
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controller, Audio controller, debug interface, Ethernet 10/100 MAC, SRAM
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and Flash controllers. CRT and Audio controller are optimized for XSV
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and Flash controllers. CRT and Audio controller are optimized for XSV
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board.
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board.
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OR1200 is a 32-bit RISC with harvard architecture. For XSV800 board it is
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OR1200 is a 32-bit RISC with harvard architecture. For XSV800 board it is
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configured with 4/4KB data/instruction caches, no D/I MMU (lack of
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configured with 4/4KB data/instruction caches, no D/I MMU (lack of
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BlockRAMs), and with programmable interrupt controller (PIC), MAC unit,
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BlockRAMs), and with programmable interrupt controller (PIC), MAC unit,
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tick timer unit and debug unit.
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tick timer unit and debug unit.
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Right now the whole system runs only at 10MHz. This is because we are
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right now focusing on getting functionality working and not optimizing.
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Running heavily constrained P&R takes much longer.
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Software for this test application consists of:
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Software for this test application consists of:
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- ORP (OpenRISC Reference Platform) monitor
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- ORP (OpenRISC Reference Platform) monitor
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- Linux (uClinux 2.0.36)
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- Linux (uClinux 2.0.36)
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- OpenRISC GNU Toolchain (ANSI C compiler GCC, debugger etc)
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- OpenRISC GNU Toolchain (ANSI C compiler GCC, debugger etc)
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Directory Structure
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Directory Structure
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+++++++++++++++++++
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+++++++++++++++++++
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bench: test bench (for simulation verification)
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bench: test bench (for simulation verification)
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doc: Some of the documentation (more on the OpenCores web)
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doc: Some of the documentation (more on the OpenCores web)
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rtl: Verilog sources of the XSV FPGA
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rtl: Verilog sources of the XSV FPGA SoC
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sim: For running simulation
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sim: For running simulation
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sw: Software example (OR1K GNU toolchain is available from OpenCores web)
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sw: Software example (OR1K GNU toolchain is available from OpenCores web)
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syn: Synthesis scripts/constraints for FPGA and ASIC
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syn: Synthesis scripts/constraints for FPGA and ASIC
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p&r: Download files for XSV800
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exo: Download files for XSV800
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Simulation
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Simulation
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++++++++++
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++++++++++
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N/A yet.
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N/A yet.
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Synthesis
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Synthesis
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+++++++++
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+++++++++
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N/A yet.
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N/A yet.
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XSV800 Programming Procedure
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XSV800 Programming Procedure
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++++++++++++++++++++++++++++
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++++++++++++++++++++++++++++
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XSV800 board must be configured for 10MHz operation (see XSV documentation
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XSV800 board must be configured for 10MHz operation (see XSV documentation
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how to set the clock divisor). If you want to use serial UART16550, or if
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how to set the clock divisor). If you want to use serial UART16550, or if
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you want to use OR1K GDB debugger, you will also have to program the CPLD
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you want to use OR1K GDB debugger, you will also have to program the CPLD
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with the cpld-tdm.svf file.
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with the cpld-tdm.svf file.
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Make sure you set the divisor first. Download the .exo file. Then download
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Make sure you set the divisor first. Download the .exo file. Then download
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the .svf file. Turn the power off.
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the .svf file. Turn the power off.
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Connect XSV800 board via RS232 cable to your PC, start terminal software.
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Connect XSV800 board via RS232 cable to your PC, start terminal software.
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Set baud rate to 19200, data/parity/stop to 8/N/1. Now you can turn the
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Set baud rate to 19200, data/parity/stop to 8/N/1. Now you can turn the
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power back on and the FPGA will be configured from the flash and the RISC
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power back on and the FPGA will be configured from the flash and the RISC
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will start booting.
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will start booting.
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What will boot depends what software is compiled and merged into the .exo
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What will boot depends what software is compiled and merged into the .exo
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file. It can be the ORP (OpenRISC Reference Platform) monitor, or Linux,
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file. It can be the ORP (OpenRISC Reference Platform) monitor, or Linux,
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or something else.
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or something else.
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If you have problems downloading the files to the XSV board, please make sure
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If you have problems downloading the files to the XSV board, please make sure
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you first read the XSV manual and check the XESS website and XESS forum.
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you first read the XSV manual and check the XESS website and XESS forum.
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Want to help?
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Want to help?
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+++++++++++++
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+++++++++++++
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We need companies, universities and individuals to help us in HW and SW areas.
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We need companies, universities and individuals to help us in HW and SW areas.
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If you want to help, first go to http://www.opencores.org/cores/or1k-new/ and
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If you want to help, first go to http://www.opencores.org/cores/or1k-new/ and
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check the status and TODOs. Also read the documentation.
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check the status and TODOs. Also read the documentation.
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Subscribe to the openrisc mailing list (and read OpenCores FAQ before you post):
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Subscribe to the openrisc mailing list (and read OpenCores FAQ before you post):
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- if you want more information
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- if you want more information
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- if you want to help with the HW design (test application(s), verification of the
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- if you want to help with the HW design (test application(s), verification of the
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OR1200, optimization of OR1200, development of new units etc)
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OR1200, optimization of OR1200, development of new units etc)
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- if you want to develop software
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- if you want to develop software
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If you want to help in some other area, please subscribe to main opencores
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If you want to help in some other area, please subscribe to main opencores
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mailing list.
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mailing list.
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About OpenCores
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About OpenCores
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===============
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===============
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OpenCores is an organization that developes free, open source soft cores. If
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OpenCores is an organization that developes free, open source soft cores. If
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you would like more information, please visit us at http://www.opencores.org.
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you would like more information, please visit us at http://www.opencores.org.
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We invite companies and individuals to help us in our mission. We need
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We invite companies and individuals to help us in our mission. We need
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experienced designers to verify and design new cores.
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experienced designers to verify and design new cores.
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And we need companies and universities to use our existing verified cores in
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And we need companies and universities to use our existing verified cores in
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projects (the whole purpose of OpenCores is to design free cores that someone
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projects (the whole purpose of OpenCores is to design free cores that someone
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will use !).
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will use !).
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--
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--
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Damjan Lampret, Mar/2002
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Damjan Lampret, Mar/2002
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$Log: not supported by cvs2svn $
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$Log: not supported by cvs2svn $
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Revision 1.1.1.1 2002/03/21 20:47:47 lampret
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First import of the "new" XESS XSV environment.
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