/*
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/*
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* linux/arch/arm/boot/compressed/head.S
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* linux/arch/arm/boot/compressed/head.S
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*
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*
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* Copyright (C) 1996 Russell King
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* Copyright (C) 1996 Russell King
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*/
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*/
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.text
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.text
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/*
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/*
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* sort out different calling conventions
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* sort out different calling conventions
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*/
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*/
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start: teq r0, #0
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start: teq r0, #0
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beq newparams
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beq newparams
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mov r4, #0x02000000
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mov r4, #0x02000000
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add r4, r4, #0x7C000
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add r4, r4, #0x7C000
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mov r3, #0x4000
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mov r3, #0x4000
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sub r3, r3, #4
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sub r3, r3, #4
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1: ldmia r0!, {r5 - r12}
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1: ldmia r0!, {r5 - r12}
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stmia r4!, {r5 - r12}
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stmia r4!, {r5 - r12}
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subs r3, r3, #32
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subs r3, r3, #32
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bpl 1b
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bpl 1b
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newparams: adr r2, LC0
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newparams: adr r2, LC0
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ldmia r2, {r2, r3, r4, r5, r6, sp}
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ldmia r2, {r2, r3, r4, r5, r6, sp}
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adr r7, start
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adr r7, start
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sub r6, r7, r6
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sub r6, r7, r6
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/*
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/*
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* Relocate pointers
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* Relocate pointers
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*/
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*/
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add r2, r2, r6
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add r2, r2, r6
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add r3, r3, r6
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add r3, r3, r6
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add r5, r5, r6
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add r5, r5, r6
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add sp, sp, r6
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add sp, sp, r6
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/*
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/*
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* Clear zero-init
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* Clear zero-init
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*/
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*/
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mov r6, #0
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mov r6, #0
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1: str r6, [r2], #4
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1: str r6, [r2], #4
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cmp r2, r3
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cmp r2, r3
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blt 1b
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blt 1b
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str r1, [r5] @ save architecture
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str r1, [r5] @ save architecture
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/*
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/*
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* Uncompress the kernel
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* Uncompress the kernel
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*/
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*/
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mov r1, #0x8000
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mov r1, #0x8000
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add r2, r2, r1, lsl #1 @ Add 64k for malloc
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add r2, r2, r1, lsl #1 @ Add 64k for malloc
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sub r1, r1, #1
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sub r1, r1, #1
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add r2, r2, r1
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add r2, r2, r1
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bic r5, r2, r1 @ decompress kernel to after end of the compressed
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bic r5, r2, r1 @ decompress kernel to after end of the compressed
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mov r0, r5
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mov r0, r5
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bl _decompress_kernel
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bl _decompress_kernel
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add r0, r0, #7
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add r0, r0, #7
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bic r2, r0, #7
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bic r2, r0, #7
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/*
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/*
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* Now move the kernel to the correct location (r5 -> r4, len r0)
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* Now move the kernel to the correct location (r5 -> r4, len r0)
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*/
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*/
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mov r0, r4 @ r0 = start of real kernel
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mov r0, r4 @ r0 = start of real kernel
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mov r1, r5 @ r1 = start of kernel image
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mov r1, r5 @ r1 = start of kernel image
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add r3, r5, r2 @ r3 = end of kernel
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add r3, r5, r2 @ r3 = end of kernel
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adr r4, movecode
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adr r4, movecode
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adr r5, movecodeend
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adr r5, movecodeend
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1: ldmia r4!, {r6 - r12, lr}
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1: ldmia r4!, {r6 - r12, lr}
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stmia r3!, {r6 - r12, lr}
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stmia r3!, {r6 - r12, lr}
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cmp r4, r5
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cmp r4, r5
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blt 1b
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blt 1b
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mrc p15, 0, r5, c0, c0
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mrc p15, 0, r5, c0, c0
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eor r5, r5, #0x44 << 24
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eor r5, r5, #0x44 << 24
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eor r5, r5, #0x01 << 16
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eor r5, r5, #0x01 << 16
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eor r5, r5, #0xa1 << 8
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eor r5, r5, #0xa1 << 8
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movs r5, r5, lsr #4
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movs r5, r5, lsr #4
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mov r5, #0
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mov r5, #0
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mcreq p15, 0, r5, c7, c5, 0 @ flush I cache
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mcreq p15, 0, r5, c7, c5, 0 @ flush I cache
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ldr r5, LC0 + 12 @ get architecture
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ldr r5, LC0 + 12 @ get architecture
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ldr r5, [r5]
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ldr r5, [r5]
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add pc, r1, r2 @ Call move code
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add pc, r1, r2 @ Call move code
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/*
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/*
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* r0 = length, r1 = to, r2 = from
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* r0 = length, r1 = to, r2 = from
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*/
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*/
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movecode: add r3, r1, r2
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movecode: add r3, r1, r2
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mov r4, r0
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mov r4, r0
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1: ldmia r1!, {r6 - r12, lr}
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1: ldmia r1!, {r6 - r12, lr}
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stmia r0!, {r6 - r12, lr}
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stmia r0!, {r6 - r12, lr}
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cmp r1, r3
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cmp r1, r3
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blt 1b
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blt 1b
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mrc p15, 0, r0, c0, c0
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mrc p15, 0, r0, c0, c0
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eor r0, r0, #0x44 << 24
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eor r0, r0, #0x44 << 24
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eor r0, r0, #0x01 << 16
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eor r0, r0, #0x01 << 16
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eor r0, r0, #0xa1 << 8
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eor r0, r0, #0xa1 << 8
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movs r0, r0, lsr #4
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movs r0, r0, lsr #4
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mov r0, #0
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mov r0, #0
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mcreq p15, 0, r0, c7, c5, 0 @ flush I cache
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mcreq p15, 0, r0, c7, c5, 0 @ flush I cache
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mov r1, r5 @ call kernel correctly
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mov r1, r5 @ call kernel correctly
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add pc, r4, #0x20 @ call via EXEC entry
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add pc, r4, #0x20 @ call via EXEC entry
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movecodeend:
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movecodeend:
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LC0: .word __edata
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LC0: .word __edata
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.word __end
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.word __end
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.word LOADADDR
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.word LOADADDR
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.word _architecture
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.word _architecture
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.word start
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.word start
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.word _user_stack+4096
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.word _user_stack+4096
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.bss
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.bss
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_architecture: .word 0
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_architecture: .word 0
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