/*
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/*
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* linux/arch/arm/drivers/char/serialecho.c
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* linux/arch/arm/drivers/char/serialecho.c
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*
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*
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* Serial echoing for kernel console messages.
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* Serial echoing for kernel console messages.
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*/
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*/
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#if defined (CONFIG_ARCH_A5K) || defined (CONFIG_ARCH_RPC) || defined(CONFIG_ARCH_EBSA110)
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#if defined (CONFIG_ARCH_A5K) || defined (CONFIG_ARCH_RPC) || defined(CONFIG_ARCH_EBSA110)
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#include <asm/io.h>
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#include <asm/io.h>
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#include <linux/serial_reg.h>
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#include <linux/serial_reg.h>
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extern int serial_echo_init (int base);
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extern int serial_echo_init (int base);
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extern int serial_echo_print (const char *s);
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extern int serial_echo_print (const char *s);
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/*
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/*
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* this defines the address for the port to which printk echoing is done
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* this defines the address for the port to which printk echoing is done
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* when CONFIG_SERIAL_ECHO is defined
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* when CONFIG_SERIAL_ECHO is defined
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*/
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*/
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#ifndef SERIAL_ECHO_PORT
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#ifndef SERIAL_ECHO_PORT
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#define SERIAL_ECHO_PORT 0x3f8 /* internal serial port */
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#define SERIAL_ECHO_PORT 0x3f8 /* internal serial port */
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#endif
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#endif
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#ifndef SERIAL_ECHO_DIVISOR
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#ifndef SERIAL_ECHO_DIVISOR
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#define SERIAL_ECHO_DIVISOR 12 /* 9600 baud */
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#define SERIAL_ECHO_DIVISOR 12 /* 9600 baud */
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#endif
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#endif
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static int serial_echo_port = 0;
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static int serial_echo_port = 0;
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#define serial_echo_outb(v,a) outb((v),(a)+serial_echo_port)
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#define serial_echo_outb(v,a) outb((v),(a)+serial_echo_port)
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#define serial_echo_inb(a) inb((a)+serial_echo_port)
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#define serial_echo_inb(a) inb((a)+serial_echo_port)
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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#define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
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/* wait for the transmitter & holding register to empty */
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/* wait for the transmitter & holding register to empty */
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#define WAIT_FOR_XMITR \
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#define WAIT_FOR_XMITR \
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do { \
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do { \
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lsr = serial_echo_inb (UART_LSR); \
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lsr = serial_echo_inb (UART_LSR); \
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} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
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} while ((lsr & BOTH_EMPTY) != BOTH_EMPTY)
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/*
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/*
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* These two functions abstract the actual communications with the
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* These two functions abstract the actual communications with the
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* debug port. This is so we can change the underlying communications
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* debug port. This is so we can change the underlying communications
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* mechanism without modifying the rest of the code.
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* mechanism without modifying the rest of the code.
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*/
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*/
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int serial_echo_print (const char *s)
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int serial_echo_print (const char *s)
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{
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{
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int lsr, ier;
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int lsr, ier;
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int i;
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int i;
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if (!serial_echo_port)
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if (!serial_echo_port)
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return 0;
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return 0;
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/*
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/*
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* First save the IER then disable interrupts
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* First save the IER then disable interrupts
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*/
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*/
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ier = serial_echo_inb (UART_IER);
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ier = serial_echo_inb (UART_IER);
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serial_echo_outb (0x00, UART_IER);
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serial_echo_outb (0x00, UART_IER);
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/*
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/*
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* Now do each character
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* Now do each character
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*/
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*/
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for (i = 0; *s; i++, s++) {
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for (i = 0; *s; i++, s++) {
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WAIT_FOR_XMITR;
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WAIT_FOR_XMITR;
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/* send the character out. */
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/* send the character out. */
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serial_echo_outb (*s, UART_TX);
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serial_echo_outb (*s, UART_TX);
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/* if a LF, also do CR... */
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/* if a LF, also do CR... */
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if (*s == 10) {
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if (*s == 10) {
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WAIT_FOR_XMITR;
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WAIT_FOR_XMITR;
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serial_echo_outb (13, UART_TX);
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serial_echo_outb (13, UART_TX);
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}
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}
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}
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}
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/*
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/*
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* Finally, wait for transmitter & holding register to empty
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* Finally, wait for transmitter & holding register to empty
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* and restore the IER.
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* and restore the IER.
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*/
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*/
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WAIT_FOR_XMITR;
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WAIT_FOR_XMITR;
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serial_echo_outb (ier, UART_IER);
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serial_echo_outb (ier, UART_IER);
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return 0;
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return 0;
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}
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}
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int serial_echo_init (int base)
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int serial_echo_init (int base)
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{
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{
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int comstat, hi, lo;
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int comstat, hi, lo;
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if (base != 0x3f8 && base != 0x2f8) {
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if (base != 0x3f8 && base != 0x2f8) {
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serial_echo_port = 0;
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serial_echo_port = 0;
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return 0;
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return 0;
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} else
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} else
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serial_echo_port = base;
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serial_echo_port = base;
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/*
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/*
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* Read the Divisor Latch
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* Read the Divisor Latch
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*/
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*/
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comstat = serial_echo_inb (UART_LCR);
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comstat = serial_echo_inb (UART_LCR);
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serial_echo_outb (comstat | UART_LCR_DLAB, UART_LCR);
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serial_echo_outb (comstat | UART_LCR_DLAB, UART_LCR);
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hi = serial_echo_inb (UART_DLM);
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hi = serial_echo_inb (UART_DLM);
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lo = serial_echo_inb (UART_DLL);
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lo = serial_echo_inb (UART_DLL);
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serial_echo_outb (comstat, UART_LCR);
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serial_echo_outb (comstat, UART_LCR);
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/*
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/*
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* now do a hardwired init
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* now do a hardwired init
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*/
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*/
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serial_echo_outb (0x03, UART_LCR); /* No parity, 8 bits, 1 stop */
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serial_echo_outb (0x03, UART_LCR); /* No parity, 8 bits, 1 stop */
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serial_echo_outb (0x83, UART_LCR); /* Access divisor latch */
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serial_echo_outb (0x83, UART_LCR); /* Access divisor latch */
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serial_echo_outb (SERIAL_ECHO_DIVISOR >> 8, UART_DLM);
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serial_echo_outb (SERIAL_ECHO_DIVISOR >> 8, UART_DLM);
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serial_echo_outb (SERIAL_ECHO_DIVISOR & 0xff, UART_DLL);
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serial_echo_outb (SERIAL_ECHO_DIVISOR & 0xff, UART_DLL);
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serial_echo_outb (0x03, UART_LCR); /* Done with divisor */
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serial_echo_outb (0x03, UART_LCR); /* Done with divisor */
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/* Prior to disabling interrupts, read the LSR and RBR
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/* Prior to disabling interrupts, read the LSR and RBR
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* registers
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* registers
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*/
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*/
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comstat = serial_echo_inb (UART_LSR); /* COM? LSR */
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comstat = serial_echo_inb (UART_LSR); /* COM? LSR */
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comstat = serial_echo_inb (UART_RX); /* COM? RBR */
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comstat = serial_echo_inb (UART_RX); /* COM? RBR */
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serial_echo_outb (0x00, UART_IER); /* Disable all interrupts */
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serial_echo_outb (0x00, UART_IER); /* Disable all interrupts */
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return 0;
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return 0;
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}
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}
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#endif
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#endif
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