/*
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/*
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* linux/arch/armnommu/kernel/head-arm-trio.S
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* linux/arch/armnommu/kernel/head-arm-trio.S
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*
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*
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* Copyright (C) 1999 Aplio SA
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* Copyright (C) 1999 Aplio SA
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*
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*
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* Kernel 32 bit startup code for APLIO Trio chip
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* Kernel 32 bit startup code for APLIO Trio chip
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*/
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*/
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#include
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#include
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#include
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#include
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#include
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#include
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.text
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.text
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.align
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.align
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/*----------------------------------
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/*----------------------------------
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* DMC & SMC Base Addresses
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* DMC & SMC Base Addresses
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* ----------------------------------
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* ----------------------------------
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*/
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*/
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#define ARM_MODE_SVC 0x13
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#define ARM_MODE_SVC 0x13
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#define DRAM_BASE 0x00000000
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#define DRAM_BASE 0x00000000
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#define DRAM_SIZE 0x400000
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#define DRAM_SIZE 0x400000
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#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
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#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
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.globl __entry,_entry
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.globl __entry,_entry
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.globl __stext,_stext
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.globl __stext,_stext
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.globl _start,start
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.globl _start,start
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start:
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start:
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_start:
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_start:
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_stext:
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_stext:
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_entry:
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_entry:
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__stext:
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__stext:
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__entry:
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__entry:
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bl config_timer1
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bl config_timer1
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#if 0
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#if 0
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/*
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/*
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| Initialise the Memory Controller
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| Initialise the Memory Controller
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| ---------------------------------
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| ---------------------------------
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| Copy the Image of the SMC & DMC Memory Controller
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| Copy the Image of the SMC & DMC Memory Controller
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*/
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*/
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adr r10, InitTableSMC /* ; get the address of the SMC chip select image */
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adr r10, InitTableSMC /* ; get the address of the SMC chip select image */
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adr r11, InitTableDMC /* ; get the address of the DMC chip select image */
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adr r11, InitTableDMC /* ; get the address of the DMC chip select image */
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/*
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/*
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;- | Load the address where to jump, Zero out the most significant bits.
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;- | Load the address where to jump, Zero out the most significant bits.
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*/
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*/
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#if 0
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#if 0
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ldr r0, =InitRemap /* ; get the real jump address ( after remap ) */
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ldr r0, =InitRemap /* ; get the real jump address ( after remap ) */
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mov r0, r0, LSL #12
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mov r0, r0, LSL #12
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mov r0, r0, LSR #12
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mov r0, r0, LSR #12
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/*
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/*
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;- | Calculate new PC after the SMC and DMC have been reconfigured.
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;- | Calculate new PC after the SMC and DMC have been reconfigured.
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*/
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*/
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ldr r1, [r10]
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ldr r1, [r10]
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ldr r2, =0xFFF00000
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ldr r2, =0xFFF00000
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and r1, r2, r1
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and r1, r2, r1
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add r12, r0, r1
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add r12, r0, r1
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#endif
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#endif
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/*
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/*
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;- | Copy The SMC Image into registers 0,1,2
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;- | Copy The SMC Image into registers 0,1,2
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*/
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*/
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ldmia r10!, {r0-r3}
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ldmia r10!, {r0-r3}
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/*
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/*
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;- | Copy The DMC Image into registers 3,4,5
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;- | Copy The DMC Image into registers 3,4,5
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*/
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*/
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ldmia r11!, {r4-r7}
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ldmia r11!, {r4-r7}
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/*
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/*
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;- Store the SMC values (r3 contains the base address of the SMC controller)
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;- Store the SMC values (r3 contains the base address of the SMC controller)
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*/
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*/
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stmia r3!, {r0-r2}
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stmia r3!, {r0-r2}
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/*
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/*
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;- Store the DMC values (r7 contains the base address of the DMC controller)
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;- Store the DMC values (r7 contains the base address of the DMC controller)
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*/
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*/
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stmia r7!, {r4-r6}
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stmia r7!, {r4-r6}
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/*
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/*
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;- | Jump to ROM at its new address
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;- | Jump to ROM at its new address
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*/
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*/
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new_remap_entry:
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new_remap_entry:
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#if 0
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#if 0
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mov pc, r12 /* jump and break the pipeline */
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mov pc, r12 /* jump and break the pipeline */
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#endif
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#endif
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#endif
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#endif
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/* we get here when RAM is mapped to address 0 */
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/* we get here when RAM is mapped to address 0 */
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InitRemap:
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InitRemap:
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/*
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/*
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; Setup the SVC mode and stack pointer on the top of the internal RAM
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; Setup the SVC mode and stack pointer on the top of the internal RAM
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*/
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*/
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mov r0, #(ARM_MODE_SVC | I_BIT | F_BIT ) /* ; No interrupts */
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mov r0, #(ARM_MODE_SVC | I_BIT | F_BIT ) /* ; No interrupts */
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msr cpsr, r0
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msr cpsr, r0
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ldr r13, =DRAM_LIMIT
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ldr r13, =DRAM_LIMIT
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/*
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/*
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;
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;
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; Call the Config routines...
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; Call the Config routines...
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;
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;
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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*/
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*/
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bl config_PIO
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bl config_PIO
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adr r5, LC0
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adr r5, LC0
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ldmia r5, {r5, r6, r8, sp} @ Setup stack
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ldmia r5, {r5, r6, r8, sp} @ Setup stack
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mov r4, #0
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mov r4, #0
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1: cmp r5, r8 @ Clear BSS
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1: cmp r5, r8 @ Clear BSS
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strcc r4, [r5],#4
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strcc r4, [r5],#4
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bcc 1b
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bcc 1b
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/*
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/*
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bl config_usart0
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bl config_usart0
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bl config_usart1
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bl config_usart1
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*/
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*/
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ldr r2,=0x41007000
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ldr r2,=0x41007000
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str r2,[r6]
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str r2,[r6]
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mov fp, #0
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mov fp, #0
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b start_kernel
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b start_kernel
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LC0: .long edata
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LC0: .long edata
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.long arm_id
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.long arm_id
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.long end
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.long end
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.long init_user_stack + 4096
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.long init_user_stack + 4096
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InitTableDMC:
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InitTableDMC:
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.long 0x0000000D /* DMC MRO */
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.long 0x0000000D /* DMC MRO */
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.long 0x1000000D /* DMC MR1 */
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.long 0x1000000D /* DMC MR1 */
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.long 0x03 /* DMC CR */
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.long 0x03 /* DMC CR */
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.long DMC_BASE /* DMC Base Address */
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.long DMC_BASE /* DMC Base Address */
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InitTableSMC:
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InitTableSMC:
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.long 0x40003125 /* SMC CSR0 */
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.long 0x40003125 /* SMC CSR0 */
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.long 0 /* SMC CSR1 */
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.long 0 /* SMC CSR1 */
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.long 0 /* SMC CSR2 */
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.long 0 /* SMC CSR2 */
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.long SMC_BASE /* SMC Base Address */
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.long SMC_BASE /* SMC Base Address */
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InitPIOs:
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InitPIOs:
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/*
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/*
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;- |
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;- |
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;- | Driving a Low to any of these lines switches the LEDs on.
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;- | Driving a Low to any of these lines switches the LEDs on.
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;- |
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;- |
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;- | PIOA 9 OUTPUT LED D28
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;- | PIOA 9 OUTPUT LED D28
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;- | PIOA 10-20 OUTPUT LED D17-27
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;- | PIOA 10-20 OUTPUT LED D17-27
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;- | PIOA 21-31 OUTPUT LED D29-D39
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;- | PIOA 21-31 OUTPUT LED D29-D39
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;- | PIOB 10-15 OUTPUT LED D40-D45
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;- | PIOB 10-15 OUTPUT LED D40-D45
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*/
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*/
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config_PIO:
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config_PIO:
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/*
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/*
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;- Configure PIOA
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;- Configure PIOA
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*/
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*/
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ldr r1, PIOA_Enable_Reg
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ldr r1, PIOA_Enable_Reg
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ldr r2, PIOA_Enable_Value
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ldr r2, PIOA_Enable_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOA_Disable_Reg
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ldr r1, PIOA_Disable_Reg
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ldr r2, PIOA_Disable_Value
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ldr r2, PIOA_Disable_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOA_COD_Reg
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ldr r1, PIOA_COD_Reg
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ldr r2, PIOA_COD_Value
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ldr r2, PIOA_COD_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOA_OE_Reg
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ldr r1, PIOA_OE_Reg
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ldr r2, PIOA_OE_Value
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ldr r2, PIOA_OE_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOA_OD_Reg
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ldr r1, PIOA_OD_Reg
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ldr r2, PIOA_OD_Value
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ldr r2, PIOA_OD_Value
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str r2, [r1]
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str r2, [r1]
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/*
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/*
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;- Configure PIOB
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;- Configure PIOB
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*/
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*/
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ldr r1, PIOB_Enable_Reg
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ldr r1, PIOB_Enable_Reg
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ldr r2, PIOB_Enable_Value
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ldr r2, PIOB_Enable_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOB_Disable_Reg
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ldr r1, PIOB_Disable_Reg
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ldr r2, PIOB_Disable_Value
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ldr r2, PIOB_Disable_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOB_COD_Reg
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ldr r1, PIOB_COD_Reg
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ldr r2, PIOB_COD_Value
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ldr r2, PIOB_COD_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOB_OE_Reg
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ldr r1, PIOB_OE_Reg
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ldr r2, PIOB_OE_Value
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ldr r2, PIOB_OE_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, PIOB_OD_Reg
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ldr r1, PIOB_OD_Reg
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ldr r2, PIOB_OD_Value
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ldr r2, PIOB_OD_Value
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str r2, [r1]
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str r2, [r1]
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mov pc,lr
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mov pc,lr
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/*
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/*
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;
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;
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; PIO configuration details
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; PIO configuration details
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;
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;
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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*/
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*/
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PIOA_Enable_Reg:
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PIOA_Enable_Reg:
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.long 0xFF00C000
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.long 0xFF00C000
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PIOA_Enable_Value:
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PIOA_Enable_Value:
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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PIOA_Disable_Reg:
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PIOA_Disable_Reg:
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.long 0xFF00C004
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.long 0xFF00C004
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PIOA_Disable_Value:
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PIOA_Disable_Value:
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.long 0x00000000
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.long 0x00000000
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PIOA_OE_Reg:
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PIOA_OE_Reg:
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.long 0xFF00C010
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.long 0xFF00C010
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PIOA_OE_Value:
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PIOA_OE_Value:
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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PIOA_OD_Reg:
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PIOA_OD_Reg:
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.long 0xFF00C014
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.long 0xFF00C014
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PIOA_OD_Value:
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PIOA_OD_Value:
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.long 0x00000000
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.long 0x00000000
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PIOA_COD_Reg:
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PIOA_COD_Reg:
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.long 0xFF00C034
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.long 0xFF00C034
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PIOA_COD_Value:
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PIOA_COD_Value:
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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PIOB_Enable_Reg:
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PIOB_Enable_Reg:
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.long 0xFF010000
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.long 0xFF010000
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PIOB_Enable_Value:
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PIOB_Enable_Value:
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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PIOB_Disable_Reg:
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PIOB_Disable_Reg:
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.long 0xFF010004
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.long 0xFF010004
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PIOB_Disable_Value:
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PIOB_Disable_Value:
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.long 0x000003FF
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.long 0x000003FF
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PIOB_OE_Reg:
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PIOB_OE_Reg:
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.long 0xFF010010
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.long 0xFF010010
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PIOB_OE_Value:
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PIOB_OE_Value:
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.long 0x0000FE4B
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.long 0x0000FE4B
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PIOB_OD_Reg:
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PIOB_OD_Reg:
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.long 0xFF010014
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.long 0xFF010014
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PIOB_OD_Value:
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PIOB_OD_Value:
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.long 0x000001B4
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.long 0x000001B4
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PIOB_COD_Reg:
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PIOB_COD_Reg:
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.long 0xFF00C034
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.long 0xFF00C034
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PIOB_COD_Value:
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PIOB_COD_Value:
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.long 0xFFFFFFFF
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.long 0xFFFFFFFF
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/*
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/*
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;
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;
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; Configure timer 1, This timer channel is connected to DRAM controller
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; Configure timer 1, This timer channel is connected to DRAM controller
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; and is used as the trigger for a DRAM refresh cycle.
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; and is used as the trigger for a DRAM refresh cycle.
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; Trashes r1, r2
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; Trashes r1, r2
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;
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;
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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*/
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*/
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config_timer1:
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config_timer1:
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ldr r1, TC_CMR_REG
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ldr r1, TC_CMR_REG
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ldr r2, TC_CMR_Value
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ldr r2, TC_CMR_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, TC_RA_REG
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ldr r1, TC_RA_REG
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ldr r2, TC_RA_Value
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ldr r2, TC_RA_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, TC_RC_REG
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ldr r1, TC_RC_REG
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ldr r2, TC_RC_Value
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ldr r2, TC_RC_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, TC_CCR_REG
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ldr r1, TC_CCR_REG
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ldr r2, TC_CCR_Value
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ldr r2, TC_CCR_Value
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str r2, [r1]
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str r2, [r1]
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ldr r1, TC_BCR_REG
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ldr r1, TC_BCR_REG
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ldr r2, TC_CCR_Value
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ldr r2, TC_CCR_Value
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str r2, [r1]
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str r2, [r1]
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mov pc, lr
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mov pc, lr
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/*
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/*
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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;
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;
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; Timer Control Configuration Data
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; Timer Control Configuration Data
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;
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;
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;------------------------------------------------------------------------------
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;------------------------------------------------------------------------------
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*/
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*/
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TC_CMR_REG:
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TC_CMR_REG:
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.long 0xFF014004
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.long 0xFF014004
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TC_CMR_Value:
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TC_CMR_Value:
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.long 0xFFFFC000
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.long 0xFFFFC000
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TC_RA_REG:
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TC_RA_REG:
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.long 0xFF014014
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.long 0xFF014014
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TC_RA_Value:
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TC_RA_Value:
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.long 0x00000047
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.long 0x00000047
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TC_RC_REG:
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TC_RC_REG:
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.long 0xFF01401C
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.long 0xFF01401C
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TC_RC_Value:
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TC_RC_Value:
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.long 0x00000047
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.long 0x00000047
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TC_CCR_REG:
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TC_CCR_REG:
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.long 0xFF014000
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.long 0xFF014000
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TC_CCR_Value:
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TC_CCR_Value:
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.long 0x00000001
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.long 0x00000001
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TC_BCR_REG:
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TC_BCR_REG:
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.long 0xFF0140C0
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.long 0xFF0140C0
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