URL https://opencores.org/ocsvn/or1k_old/or1k_old/trunk

Subversion Repositories or1k_old

[/] [or1k_old/] [trunk/] [rc203soc/] [sw/] [uClinux/] [arch/] [or32/] [board/] [comp.ld] - Diff between revs 1765 and 1782

Rev 1765	Rev 1782
`MEMORY`	`MEMORY`
`{`	`{`
`ram : ORIGIN = 0x01000000, LENGTH = 0x00010000`	`ram : ORIGIN = 0x01000000, LENGTH = 0x00010000`
`flash : ORIGIN = 0x04000000, LENGTH = 0x00200000`	`flash : ORIGIN = 0x04000000, LENGTH = 0x00200000`
`}`	`}`

`SECTIONS`	`SECTIONS`
`{`	`{`
`.reset :`	`.reset :`
`{`	`{`
`*(.reset)`	`*(.reset)`
`} > flash`	`} > flash`

`.text :`	`.text :`
`{`	`{`
`*(.text)`	`*(.text)`
`} > flash`	`} > flash`

`.linux ALIGN(0x4):`	`.linux ALIGN(0x4):`
`{`	`{`
`_linux_start = .;`	`_linux_start = .;`
`*(.linux)`	`*(.linux)`
`_linux_end = .;`	`_linux_end = .;`
`_src_beg = .;`	`_src_beg = .;`
`} > flash`	`} > flash`

`.data :`	`.data :`
`AT ( ADDR (.text) + SIZEOF (.text) + SIZEOF (.linux))`	`AT ( ADDR (.text) + SIZEOF (.text) + SIZEOF (.linux))`
`{`	`{`
`_dst_beg = .;`	`_dst_beg = .;`
`*(.rodata)`	`*(.rodata)`
`*(.data)`	`*(.data)`
`_dst_end = .;`	`_dst_end = .;`
`} > ram`	`} > ram`

`.bss :`	`.bss :`
`{`	`{`
`*(.bss)`	`*(.bss)`
`} > ram`	`} > ram`

`.stack ALIGN(0x10) (NOLOAD):`	`.stack ALIGN(0x10) (NOLOAD):`
`{`	`{`
`*(.stack)`	`*(.stack)`
`} > ram`	`} > ram`
`}`	`}`