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https://opencores.org/ocsvn/or1k_old/or1k_old/trunk
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Rev 1624 |
Rev 1765 |
MEMORY
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MEMORY
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{
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{
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romvec : ORIGIN = 0xf0000000, LENGTH = 0x2000
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romvec : ORIGIN = 0xf0000000, LENGTH = 0x2000
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flash : ORIGIN = 0xf0002000, LENGTH = 0x00800000 - 0x2000
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flash : ORIGIN = 0xf0002000, LENGTH = 0x00800000 - 0x2000
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eflash : ORIGIN = 0xf0800000, LENGTH = 0
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eflash : ORIGIN = 0xf0800000, LENGTH = 0
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ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000
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ramvec : ORIGIN = 0x00000000, LENGTH = 0x00002000
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ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000
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ram : ORIGIN = 0x00002000, LENGTH = 0x00800000 - 0x2000
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eram : ORIGIN = 0x00800000, LENGTH = 0
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eram : ORIGIN = 0x00800000, LENGTH = 0
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}
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}
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SECTIONS
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SECTIONS
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{
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{
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.romvec :
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.romvec :
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{
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{
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__romvec = . ;
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__romvec = . ;
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*(.romvec)
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*(.romvec)
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} > romvec
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} > romvec
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.text :
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.text :
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{
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{
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___rom_start = . ;
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___rom_start = . ;
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text_start = . ;
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text_start = . ;
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*(.text)
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*(.text)
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} > flash
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} > flash
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.rodata :
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.rodata :
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{
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{
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*(.rodata)
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*(.rodata)
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__etext = . ;
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__etext = . ;
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} > flash
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} > flash
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.initrd :
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.initrd :
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{
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{
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__initrd_start = . ;
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__initrd_start = . ;
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*(.initrd)
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*(.initrd)
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__initrd_end = . ;
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__initrd_end = . ;
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___data_rom_start = . ;
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___data_rom_start = . ;
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} > flash
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} > flash
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.eflash :
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.eflash :
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{
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{
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__flashend = . ;
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__flashend = . ;
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} > eflash
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} > eflash
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.data :
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.data :
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AT ( ADDR (.initrd) + SIZEOF (.initrd))
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AT ( ADDR (.initrd) + SIZEOF (.initrd))
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{
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{
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__ramstart = . ;
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__ramstart = . ;
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__sdata = . ;
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__sdata = . ;
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___data_start = . ;
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___data_start = . ;
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*(.data)
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*(.data)
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__edata = . ;
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__edata = . ;
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__end_data = . ;
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__end_data = . ;
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__data_end = . ;
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__data_end = . ;
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edata = ALIGN( 0x10 ) ;
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edata = ALIGN( 0x10 ) ;
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} > ram
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} > ram
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.bss :
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.bss :
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{
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{
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__sbss = ALIGN( 0x10 ) ;
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__sbss = ALIGN( 0x10 ) ;
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___bss_start = ALIGN( 0x10 ) ;
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___bss_start = ALIGN( 0x10 ) ;
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*(.bss)
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*(.bss)
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*(COMMON)
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*(COMMON)
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__ebss = . ;
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__ebss = . ;
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___bss_end = . ;
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___bss_end = . ;
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end = ALIGN( 0x10 ) ;
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end = ALIGN( 0x10 ) ;
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__end = ALIGN( 0x10 ) ;
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__end = ALIGN( 0x10 ) ;
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} > ram
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} > ram
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.ramvec :
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.ramvec :
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AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))
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AT ( ADDR (.initrd) + SIZEOF (.initrd) + SIZEOF (.data))
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{
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{
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__ramvec_start = . ;
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__ramvec_start = . ;
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*(.ramvec)
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*(.ramvec)
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__ramvec_end = . ;
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__ramvec_end = . ;
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} > ramvec
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} > ramvec
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.eram :
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.eram :
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{
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{
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__ramend = . ;
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__ramend = . ;
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} > eram
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} > eram
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}
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}
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