/*
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/*
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* linux/include/asm-arm/arch-trio/hardware.h
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* linux/include/asm-arm/arch-trio/hardware.h
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*
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 1996 Russell King.
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*
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*
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* This file contains the hardware definitions of the APLIO TRIO series machines.
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* This file contains the hardware definitions of the APLIO TRIO series machines.
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*/
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*/
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#ifndef __ASM_ARCH_HARDWARE_H
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#ifndef __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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#define __ASM_ARCH_HARDWARE_H
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/*
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/*
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* What hardware must be present
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* What hardware must be present
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*/
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*/
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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typedef unsigned long u_32;
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typedef unsigned long u_32;
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/* ARM asynchronous clock */
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/* ARM asynchronous clock */
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#define ARM_CLK ((u_32)(24000000))
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#define ARM_CLK ((u_32)(24000000))
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/* ARM synchronous with OAK clock */
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/* ARM synchronous with OAK clock */
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#define A_O_CLK ((u_32)(20000000))
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#define A_O_CLK ((u_32)(20000000))
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#else
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#else
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#define ARM_CLK 24000000
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#define ARM_CLK 24000000
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#define A_O_CLK 20000000
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#define A_O_CLK 20000000
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#endif
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#endif
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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/*
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/*
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* RAM definitions
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* RAM definitions
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*/
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*/
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#define MAPTOPHYS(a) ((unsigned long)a)
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#define MAPTOPHYS(a) ((unsigned long)a)
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#define KERNTOPHYS(a) ((unsigned long)(&a))
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#define KERNTOPHYS(a) ((unsigned long)(&a))
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#define GET_MEMORY_END(p) ((p->u1.s.page_size) * (p->u1.s.nr_pages))
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#define GET_MEMORY_END(p) ((p->u1.s.page_size) * (p->u1.s.nr_pages))
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#define PARAMS_BASE 0x1000
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#define PARAMS_BASE 0x1000
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//#define KERNEL_BASE (PAGE_OFFSET + 0x80000)
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//#define KERNEL_BASE (PAGE_OFFSET + 0x80000)
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#endif
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#endif
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#define IO_BASE 0
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#define IO_BASE 0
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#define PERIPH_BASE 0xff000000
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#define PERIPH_BASE 0xff000000
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#define OAKA_PRAM 0xfd000000
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#define OAKA_PRAM 0xfd000000
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#define OAKB_PRAM 0xfe000000
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#define OAKB_PRAM 0xfe000000
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#define SRAM_BASE 0xfc000000
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#define SRAM_BASE 0xfc000000
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#define SRAM_SIZE 0x1000
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#define SRAM_SIZE 0x1000
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#define DPMBA_BASE 0xfa000000
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#define DPMBA_BASE 0xfa000000
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#define DPMBB_BASE 0xfb000000
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#define DPMBB_BASE 0xfb000000
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#define DPMB_SIZE 0x800
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#define DPMB_SIZE 0x800
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#define BOOTROM_BASE 0xfb000000
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#define BOOTROM_BASE 0xfb000000
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#define BOOTROM_SIZE 0x400
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#define BOOTROM_SIZE 0x400
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/*
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/*
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Peripherials
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Peripherials
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*/
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*/
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#define SIAP_BASE (PERIPH_BASE+0)
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#define SIAP_BASE (PERIPH_BASE+0)
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#define SMC_BASE (PERIPH_BASE+0x4000)
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#define SMC_BASE (PERIPH_BASE+0x4000)
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#define DMC_BASE (PERIPH_BASE+0x8000)
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#define DMC_BASE (PERIPH_BASE+0x8000)
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#define PIOA_BASE (PERIPH_BASE+0xc000)
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#define PIOA_BASE (PERIPH_BASE+0xc000)
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#define PIOB_BASE (PERIPH_BASE+0x10000)
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#define PIOB_BASE (PERIPH_BASE+0x10000)
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#define KB_BASE (PERIPH_BASE+0x10000)
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#define KB_BASE (PERIPH_BASE+0x10000)
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#define TMC_BASE (PERIPH_BASE+0x14000)
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#define TMC_BASE (PERIPH_BASE+0x14000)
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#define USARTA_BASE (PERIPH_BASE+0x18000)
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#define USARTA_BASE (PERIPH_BASE+0x18000)
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#define USARTB_BASE (PERIPH_BASE+0x1c000)
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#define USARTB_BASE (PERIPH_BASE+0x1c000)
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#define SPI_BASE (PERIPH_BASE+0x20000)
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#define SPI_BASE (PERIPH_BASE+0x20000)
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#define WDG_BASE (PERIPH_BASE+0x28000)
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#define WDG_BASE (PERIPH_BASE+0x28000)
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#define AIC_BASE (PERIPH_BASE+0x30000)
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#define AIC_BASE (PERIPH_BASE+0x30000)
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/*
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/*
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SIAP registers
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SIAP registers
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*/
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*/
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#define SIAP_MD (SIAP_BASE)
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#define SIAP_MD (SIAP_BASE)
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#define SIAP_ID (SIAP_BASE+4)
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#define SIAP_ID (SIAP_BASE+4)
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#define SIAP_RST (SIAP_BASE+8)
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#define SIAP_RST (SIAP_BASE+8)
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/* SIAP mode register */
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/* SIAP mode register */
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#define SIAP_SW2 (1<<11)
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#define SIAP_SW2 (1<<11)
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#define SIAP_SW1 (1<<10)
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#define SIAP_SW1 (1<<10)
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#define SIAP_LPCS(x)(x<<8 & 0x300)
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#define SIAP_LPCS(x)(x<<8 & 0x300)
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#define SIAP_LP (1<<6)
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#define SIAP_LP (1<<6)
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#define SIAP_CS (1<<5)
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#define SIAP_CS (1<<5)
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#define SIAP_IB (1<<4)
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#define SIAP_IB (1<<4)
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#define SIAP_IA (1<<3)
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#define SIAP_IA (1<<3)
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#define SIAP_RB (1<<2)
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#define SIAP_RB (1<<2)
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#define SIAP_RA (1<<1)
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#define SIAP_RA (1<<1)
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#define SIAP_RM (1)
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#define SIAP_RM (1)
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/* SIAP ID register */
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/* SIAP ID register */
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#define SIAP_PKG (1<<31)
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#define SIAP_PKG (1<<31)
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#define SIAP_VERS (1)
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#define SIAP_VERS (1)
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/* SIAP reset register */
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/* SIAP reset register */
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#define SIAP_RESET (7)
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#define SIAP_RESET (7)
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/*
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/*
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DRAM Memory controller registers
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DRAM Memory controller registers
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*/
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*/
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#define DMR0 (DMC_BASE + 0)
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#define DMR0 (DMC_BASE + 0)
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#define DMR1 (DMC_BASE + 4)
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#define DMR1 (DMC_BASE + 4)
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#define DMC_CR (DMC_BASE + 8)
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#define DMC_CR (DMC_BASE + 8)
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/* DMRx registers */
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/* DMRx registers */
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#define DMR_EMR 1
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#define DMR_EMR 1
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#define DMR_PS(x) (x<<1 & 6)
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#define DMR_PS(x) (x<<1 & 6)
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#define DMR_SZ(x) (x<<3 & 0x18)
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#define DMR_SZ(x) (x<<3 & 0x18)
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/* DMR memory control register */
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/* DMR memory control register */
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#define DMR_ROR (1<<2)
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#define DMR_ROR (1<<2)
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#define DMR_BBR (1<<1)
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#define DMR_BBR (1<<1)
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#define DMR_DBW 1
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#define DMR_DBW 1
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/*
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/*
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Static Memory controller registers
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Static Memory controller registers
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*/
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*/
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#define SMC_CSR0 (SMC_BASE + 0)
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#define SMC_CSR0 (SMC_BASE + 0)
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#define SMC_CSR1 (SMC_BASE + 4)
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#define SMC_CSR1 (SMC_BASE + 4)
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#define SMC_CSR2 (SMC_BASE + 8)
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#define SMC_CSR2 (SMC_BASE + 8)
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#define SMC_CSR3 (SMC_BASE + 0xc)
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#define SMC_CSR3 (SMC_BASE + 0xc)
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#define SMC_MCR (SMC_BASE + 0x24)
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#define SMC_MCR (SMC_BASE + 0x24)
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/* SMC chip select registers */
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/* SMC chip select registers */
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#define SMC_CSEN (1<<13)
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#define SMC_CSEN (1<<13)
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#define SMC_BAT (1<<12)
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#define SMC_BAT (1<<12)
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#define SMC_TDF(x) (x<<9 & 0xe000)
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#define SMC_TDF(x) (x<<9 & 0xe000)
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#define SMC_PGS(x) (x<<7 & 0x1800)
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#define SMC_PGS(x) (x<<7 & 0x1800)
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#define SMC_WSE (1<<5)
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#define SMC_WSE (1<<5)
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#define SMC_NWS(x) (x<<2 & 0x1c)
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#define SMC_NWS(x) (x<<2 & 0x1c)
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#define SMC_DBW(x) (x & 3)
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#define SMC_DBW(x) (x & 3)
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/* SMC memory control register */
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/* SMC memory control register */
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#define SMC_DRP (1<<4)
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#define SMC_DRP (1<<4)
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/*
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/*
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Dual Port Memory A
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Dual Port Memory A
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*/
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*/
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#define DPMBA_S0 (DPMBA_BASE + 0x200)
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#define DPMBA_S0 (DPMBA_BASE + 0x200)
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#define DPMBA_S1 (DPMBA_BASE + 0x204)
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#define DPMBA_S1 (DPMBA_BASE + 0x204)
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#define DPMBA_S2 (DPMBA_BASE + 0x208)
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#define DPMBA_S2 (DPMBA_BASE + 0x208)
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#define DPMBA_S3 (DPMBA_BASE + 0x20c)
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#define DPMBA_S3 (DPMBA_BASE + 0x20c)
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#define DPMBA_S4 (DPMBA_BASE + 0x210)
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#define DPMBA_S4 (DPMBA_BASE + 0x210)
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#define DPMBA_S5 (DPMBA_BASE + 0x214)
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#define DPMBA_S5 (DPMBA_BASE + 0x214)
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#define DPMBA_S6 (DPMBA_BASE + 0x218)
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#define DPMBA_S6 (DPMBA_BASE + 0x218)
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#define DPMBA_S7 (DPMBA_BASE + 0x21c)
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#define DPMBA_S7 (DPMBA_BASE + 0x21c)
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#define DPMBA_CC (DPMBA_BASE + 0x220)
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#define DPMBA_CC (DPMBA_BASE + 0x220)
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/*
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/*
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Dual Port Memory B
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Dual Port Memory B
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*/
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*/
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#define DPMBB_S0 (DPMBB_BASE + 0x200)
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#define DPMBB_S0 (DPMBB_BASE + 0x200)
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#define DPMBB_S1 (DPMBB_BASE + 0x204)
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#define DPMBB_S1 (DPMBB_BASE + 0x204)
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#define DPMBB_S2 (DPMBB_BASE + 0x208)
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#define DPMBB_S2 (DPMBB_BASE + 0x208)
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#define DPMBB_S3 (DPMBB_BASE + 0x20c)
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#define DPMBB_S3 (DPMBB_BASE + 0x20c)
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#define DPMBB_S4 (DPMBB_BASE + 0x210)
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#define DPMBB_S4 (DPMBB_BASE + 0x210)
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#define DPMBB_S5 (DPMBB_BASE + 0x214)
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#define DPMBB_S5 (DPMBB_BASE + 0x214)
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#define DPMBB_S6 (DPMBB_BASE + 0x218)
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#define DPMBB_S6 (DPMBB_BASE + 0x218)
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#define DPMBB_S7 (DPMBB_BASE + 0x21c)
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#define DPMBB_S7 (DPMBB_BASE + 0x21c)
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#define DPMBB_CC (DPMBB_BASE + 0x220)
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#define DPMBB_CC (DPMBB_BASE + 0x220)
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/*
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/*
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Timer registers
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Timer registers
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*/
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*/
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#define TC0_BASE (TMC_BASE + 0)
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#define TC0_BASE (TMC_BASE + 0)
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#define TC1_BASE (TMC_BASE + 0x40)
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#define TC1_BASE (TMC_BASE + 0x40)
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#define TC2_BASE (TMC_BASE + 0x80)
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#define TC2_BASE (TMC_BASE + 0x80)
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#define TC_OFFSET 0x14000
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#define TC_OFFSET 0x14000
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#define TC_BASE(i) (PERIPH_BASE+TC_OFFSET+(i)*0x40)
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#define TC_BASE(i) (PERIPH_BASE+TC_OFFSET+(i)*0x40)
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#define TC_BCR (TMC_BASE + 0xC0)
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#define TC_BCR (TMC_BASE + 0xC0)
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#define TC_BMR (TMC_BASE + 0xC4)
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#define TC_BMR (TMC_BASE + 0xC4)
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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struct trio_timer_channel
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struct trio_timer_channel
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{
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{
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unsigned long ccr; // channel control register (WO)
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unsigned long ccr; // channel control register (WO)
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unsigned long cmr; // channel mode register (RW)
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unsigned long cmr; // channel mode register (RW)
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unsigned long reserved[2];
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unsigned long reserved[2];
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unsigned long cv; // counter value (RW)
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unsigned long cv; // counter value (RW)
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unsigned long ra; // register A (RW)
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unsigned long ra; // register A (RW)
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unsigned long rb; // register B (RW)
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unsigned long rb; // register B (RW)
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unsigned long rc; // register C (RW)
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unsigned long rc; // register C (RW)
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unsigned long sr; // status register (RO)
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unsigned long sr; // status register (RO)
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unsigned long ier; // interrupt enable register (WO)
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unsigned long ier; // interrupt enable register (WO)
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unsigned long idr; // interrupt disable register (WO)
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unsigned long idr; // interrupt disable register (WO)
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unsigned long imr; // interrupt mask register (RO)
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unsigned long imr; // interrupt mask register (RO)
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};
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};
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struct trio_timers
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struct trio_timers
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{
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{
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struct {
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struct {
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struct trio_timer_channel ch;
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struct trio_timer_channel ch;
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unsigned char padding[0x40-sizeof(struct trio_timer_channel)];
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unsigned char padding[0x40-sizeof(struct trio_timer_channel)];
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} chans[3];
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} chans[3];
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unsigned long bcr; // block control register (WO)
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unsigned long bcr; // block control register (WO)
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unsigned long bmr; // block mode register (RW)
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unsigned long bmr; // block mode register (RW)
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};
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};
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#endif
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#endif
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/* TC control register */
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/* TC control register */
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#define TC_SYNC (1)
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#define TC_SYNC (1)
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/* TC mode register */
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/* TC mode register */
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#define TC2XC2S(x) (x & 0x3)
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#define TC2XC2S(x) (x & 0x3)
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#define TC1XC1S(x) (x<<2 & 0xc)
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#define TC1XC1S(x) (x<<2 & 0xc)
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#define TC0XC0S(x) (x<<4 & 0x30)
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#define TC0XC0S(x) (x<<4 & 0x30)
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/* TC channel control */
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/* TC channel control */
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#define TC_CLKEN (1)
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#define TC_CLKEN (1)
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#define TC_CLKDIS (1<<1)
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#define TC_CLKDIS (1<<1)
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#define TC_SWTRG (1<<2)
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#define TC_SWTRG (1<<2)
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/* TC interrupts enable/disable/mask and status registers */
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/* TC interrupts enable/disable/mask and status registers */
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#define TC_MTIOB (1<<18)
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#define TC_MTIOB (1<<18)
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#define TC_MTIOA (1<<17)
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#define TC_MTIOA (1<<17)
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#define TC_CLKSTA (1<<16)
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#define TC_CLKSTA (1<<16)
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#define TC_ETRGS (1<<7)
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#define TC_ETRGS (1<<7)
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#define TC_LDRBS (1<<6)
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#define TC_LDRBS (1<<6)
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#define TC_LDRAS (1<<5)
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#define TC_LDRAS (1<<5)
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#define TC_CPCS (1<<4)
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#define TC_CPCS (1<<4)
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#define TC_CPBS (1<<3)
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#define TC_CPBS (1<<3)
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#define TC_CPAS (1<<2)
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#define TC_CPAS (1<<2)
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#define TC_LOVRS (1<<1)
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#define TC_LOVRS (1<<1)
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#define TC_COVFS (1)
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#define TC_COVFS (1)
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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/*
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/*
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UART registers
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UART registers
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*/
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*/
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struct uart_regs{
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struct uart_regs{
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u_32 cr; // control
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u_32 cr; // control
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u_32 mr; // mode
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u_32 mr; // mode
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u_32 ier; // interrupt enable
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u_32 ier; // interrupt enable
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u_32 idr; // interrupt disable
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u_32 idr; // interrupt disable
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u_32 imr; // interrupt mask
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u_32 imr; // interrupt mask
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u_32 csr; // channel status
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u_32 csr; // channel status
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u_32 rhr; // receive holding
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u_32 rhr; // receive holding
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u_32 thr; // tramsmit holding
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u_32 thr; // tramsmit holding
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u_32 brgr; // baud rate generator
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u_32 brgr; // baud rate generator
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u_32 rtor; // rx time-out
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u_32 rtor; // rx time-out
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u_32 ttgr; // tx time-guard
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u_32 ttgr; // tx time-guard
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u_32 res1;
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u_32 res1;
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u_32 rpr; // rx pointer
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u_32 rpr; // rx pointer
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u_32 rcr; // rx counter
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u_32 rcr; // rx counter
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u_32 tpr; // tx pointer
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u_32 tpr; // tx pointer
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u_32 tcr; // tx counter
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u_32 tcr; // tx counter
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u_32 mc; // modem control
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u_32 mc; // modem control
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u_32 ms; // modem status
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u_32 ms; // modem status
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};
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};
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#endif
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#endif
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/* US control register */
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/* US control register */
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#define US_SENDA (1<<12)
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#define US_SENDA (1<<12)
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#define US_STTO (1<<11)
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#define US_STTO (1<<11)
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#define US_STPBRK (1<<10)
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#define US_STPBRK (1<<10)
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#define US_STTBRK (1<<9)
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#define US_STTBRK (1<<9)
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#define US_RSTSTA (1<<8)
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#define US_RSTSTA (1<<8)
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#define US_TXDIS (1<<7)
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#define US_TXDIS (1<<7)
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#define US_TXEN (1<<6)
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#define US_TXEN (1<<6)
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#define US_RXDIS (1<<5)
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#define US_RXDIS (1<<5)
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#define US_RXEN (1<<4)
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#define US_RXEN (1<<4)
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#define US_RSTTX (1<<3)
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#define US_RSTTX (1<<3)
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#define US_RSTRX (1<<2)
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#define US_RSTRX (1<<2)
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|
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/* US mode register */
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/* US mode register */
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#define US_CLK0 (1<<18)
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#define US_CLK0 (1<<18)
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#define US_MODE9 (1<<17)
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#define US_MODE9 (1<<17)
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#define US_CHMODE(x)(x<<14 & 0xc000)
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#define US_CHMODE(x)(x<<14 & 0xc000)
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#define US_NBSTOP(x)(x<<12 & 0x3000)
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#define US_NBSTOP(x)(x<<12 & 0x3000)
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#define US_PAR(x) (x<<9 & 0xe00)
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#define US_PAR(x) (x<<9 & 0xe00)
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#define US_SYNC (1<<8)
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#define US_SYNC (1<<8)
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#define US_CHRL(x) (x<<6 & 0xc0)
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#define US_CHRL(x) (x<<6 & 0xc0)
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#define US_USCLKS(x)(x<<4 & 0x30)
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#define US_USCLKS(x)(x<<4 & 0x30)
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|
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/* US interrupts enable/disable/mask and status register */
|
/* US interrupts enable/disable/mask and status register */
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#define US_DMSI (1<<10)
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#define US_DMSI (1<<10)
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#define US_TXEMPTY (1<<9)
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#define US_TXEMPTY (1<<9)
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#define US_TIMEOUT (1<<8)
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#define US_TIMEOUT (1<<8)
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#define US_PARE (1<<7)
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#define US_PARE (1<<7)
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#define US_FRAME (1<<6)
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#define US_FRAME (1<<6)
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#define US_OVRE (1<<5)
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#define US_OVRE (1<<5)
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#define US_ENDTX (1<<4)
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#define US_ENDTX (1<<4)
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#define US_ENDRX (1<<3)
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#define US_ENDRX (1<<3)
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#define US_RXBRK (1<<2)
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#define US_RXBRK (1<<2)
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#define US_TXRDY (1<<1)
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#define US_TXRDY (1<<1)
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#define US_RXRDY (1)
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#define US_RXRDY (1)
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|
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#define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY)
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#define US_ALL_INTS (US_DMSI|US_TXEMPTY|US_TIMEOUT|US_PARE|US_FRAME|US_OVRE|US_ENDTX|US_ENDRX|US_RXBRK|US_TXRDY|US_RXRDY)
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/* US modem control register */
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/* US modem control register */
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#define US_FCM (1<<5)
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#define US_FCM (1<<5)
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#define US_RTS (1<<1)
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#define US_RTS (1<<1)
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#define US_DTR (1)
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#define US_DTR (1)
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/* US modem status register */
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/* US modem status register */
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#define US_FCMS (1<<8)
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#define US_FCMS (1<<8)
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#define US_DCD (1<<7)
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#define US_DCD (1<<7)
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#define US_RI (1<<6)
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#define US_RI (1<<6)
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#define US_DSR (1<<5)
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#define US_DSR (1<<5)
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#define US_CTS (1<<4)
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#define US_CTS (1<<4)
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#define US_DDCD (1<<3)
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#define US_DDCD (1<<3)
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#define US_TERI (1<<2)
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#define US_TERI (1<<2)
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#define US_DDSR (1<<1)
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#define US_DDSR (1<<1)
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#define US_DCTS (1)
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#define US_DCTS (1)
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/*
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/*
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Advanced Interrupt Controller registers
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Advanced Interrupt Controller registers
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*/
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*/
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#define AIC_SMR(i) (AIC_BASE+i*4)
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#define AIC_SMR(i) (AIC_BASE+i*4)
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#define AIC_IVR (AIC_BASE+0x100)
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#define AIC_IVR (AIC_BASE+0x100)
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#define AIC_FVR (AIC_BASE+0x104)
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#define AIC_FVR (AIC_BASE+0x104)
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#define AIC_ISR (AIC_BASE+0x108)
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#define AIC_ISR (AIC_BASE+0x108)
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#define AIC_IPR (AIC_BASE+0x10C)
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#define AIC_IPR (AIC_BASE+0x10C)
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#define AIC_IMR (AIC_BASE+0x110)
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#define AIC_IMR (AIC_BASE+0x110)
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#define AIC_CISR (AIC_BASE+0x114)
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#define AIC_CISR (AIC_BASE+0x114)
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#define AIC_IECR (AIC_BASE+0x120)
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#define AIC_IECR (AIC_BASE+0x120)
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#define AIC_IDCR (AIC_BASE+0x124)
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#define AIC_IDCR (AIC_BASE+0x124)
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#define AIC_ICCR (AIC_BASE+0x128)
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#define AIC_ICCR (AIC_BASE+0x128)
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#define AIC_ISCR (AIC_BASE+0x12C)
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#define AIC_ISCR (AIC_BASE+0x12C)
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#define AIC_EOICR (AIC_BASE+0x130)
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#define AIC_EOICR (AIC_BASE+0x130)
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/* AIC enable/disable/mask/pending registers */
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/* AIC enable/disable/mask/pending registers */
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#define AIC_PIOB (1<<15)
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#define AIC_PIOB (1<<15)
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#define AIC_UB (1<<14)
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#define AIC_UB (1<<14)
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#define AIC_OAKB (1<<13)
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#define AIC_OAKB (1<<13)
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#define AIC_OAKA (1<<12)
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#define AIC_OAKA (1<<12)
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#define AIC_IRQ1 (1<<11)
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#define AIC_IRQ1 (1<<11)
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#define AIC_IRQ0 (1<<10)
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#define AIC_IRQ0 (1<<10)
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#define AIC_SPI (1<<9)
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#define AIC_SPI (1<<9)
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#define AIC_LCD (1<<8)
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#define AIC_LCD (1<<8)
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#define AIC_PIOA (1<<7)
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#define AIC_PIOA (1<<7)
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#define AIC_TC2 (1<<6)
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#define AIC_TC2 (1<<6)
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#define AIC_TC1 (1<<5)
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#define AIC_TC1 (1<<5)
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#define AIC_TC0 (1<<4)
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#define AIC_TC0 (1<<4)
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#define AIC_UA (1<<3)
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#define AIC_UA (1<<3)
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#define AIC_SWI (1<<2)
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#define AIC_SWI (1<<2)
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#define AIC_WD (1<<1)
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#define AIC_WD (1<<1)
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#define AIC_FIQ (1)
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#define AIC_FIQ (1)
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/*
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/*
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PIOA registers
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PIOA registers
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*/
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*/
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#define PIOA_PER (PIOA_BASE+0)
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#define PIOA_PER (PIOA_BASE+0)
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#define PIOA_PDR (PIOA_BASE+0x4)
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#define PIOA_PDR (PIOA_BASE+0x4)
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#define PIOA_PSR (PIOA_BASE+0x8)
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#define PIOA_PSR (PIOA_BASE+0x8)
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#define PIOA_OER (PIOA_BASE+0x10)
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#define PIOA_OER (PIOA_BASE+0x10)
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#define PIOA_ODR (PIOA_BASE+0x14)
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#define PIOA_ODR (PIOA_BASE+0x14)
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#define PIOA_OSR (PIOA_BASE+0x18)
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#define PIOA_OSR (PIOA_BASE+0x18)
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#define PIOA_IFER (PIOA_BASE+0x20)
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#define PIOA_IFER (PIOA_BASE+0x20)
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#define PIOA_IFDR (PIOA_BASE+0x24)
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#define PIOA_IFDR (PIOA_BASE+0x24)
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#define PIOA_IFSR (PIOA_BASE+0x28)
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#define PIOA_IFSR (PIOA_BASE+0x28)
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#define PIOA_SODR (PIOA_BASE+0x30)
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#define PIOA_SODR (PIOA_BASE+0x30)
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#define PIOA_CODR (PIOA_BASE+0x34)
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#define PIOA_CODR (PIOA_BASE+0x34)
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#define PIOA_ODSR (PIOA_BASE+0x38)
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#define PIOA_ODSR (PIOA_BASE+0x38)
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#define PIOA_PDSR (PIOA_BASE+0x3C)
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#define PIOA_PDSR (PIOA_BASE+0x3C)
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#define PIOA_IER (PIOA_BASE+0x40)
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#define PIOA_IER (PIOA_BASE+0x40)
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#define PIOA_IDR (PIOA_BASE+0x44)
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#define PIOA_IDR (PIOA_BASE+0x44)
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#define PIOA_IMR (PIOA_BASE+0x48)
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#define PIOA_IMR (PIOA_BASE+0x48)
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#define PIOA_ISR (PIOA_BASE+0x4C)
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#define PIOA_ISR (PIOA_BASE+0x4C)
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/* PIOA bit allocation */
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/* PIOA bit allocation */
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#define PIOA_TCLK0 (1<<8)
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#define PIOA_TCLK0 (1<<8)
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#define PIOA_TI0A0 (1<<9)
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#define PIOA_TI0A0 (1<<9)
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#define PIOA_TI0B0 (1<<10)
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#define PIOA_TI0B0 (1<<10)
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#define PIOA_SCLKA (1<<11)
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#define PIOA_SCLKA (1<<11)
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#define PIOA_NPCS1 (1<<12)
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#define PIOA_NPCS1 (1<<12)
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#define PIOA_SCLKB (1<<13)
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#define PIOA_SCLKB (1<<13)
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#define PIOA_NPCS2 (1<<14)
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#define PIOA_NPCS2 (1<<14)
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#define PIOA_NPCS3 (1<<15)
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#define PIOA_NPCS3 (1<<15)
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#define PIOA_TCLK2 (1<<16)
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#define PIOA_TCLK2 (1<<16)
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#define PIOA_TIOA2 (1<<17)
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#define PIOA_TIOA2 (1<<17)
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#define PIOA_TIOB2 (1<<18)
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#define PIOA_TIOB2 (1<<18)
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#define PIOA_ACLK (1<<19)
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#define PIOA_ACLK (1<<19)
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/*
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/*
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PIOB registers
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PIOB registers
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*/
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*/
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#define PIOB_PER (PIOB_BASE+0)
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#define PIOB_PER (PIOB_BASE+0)
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#define PIOB_PDR (PIOB_BASE+0x4)
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#define PIOB_PDR (PIOB_BASE+0x4)
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#define PIOB_PSR (PIOB_BASE+0x8)
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#define PIOB_PSR (PIOB_BASE+0x8)
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#define PIOB_OER (PIOB_BASE+0x10)
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#define PIOB_OER (PIOB_BASE+0x10)
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#define PIOB_ODR (PIOB_BASE+0x14)
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#define PIOB_ODR (PIOB_BASE+0x14)
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#define PIOB_OSR (PIOB_BASE+0x18)
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#define PIOB_OSR (PIOB_BASE+0x18)
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#define PIOB_IFER (PIOB_BASE+0x20)
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#define PIOB_IFER (PIOB_BASE+0x20)
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#define PIOB_IFDR (PIOB_BASE+0x24)
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#define PIOB_IFDR (PIOB_BASE+0x24)
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#define PIOB_IFSR (PIOB_BASE+0x28)
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#define PIOB_IFSR (PIOB_BASE+0x28)
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#define PIOB_SODR (PIOB_BASE+0x30)
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#define PIOB_SODR (PIOB_BASE+0x30)
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#define PIOB_CODR (PIOB_BASE+0x34)
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#define PIOB_CODR (PIOB_BASE+0x34)
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#define PIOB_ODSR (PIOB_BASE+0x38)
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#define PIOB_ODSR (PIOB_BASE+0x38)
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#define PIOB_PDSR (PIOB_BASE+0x3C)
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#define PIOB_PDSR (PIOB_BASE+0x3C)
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#define PIOB_IER (PIOB_BASE+0x40)
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#define PIOB_IER (PIOB_BASE+0x40)
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#define PIOB_IDR (PIOB_BASE+0x44)
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#define PIOB_IDR (PIOB_BASE+0x44)
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#define PIOB_IMR (PIOB_BASE+0x48)
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#define PIOB_IMR (PIOB_BASE+0x48)
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#define PIOB_ISR (PIOB_BASE+0x4C)
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#define PIOB_ISR (PIOB_BASE+0x4C)
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/* PIOB bit allocation */
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/* PIOB bit allocation */
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#define PIOB_TCLK1 (1)
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#define PIOB_TCLK1 (1)
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#define PIOB_TIOA1 (1<<1)
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#define PIOB_TIOA1 (1<<1)
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#define PIOB_TIOB1 (1<<2)
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#define PIOB_TIOB1 (1<<2)
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#define PIOB_NCTSA (1<<3)
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#define PIOB_NCTSA (1<<3)
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#define PIOB_NRIA (1<<5)
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#define PIOB_NRIA (1<<5)
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#define PIOB_NWDOVF (1<<6)
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#define PIOB_NWDOVF (1<<6)
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#define PIOB_NCE1 (1<<7)
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#define PIOB_NCE1 (1<<7)
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#define PIOB_NCE2 (1<<8)
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#define PIOB_NCE2 (1<<8)
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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struct pio_regs{
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struct pio_regs{
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u_32 per;
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u_32 per;
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u_32 pdr;
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u_32 pdr;
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u_32 psr;
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u_32 psr;
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u_32 res1;
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u_32 res1;
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u_32 oer;
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u_32 oer;
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u_32 odr;
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u_32 odr;
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u_32 osr;
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u_32 osr;
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u_32 res2;
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u_32 res2;
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u_32 ifer;
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u_32 ifer;
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u_32 ifdr;
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u_32 ifdr;
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u_32 ifsr;
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u_32 ifsr;
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u_32 res3;
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u_32 res3;
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u_32 sodr;
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u_32 sodr;
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u_32 codr;
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u_32 codr;
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u_32 odsr;
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u_32 odsr;
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u_32 pdsr;
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u_32 pdsr;
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u_32 ier;
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u_32 ier;
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u_32 idr;
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u_32 idr;
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u_32 imr;
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u_32 imr;
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u_32 isr;
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u_32 isr;
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};
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};
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#endif
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#endif
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/*
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/*
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Serial Peripheral Interface
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Serial Peripheral Interface
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*/
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*/
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#define SP_CR (SPI_BASE + 0)
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#define SP_CR (SPI_BASE + 0)
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#define SP_MR (SPI_BASE + 4)
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#define SP_MR (SPI_BASE + 4)
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#define SP_RDR (SPI_BASE + 8)
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#define SP_RDR (SPI_BASE + 8)
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#define SP_TDR (SPI_BASE + 0xC)
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#define SP_TDR (SPI_BASE + 0xC)
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#define SP_SR (SPI_BASE + 0x10)
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#define SP_SR (SPI_BASE + 0x10)
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#define SP_IER (SPI_BASE + 0x14)
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#define SP_IER (SPI_BASE + 0x14)
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#define SP_IDR (SPI_BASE + 0x18)
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#define SP_IDR (SPI_BASE + 0x18)
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#define SP_IMR (SPI_BASE + 0x1C)
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#define SP_IMR (SPI_BASE + 0x1C)
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#define SP_CSR0 (SPI_BASE + 0x30)
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#define SP_CSR0 (SPI_BASE + 0x30)
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#define SP_CSR1 (SPI_BASE + 0x34)
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#define SP_CSR1 (SPI_BASE + 0x34)
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#define SP_CSR2 (SPI_BASE + 0x38)
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#define SP_CSR2 (SPI_BASE + 0x38)
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#define SP_CSR3 (SPI_BASE + 0x3C)
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#define SP_CSR3 (SPI_BASE + 0x3C)
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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struct spi_regs{
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struct spi_regs{
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u_32 cr;
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u_32 cr;
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u_32 mr;
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u_32 mr;
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u_32 rdr;
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u_32 rdr;
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u_32 tdr;
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u_32 tdr;
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u_32 sr;
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u_32 sr;
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u_32 ier;
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u_32 ier;
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u_32 idr;
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u_32 idr;
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u_32 imr;
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u_32 imr;
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u_32 res1;
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u_32 res1;
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u_32 res2;
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u_32 res2;
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u_32 res3;
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u_32 res3;
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u_32 res4;
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u_32 res4;
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u_32 csr0;
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u_32 csr0;
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u_32 csr1;
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u_32 csr1;
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u_32 csr2;
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u_32 csr2;
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u_32 csr3;
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u_32 csr3;
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};
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};
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#endif
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#endif
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/* SPI control register */
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/* SPI control register */
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#define SPI_SWRST (1<<7)
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#define SPI_SWRST (1<<7)
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#define SPI_SPIDIS (1<<1)
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#define SPI_SPIDIS (1<<1)
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#define SPI_SPIEN (1)
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#define SPI_SPIEN (1)
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/* SPI mode register */
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/* SPI mode register */
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#define SPI_MSTR (1)
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#define SPI_MSTR (1)
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#define SPI_PS (1<<1)
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#define SPI_PS (1<<1)
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#define SPI_PCSDEC (1<<2)
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#define SPI_PCSDEC (1<<2)
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#define SPI_MCSK32 (1<<3)
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#define SPI_MCSK32 (1<<3)
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#define SPI_LLB (1<<7)
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#define SPI_LLB (1<<7)
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#define SPI_PCS(x) (x<<16 & 0xF0000)
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#define SPI_PCS(x) (x<<16 & 0xF0000)
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#define SPI_DLYBCS(x) (x<<24 & 0xFF000000)
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#define SPI_DLYBCS(x) (x<<24 & 0xFF000000)
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/* SPI Receive/Transmit Data Register */
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/* SPI Receive/Transmit Data Register */
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#define SPI_PCS_MASK (0xF0000)
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#define SPI_PCS_MASK (0xF0000)
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/* SPI Interrupt enable/disable and Status registers */
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/* SPI Interrupt enable/disable and Status registers */
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#define SPI_OVRES (1<<3)
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#define SPI_OVRES (1<<3)
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#define SPI_MODF (1<<2)
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#define SPI_MODF (1<<2)
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#define SPI_TDRE (1<<1)
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#define SPI_TDRE (1<<1)
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#define SPI_RDRF (1)
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#define SPI_RDRF (1)
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/* SPI chip selects registers */
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/* SPI chip selects registers */
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#define SPI_CPOL (1)
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#define SPI_CPOL (1)
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#define SPI_NCPHA (1<<1)
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#define SPI_NCPHA (1<<1)
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#define SPI_BITS_MASK 0xF0
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#define SPI_BITS_MASK 0xF0
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#define SPI_SCBR_MASK 0xF00
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#define SPI_SCBR_MASK 0xF00
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#define SPI_DLYBS_MASK 0xF0000
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#define SPI_DLYBS_MASK 0xF0000
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#define SPI_DLYBCT_MASK 0xF000000
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#define SPI_DLYBCT_MASK 0xF000000
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#define SPI_BITS(x) (x<<4 & SPI_BITS_MASK)
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#define SPI_BITS(x) (x<<4 & SPI_BITS_MASK)
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#define SPI_SCBR(x) (x<<8 & SPI_SCBR_MASK)
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#define SPI_SCBR(x) (x<<8 & SPI_SCBR_MASK)
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#define SPI_DLYBS(x) (x<<16 & SPI_DLYBS_MASK)
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#define SPI_DLYBS(x) (x<<16 & SPI_DLYBS_MASK)
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#define SPI_DLYBCT(x) (x<<24 & SPI_DLYBCT_MASK)
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#define SPI_DLYBCT(x) (x<<24 & SPI_DLYBCT_MASK)
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/*
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/*
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Watchdog registers
|
Watchdog registers
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*/
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*/
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#define WDG_OMR (WD_BASE + 0)
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#define WDG_OMR (WD_BASE + 0)
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#define WDG_CMR (WD_BASE + 4)
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#define WDG_CMR (WD_BASE + 4)
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#define WDG_CR (WD_BASE + 8)
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#define WDG_CR (WD_BASE + 8)
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#define WDG_SR (WD_BASE + 0xC)
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#define WDG_SR (WD_BASE + 0xC)
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/* Overflow Mode Register */
|
/* Overflow Mode Register */
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#define WDG_OKEY_MASK 0xFFF0
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#define WDG_OKEY_MASK 0xFFF0
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#define WDG_OKEY(x) (x<<4 & WDG_OKEY_MASK)
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#define WDG_OKEY(x) (x<<4 & WDG_OKEY_MASK)
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#define WDG_EXTEN (1<<3)
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#define WDG_EXTEN (1<<3)
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#define WDG_IRQEN (1<<2)
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#define WDG_IRQEN (1<<2)
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#define WDG_RSTEN (1<<1)
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#define WDG_RSTEN (1<<1)
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#define WDG_WDEN (1)
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#define WDG_WDEN (1)
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/* Clock Mode Register */
|
/* Clock Mode Register */
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#define WDG_CKEY_MASK 0xFF80
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#define WDG_CKEY_MASK 0xFF80
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#define WDG_HPCV_MASK 0x3C
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#define WDG_HPCV_MASK 0x3C
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#define WDG_WDCLKS_MASK 0x3
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#define WDG_WDCLKS_MASK 0x3
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#define WDG_CKEY(x) (x<<7 & WDG_CKEY_MASK)
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#define WDG_CKEY(x) (x<<7 & WDG_CKEY_MASK)
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#define WDG_HPCV(x) (x<<2 & WDG_HPCV_MASK)
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#define WDG_HPCV(x) (x<<2 & WDG_HPCV_MASK)
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#define WDG_WDCLKS(x) (x & WDG_WDCLKS_MASK)
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#define WDG_WDCLKS(x) (x & WDG_WDCLKS_MASK)
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/* Control Register */
|
/* Control Register */
|
#define WDG_RESTART_KEY 0xC071
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#define WDG_RESTART_KEY 0xC071
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/* Status Register */
|
/* Status Register */
|
#define WDG_WDOVF (1)
|
#define WDG_WDOVF (1)
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#endif
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#endif
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