/*
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/*
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* linux/include/asm-arm/hardware.h
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* linux/include/asm-arm/hardware.h
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*
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*
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* Copyright (C) 1996 Russell King
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* Copyright (C) 1996 Russell King
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*
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*
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* Common hardware definitions
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* Common hardware definitions
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*/
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*/
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#ifndef __ASM_HARDWARE_H
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#ifndef __ASM_HARDWARE_H
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#define __ASM_HARDWARE_H
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#define __ASM_HARDWARE_H
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|
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#include <asm/arch/hardware.h>
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#include <asm/arch/hardware.h>
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/*
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/*
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* Use these macros to read/write the IOC. All it does is perform the actual
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* Use these macros to read/write the IOC. All it does is perform the actual
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* read/write.
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* read/write.
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*/
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*/
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#ifdef HAS_IOC
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#ifdef HAS_IOC
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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#define __IOC(offset) (IO_IOC_BASE + (offset >> 2))
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#define __IOC(offset) (IO_IOC_BASE + (offset >> 2))
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#else
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#else
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#define __IOC(offset) offset
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#define __IOC(offset) offset
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#endif
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#endif
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#define IOC_CONTROL __IOC(0x00)
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#define IOC_CONTROL __IOC(0x00)
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#define IOC_KARTTX __IOC(0x04)
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#define IOC_KARTTX __IOC(0x04)
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#define IOC_KARTRX __IOC(0x04)
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#define IOC_KARTRX __IOC(0x04)
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#define IOC_IRQSTATA __IOC(0x10)
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#define IOC_IRQSTATA __IOC(0x10)
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#define IOC_IRQREQA __IOC(0x14)
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#define IOC_IRQREQA __IOC(0x14)
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#define IOC_IRQCLRA __IOC(0x14)
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#define IOC_IRQCLRA __IOC(0x14)
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#define IOC_IRQMASKA __IOC(0x18)
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#define IOC_IRQMASKA __IOC(0x18)
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#define IOC_IRQSTATB __IOC(0x20)
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#define IOC_IRQSTATB __IOC(0x20)
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#define IOC_IRQREQB __IOC(0x24)
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#define IOC_IRQREQB __IOC(0x24)
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#define IOC_IRQMASKB __IOC(0x28)
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#define IOC_IRQMASKB __IOC(0x28)
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#define IOC_FIQSTAT __IOC(0x30)
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#define IOC_FIQSTAT __IOC(0x30)
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#define IOC_FIQREQ __IOC(0x34)
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#define IOC_FIQREQ __IOC(0x34)
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#define IOC_FIQMASK __IOC(0x38)
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#define IOC_FIQMASK __IOC(0x38)
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#define IOC_T0CNTL __IOC(0x40)
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#define IOC_T0CNTL __IOC(0x40)
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#define IOC_T0LTCHL __IOC(0x40)
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#define IOC_T0LTCHL __IOC(0x40)
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#define IOC_T0CNTH __IOC(0x44)
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#define IOC_T0CNTH __IOC(0x44)
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#define IOC_T0LTCHH __IOC(0x44)
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#define IOC_T0LTCHH __IOC(0x44)
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#define IOC_T0GO __IOC(0x48)
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#define IOC_T0GO __IOC(0x48)
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#define IOC_T0LATCH __IOC(0x4c)
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#define IOC_T0LATCH __IOC(0x4c)
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#define IOC_T1CNTL __IOC(0x50)
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#define IOC_T1CNTL __IOC(0x50)
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#define IOC_T1LTCHL __IOC(0x50)
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#define IOC_T1LTCHL __IOC(0x50)
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#define IOC_T1CNTH __IOC(0x54)
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#define IOC_T1CNTH __IOC(0x54)
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#define IOC_T1LTCHH __IOC(0x54)
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#define IOC_T1LTCHH __IOC(0x54)
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#define IOC_T1GO __IOC(0x58)
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#define IOC_T1GO __IOC(0x58)
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#define IOC_T1LATCH __IOC(0x5c)
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#define IOC_T1LATCH __IOC(0x5c)
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#define IOC_T2CNTL __IOC(0x60)
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#define IOC_T2CNTL __IOC(0x60)
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#define IOC_T2LTCHL __IOC(0x60)
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#define IOC_T2LTCHL __IOC(0x60)
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#define IOC_T2CNTH __IOC(0x64)
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#define IOC_T2CNTH __IOC(0x64)
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#define IOC_T2LTCHH __IOC(0x64)
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#define IOC_T2LTCHH __IOC(0x64)
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#define IOC_T2GO __IOC(0x68)
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#define IOC_T2GO __IOC(0x68)
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#define IOC_T2LATCH __IOC(0x6c)
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#define IOC_T2LATCH __IOC(0x6c)
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#define IOC_T3CNTL __IOC(0x70)
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#define IOC_T3CNTL __IOC(0x70)
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#define IOC_T3LTCHL __IOC(0x70)
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#define IOC_T3LTCHL __IOC(0x70)
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#define IOC_T3CNTH __IOC(0x74)
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#define IOC_T3CNTH __IOC(0x74)
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#define IOC_T3LTCHH __IOC(0x74)
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#define IOC_T3LTCHH __IOC(0x74)
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#define IOC_T3GO __IOC(0x78)
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#define IOC_T3GO __IOC(0x78)
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#define IOC_T3LATCH __IOC(0x7c)
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#define IOC_T3LATCH __IOC(0x7c)
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#endif
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#endif
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#ifdef HAS_MEMC
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#ifdef HAS_MEMC
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#define VDMA_ALIGNMENT PAGE_SIZE
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#define VDMA_ALIGNMENT PAGE_SIZE
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#define VDMA_XFERSIZE 16
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#define VDMA_XFERSIZE 16
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#define VDMA_INIT 0
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#define VDMA_INIT 0
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#define VDMA_START 1
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#define VDMA_START 1
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#define VDMA_END 2
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#define VDMA_END 2
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#define video_set_dma(start,end,offset) \
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#define video_set_dma(start,end,offset) \
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do { \
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do { \
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memc_write (VDMA_START, (start >> 2)); \
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memc_write (VDMA_START, (start >> 2)); \
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memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
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memc_write (VDMA_END, (end - VDMA_XFERSIZE) >> 2); \
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memc_write (VDMA_INIT, (offset >> 2)); \
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memc_write (VDMA_INIT, (offset >> 2)); \
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} while (0)
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} while (0)
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#endif
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#endif
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#ifdef HAS_IOMD
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#ifdef HAS_IOMD
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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#define __IOMD(offset) (IO_IOMD_BASE + (offset >> 2))
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#define __IOMD(offset) (IO_IOMD_BASE + (offset >> 2))
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#else
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#else
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#define __IOMD(offset) offset
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#define __IOMD(offset) offset
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#endif
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#endif
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#define IOMD_CONTROL __IOMD(0x000)
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#define IOMD_CONTROL __IOMD(0x000)
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#define IOMD_KARTTX __IOMD(0x004)
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#define IOMD_KARTTX __IOMD(0x004)
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#define IOMD_KARTRX __IOMD(0x004)
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#define IOMD_KARTRX __IOMD(0x004)
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#define IOMD_KCTRL __IOMD(0x008)
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#define IOMD_KCTRL __IOMD(0x008)
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#define IOMD_IRQSTATA __IOMD(0x010)
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#define IOMD_IRQSTATA __IOMD(0x010)
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#define IOMD_IRQREQA __IOMD(0x014)
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#define IOMD_IRQREQA __IOMD(0x014)
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#define IOMD_IRQCLRA __IOMD(0x014)
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#define IOMD_IRQCLRA __IOMD(0x014)
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#define IOMD_IRQMASKA __IOMD(0x018)
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#define IOMD_IRQMASKA __IOMD(0x018)
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#define IOMD_IRQSTATB __IOMD(0x020)
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#define IOMD_IRQSTATB __IOMD(0x020)
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#define IOMD_IRQREQB __IOMD(0x024)
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#define IOMD_IRQREQB __IOMD(0x024)
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#define IOMD_IRQMASKB __IOMD(0x028)
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#define IOMD_IRQMASKB __IOMD(0x028)
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#define IOMD_FIQSTAT __IOMD(0x030)
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#define IOMD_FIQSTAT __IOMD(0x030)
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#define IOMD_FIQREQ __IOMD(0x034)
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#define IOMD_FIQREQ __IOMD(0x034)
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#define IOMD_FIQMASK __IOMD(0x038)
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#define IOMD_FIQMASK __IOMD(0x038)
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#define IOMD_T0CNTL __IOMD(0x040)
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#define IOMD_T0CNTL __IOMD(0x040)
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#define IOMD_T0LTCHL __IOMD(0x040)
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#define IOMD_T0LTCHL __IOMD(0x040)
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#define IOMD_T0CNTH __IOMD(0x044)
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#define IOMD_T0CNTH __IOMD(0x044)
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#define IOMD_T0LTCHH __IOMD(0x044)
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#define IOMD_T0LTCHH __IOMD(0x044)
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#define IOMD_T0GO __IOMD(0x048)
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#define IOMD_T0GO __IOMD(0x048)
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#define IOMD_T0LATCH __IOMD(0x04c)
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#define IOMD_T0LATCH __IOMD(0x04c)
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#define IOMD_T1CNTL __IOMD(0x050)
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#define IOMD_T1CNTL __IOMD(0x050)
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#define IOMD_T1LTCHL __IOMD(0x050)
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#define IOMD_T1LTCHL __IOMD(0x050)
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#define IOMD_T1CNTH __IOMD(0x054)
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#define IOMD_T1CNTH __IOMD(0x054)
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#define IOMD_T1LTCHH __IOMD(0x054)
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#define IOMD_T1LTCHH __IOMD(0x054)
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#define IOMD_T1GO __IOMD(0x058)
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#define IOMD_T1GO __IOMD(0x058)
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#define IOMD_T1LATCH __IOMD(0x05c)
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#define IOMD_T1LATCH __IOMD(0x05c)
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#define IOMD_ROMCR0 __IOMD(0x080)
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#define IOMD_ROMCR0 __IOMD(0x080)
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#define IOMD_ROMCR1 __IOMD(0x084)
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#define IOMD_ROMCR1 __IOMD(0x084)
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#define IOMD_DRAMCR __IOMD(0x088)
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#define IOMD_DRAMCR __IOMD(0x088)
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#define IOMD_VREFCR __IOMD(0x08C)
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#define IOMD_VREFCR __IOMD(0x08C)
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#define IOMD_FSIZE __IOMD(0x090)
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#define IOMD_FSIZE __IOMD(0x090)
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#define IOMD_ID0 __IOMD(0x094)
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#define IOMD_ID0 __IOMD(0x094)
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#define IOMD_ID1 __IOMD(0x098)
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#define IOMD_ID1 __IOMD(0x098)
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#define IOMD_VERSION __IOMD(0x09C)
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#define IOMD_VERSION __IOMD(0x09C)
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#define IOMD_MOUSEX __IOMD(0x0A0)
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#define IOMD_MOUSEX __IOMD(0x0A0)
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#define IOMD_MOUSEY __IOMD(0x0A4)
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#define IOMD_MOUSEY __IOMD(0x0A4)
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#define IOMD_DMATCR __IOMD(0x0C0)
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#define IOMD_DMATCR __IOMD(0x0C0)
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#define IOMD_IOTCR __IOMD(0x0C4)
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#define IOMD_IOTCR __IOMD(0x0C4)
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#define IOMD_ECTCR __IOMD(0x0C8)
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#define IOMD_ECTCR __IOMD(0x0C8)
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#define IOMD_DMAEXT __IOMD(0x0CC)
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#define IOMD_DMAEXT __IOMD(0x0CC)
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#define DMA_EXT_IO0 1
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#define DMA_EXT_IO0 1
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#define DMA_EXT_IO1 2
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#define DMA_EXT_IO1 2
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#define DMA_EXT_IO2 4
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#define DMA_EXT_IO2 4
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#define DMA_EXT_IO3 8
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#define DMA_EXT_IO3 8
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#define IOMD_IO0CURA __IOMD(0x100)
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#define IOMD_IO0CURA __IOMD(0x100)
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#define IOMD_IO0ENDA __IOMD(0x104)
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#define IOMD_IO0ENDA __IOMD(0x104)
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#define IOMD_IO0CURB __IOMD(0x108)
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#define IOMD_IO0CURB __IOMD(0x108)
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#define IOMD_IO0ENDB __IOMD(0x10C)
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#define IOMD_IO0ENDB __IOMD(0x10C)
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#define IOMD_IO0CR __IOMD(0x110)
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#define IOMD_IO0CR __IOMD(0x110)
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#define IOMD_IO0ST __IOMD(0x114)
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#define IOMD_IO0ST __IOMD(0x114)
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#define IOMD_IO1CURA __IOMD(0x120)
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#define IOMD_IO1CURA __IOMD(0x120)
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#define IOMD_IO1ENDA __IOMD(0x124)
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#define IOMD_IO1ENDA __IOMD(0x124)
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#define IOMD_IO1CURB __IOMD(0x128)
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#define IOMD_IO1CURB __IOMD(0x128)
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#define IOMD_IO1ENDB __IOMD(0x12C)
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#define IOMD_IO1ENDB __IOMD(0x12C)
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#define IOMD_IO1CR __IOMD(0x130)
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#define IOMD_IO1CR __IOMD(0x130)
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#define IOMD_IO1ST __IOMD(0x134)
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#define IOMD_IO1ST __IOMD(0x134)
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#define IOMD_IO2CURA __IOMD(0x140)
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#define IOMD_IO2CURA __IOMD(0x140)
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#define IOMD_IO2ENDA __IOMD(0x144)
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#define IOMD_IO2ENDA __IOMD(0x144)
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#define IOMD_IO2CURB __IOMD(0x148)
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#define IOMD_IO2CURB __IOMD(0x148)
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#define IOMD_IO2ENDB __IOMD(0x14C)
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#define IOMD_IO2ENDB __IOMD(0x14C)
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#define IOMD_IO2CR __IOMD(0x150)
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#define IOMD_IO2CR __IOMD(0x150)
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#define IOMD_IO2ST __IOMD(0x154)
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#define IOMD_IO2ST __IOMD(0x154)
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#define IOMD_IO3CURA __IOMD(0x160)
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#define IOMD_IO3CURA __IOMD(0x160)
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#define IOMD_IO3ENDA __IOMD(0x164)
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#define IOMD_IO3ENDA __IOMD(0x164)
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#define IOMD_IO3CURB __IOMD(0x168)
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#define IOMD_IO3CURB __IOMD(0x168)
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#define IOMD_IO3ENDB __IOMD(0x16C)
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#define IOMD_IO3ENDB __IOMD(0x16C)
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#define IOMD_IO3CR __IOMD(0x170)
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#define IOMD_IO3CR __IOMD(0x170)
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#define IOMD_IO3ST __IOMD(0x174)
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#define IOMD_IO3ST __IOMD(0x174)
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#define IOMD_SD0CURA __IOMD(0x180)
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#define IOMD_SD0CURA __IOMD(0x180)
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#define IOMD_SD0ENDA __IOMD(0x184)
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#define IOMD_SD0ENDA __IOMD(0x184)
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#define IOMD_SD0CURB __IOMD(0x188)
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#define IOMD_SD0CURB __IOMD(0x188)
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#define IOMD_SD0ENDB __IOMD(0x18C)
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#define IOMD_SD0ENDB __IOMD(0x18C)
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#define IOMD_SD0CR __IOMD(0x190)
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#define IOMD_SD0CR __IOMD(0x190)
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#define IOMD_SD0ST __IOMD(0x194)
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#define IOMD_SD0ST __IOMD(0x194)
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#define IOMD_SD1CURA __IOMD(0x1A0)
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#define IOMD_SD1CURA __IOMD(0x1A0)
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#define IOMD_SD1ENDA __IOMD(0x1A4)
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#define IOMD_SD1ENDA __IOMD(0x1A4)
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#define IOMD_SD1CURB __IOMD(0x1A8)
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#define IOMD_SD1CURB __IOMD(0x1A8)
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#define IOMD_SD1ENDB __IOMD(0x1AC)
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#define IOMD_SD1ENDB __IOMD(0x1AC)
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#define IOMD_SD1CR __IOMD(0x1B0)
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#define IOMD_SD1CR __IOMD(0x1B0)
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#define IOMD_SD1ST __IOMD(0x1B4)
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#define IOMD_SD1ST __IOMD(0x1B4)
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#define IOMD_CURSCUR __IOMD(0x1C0)
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#define IOMD_CURSCUR __IOMD(0x1C0)
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#define IOMD_CURSINIT __IOMD(0x1C4)
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#define IOMD_CURSINIT __IOMD(0x1C4)
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#define IOMD_VIDCUR __IOMD(0x1D0)
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#define IOMD_VIDCUR __IOMD(0x1D0)
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#define IOMD_VIDEND __IOMD(0x1D4)
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#define IOMD_VIDEND __IOMD(0x1D4)
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#define IOMD_VIDSTART __IOMD(0x1D8)
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#define IOMD_VIDSTART __IOMD(0x1D8)
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#define IOMD_VIDINIT __IOMD(0x1DC)
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#define IOMD_VIDINIT __IOMD(0x1DC)
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#define IOMD_VIDCR __IOMD(0x1E0)
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#define IOMD_VIDCR __IOMD(0x1E0)
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#define IOMD_DMASTAT __IOMD(0x1F0)
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#define IOMD_DMASTAT __IOMD(0x1F0)
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#define IOMD_DMAREQ __IOMD(0x1F4)
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#define IOMD_DMAREQ __IOMD(0x1F4)
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#define IOMD_DMAMASK __IOMD(0x1F8)
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#define IOMD_DMAMASK __IOMD(0x1F8)
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#define DMA_END_S (1 << 31)
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#define DMA_END_S (1 << 31)
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#define DMA_END_L (1 << 30)
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#define DMA_END_L (1 << 30)
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#define DMA_CR_C 0x80
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#define DMA_CR_C 0x80
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#define DMA_CR_D 0x40
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#define DMA_CR_D 0x40
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#define DMA_CR_E 0x20
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#define DMA_CR_E 0x20
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#define DMA_ST_OFL 4
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#define DMA_ST_OFL 4
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#define DMA_ST_INT 2
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#define DMA_ST_INT 2
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#define DMA_ST_AB 1
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#define DMA_ST_AB 1
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/*
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/*
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* IOC compatibility
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* IOC compatibility
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*/
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*/
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#define IOC_CONTROL IOMD_CONTROL
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#define IOC_CONTROL IOMD_CONTROL
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#define IOC_IRQSTATA IOMD_IRQSTATA
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#define IOC_IRQSTATA IOMD_IRQSTATA
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#define IOC_IRQREQA IOMD_IRQREQA
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#define IOC_IRQREQA IOMD_IRQREQA
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#define IOC_IRQCLRA IOMD_IRQCLRA
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#define IOC_IRQCLRA IOMD_IRQCLRA
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#define IOC_IRQMASKA IOMD_IRQMASKA
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#define IOC_IRQMASKA IOMD_IRQMASKA
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#define IOC_IRQSTATB IOMD_IRQSTATB
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#define IOC_IRQSTATB IOMD_IRQSTATB
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#define IOC_IRQREQB IOMD_IRQREQB
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#define IOC_IRQREQB IOMD_IRQREQB
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#define IOC_IRQMASKB IOMD_IRQMASKB
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#define IOC_IRQMASKB IOMD_IRQMASKB
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#define IOC_FIQSTAT IOMD_FIQSTAT
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#define IOC_FIQSTAT IOMD_FIQSTAT
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#define IOC_FIQREQ IOMD_FIQREQ
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#define IOC_FIQREQ IOMD_FIQREQ
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#define IOC_FIQMASK IOMD_FIQMASK
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#define IOC_FIQMASK IOMD_FIQMASK
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#define IOC_T0CNTL IOMD_T0CNTL
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#define IOC_T0CNTL IOMD_T0CNTL
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#define IOC_T0LTCHL IOMD_T0LTCHL
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#define IOC_T0LTCHL IOMD_T0LTCHL
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#define IOC_T0CNTH IOMD_T0CNTH
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#define IOC_T0CNTH IOMD_T0CNTH
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#define IOC_T0LTCHH IOMD_T0LTCHH
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#define IOC_T0LTCHH IOMD_T0LTCHH
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#define IOC_T0GO IOMD_T0GO
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#define IOC_T0GO IOMD_T0GO
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#define IOC_T0LATCH IOMD_T0LATCH
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#define IOC_T0LATCH IOMD_T0LATCH
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#define IOC_T1CNTL IOMD_T1CNTL
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#define IOC_T1CNTL IOMD_T1CNTL
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#define IOC_T1LTCHL IOMD_T1LTCHL
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#define IOC_T1LTCHL IOMD_T1LTCHL
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#define IOC_T1CNTH IOMD_T1CNTH
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#define IOC_T1CNTH IOMD_T1CNTH
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#define IOC_T1LTCHH IOMD_T1LTCHH
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#define IOC_T1LTCHH IOMD_T1LTCHH
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#define IOC_T1GO IOMD_T1GO
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#define IOC_T1GO IOMD_T1GO
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#define IOC_T1LATCH IOMD_T1LATCH
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#define IOC_T1LATCH IOMD_T1LATCH
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/*
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/*
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* DMA (MEMC) compatibility
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* DMA (MEMC) compatibility
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*/
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*/
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#define HALF_SAM vram_half_sam
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#define HALF_SAM vram_half_sam
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#define VDMA_ALIGNMENT (HALF_SAM * 2)
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#define VDMA_ALIGNMENT (HALF_SAM * 2)
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#define VDMA_XFERSIZE (HALF_SAM)
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#define VDMA_XFERSIZE (HALF_SAM)
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#define VDMA_INIT IOMD_VIDINIT
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#define VDMA_INIT IOMD_VIDINIT
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#define VDMA_START IOMD_VIDSTART
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#define VDMA_START IOMD_VIDSTART
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#define VDMA_END IOMD_VIDEND
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#define VDMA_END IOMD_VIDEND
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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extern unsigned int vram_half_sam;
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extern unsigned int vram_half_sam;
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#define video_set_dma(start,end,offset) \
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#define video_set_dma(start,end,offset) \
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do { \
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do { \
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outl (SCREEN_START + start, VDMA_START); \
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outl (SCREEN_START + start, VDMA_START); \
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outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
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outl (SCREEN_START + end - VDMA_XFERSIZE, VDMA_END); \
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if (offset >= end - VDMA_XFERSIZE) \
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if (offset >= end - VDMA_XFERSIZE) \
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offset |= 0x40000000; \
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offset |= 0x40000000; \
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outl (SCREEN_START + offset, VDMA_INIT); \
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outl (SCREEN_START + offset, VDMA_INIT); \
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} while (0)
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} while (0)
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#endif
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#endif
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#endif
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#endif
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#ifdef HAS_EXPMASK
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#ifdef HAS_EXPMASK
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#ifndef __ASSEMBLER__
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#ifndef __ASSEMBLER__
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#define __EXPMASK(offset) (((volatile unsigned char *)EXPMASK_BASE)[offset])
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#define __EXPMASK(offset) (((volatile unsigned char *)EXPMASK_BASE)[offset])
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#else
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#else
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#define __EXPMASK(offset) offset
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#define __EXPMASK(offset) offset
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#endif
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#endif
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#define EXPMASK_STATUS __EXPMASK(0x00)
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#define EXPMASK_STATUS __EXPMASK(0x00)
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#define EXPMASK_ENABLE __EXPMASK(0x04)
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#define EXPMASK_ENABLE __EXPMASK(0x04)
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#endif
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#endif
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#endif
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#endif
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