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/* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
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/* Copyright (C) 1998 Kenneth Albanowski <kjahds@kjahds.com>,
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* The Silver Hammer Group, Ltd.
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* The Silver Hammer Group, Ltd.
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*/
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*/
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#ifndef _M68K_SHGLCORE_H
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#ifndef _M68K_SHGLCORE_H
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#define _M68K_SHGLCORE_H
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#define _M68K_SHGLCORE_H
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#include <linux/config.h>
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#include <linux/config.h>
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#ifdef CONFIG_SHGLCORE
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#ifdef CONFIG_SHGLCORE
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#include <asm/MC68332.h>
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#include <asm/MC68332.h>
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#ifdef CONFIG_SHGLCORE_2MEG
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#ifdef CONFIG_SHGLCORE_2MEG
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#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
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#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
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#define SHGLCORE_ROM_BANK_1_ADDR 0x100000
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#define SHGLCORE_ROM_BANK_1_ADDR 0x100000
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#define SHGLCORE_RAM_BANK_0_ADDR 0x200000
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#define SHGLCORE_RAM_BANK_0_ADDR 0x200000
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#define SHGLCORE_RAM_BANK_1_ADDR 0x300000
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#define SHGLCORE_RAM_BANK_1_ADDR 0x300000
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#define SHGLCORE_FLASH_BANK_0_ADDR 0x400000
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#define SHGLCORE_FLASH_BANK_0_ADDR 0x400000
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#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_ROM_BANK_1_LENGTH 0x100000
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#define SHGLCORE_ROM_BANK_1_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_1_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_1_LENGTH 0x100000
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#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
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#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
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#define SHGLCORE_ACC_ADDR 0x600000
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#define SHGLCORE_ACC_ADDR 0x600000
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#define SHGLCORE_LANCE_ADDR 0x700000
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#define SHGLCORE_LANCE_ADDR 0x700000
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#else
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#else
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#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
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#define SHGLCORE_ROM_BANK_0_ADDR 0x000000
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#define SHGLCORE_RAM_BANK_0_ADDR 0x100000
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#define SHGLCORE_RAM_BANK_0_ADDR 0x100000
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#define SHGLCORE_FLASH_BANK_0_ADDR 0x300000
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#define SHGLCORE_FLASH_BANK_0_ADDR 0x300000
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#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_ROM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_RAM_BANK_0_LENGTH 0x100000
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#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
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#define SHGLCORE_FLASH_BANK_0_LENGTH 0x80000
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#define SHGLCORE_ACC_ADDR 0x400000
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#define SHGLCORE_ACC_ADDR 0x400000
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#define SHGLCORE_LANCE_ADDR 0x500000
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#define SHGLCORE_LANCE_ADDR 0x500000
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#endif
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#endif
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#define MAX_DMA_ADDRESS SHGLCORE_RAM_BANK_0_ADDR + SHGLCORE_RAM_BANK_0_LENGTH
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#define MAX_DMA_ADDRESS SHGLCORE_RAM_BANK_0_ADDR + SHGLCORE_RAM_BANK_0_LENGTH
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#define SHGLCORE_LATCH_ADDR (SHGLCORE_ACC_ADDR+0x100)
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#define SHGLCORE_LATCH_ADDR (SHGLCORE_ACC_ADDR+0x100)
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#define SHGLCORE_1865_0_ADDR (SHGLCORE_ACC_ADDR+0x600)
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#define SHGLCORE_1865_0_ADDR (SHGLCORE_ACC_ADDR+0x600)
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#define SHGLCORE_1865_1_ADDR (SHGLCORE_ACC_ADDR+0x700)
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#define SHGLCORE_1865_1_ADDR (SHGLCORE_ACC_ADDR+0x700)
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#define SHGLCORE_LATCH_BIT(x) BYTE_REF(SHGLCORE_LATCH_ADDR+x)
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#define SHGLCORE_LATCH_BIT(x) BYTE_REF(SHGLCORE_LATCH_ADDR+x)
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#define SHGLCORE_LATCH_STATUS_LED 0
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#define SHGLCORE_LATCH_STATUS_LED 0
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#define SHGLCORE_LATCH_ERROR_LED 1
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#define SHGLCORE_LATCH_ERROR_LED 1
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#define SHGLCORE_LATCH_ALARM_LED 2
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#define SHGLCORE_LATCH_ALARM_LED 2
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#define SHGLCORE_LATCH_1865 4
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#define SHGLCORE_LATCH_1865 4
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#define SHGLCORE_LATCH_RELAY_1 6
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#define SHGLCORE_LATCH_RELAY_1 6
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#define SHGLCORE_LATCH_RELAY_2 7
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#define SHGLCORE_LATCH_RELAY_2 7
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#endif /* SHGLCORE */
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#endif /* SHGLCORE */
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#endif /* _M68K_SHGLCORE_H */
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#endif /* _M68K_SHGLCORE_H */
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