/*
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/*
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* PowerPC machine specifics
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* PowerPC machine specifics
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*/
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*/
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#ifndef _PPC_MACHINE_H_
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#ifndef _PPC_MACHINE_H_
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#define _PPC_MACHINE_H_
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#define _PPC_MACHINE_H_
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/* Bit encodings for Machine State Register (MSR) */
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/* Bit encodings for Machine State Register (MSR) */
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#define MSR_POW (1<<18) /* Enable Power Management */
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#define MSR_POW (1<<18) /* Enable Power Management */
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */
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#define MSR_TGPR (1<<17) /* TLB Update registers in use */
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#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
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#define MSR_ILE (1<<16) /* Interrupt Little-Endian enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_EE (1<<15) /* External Interrupt enable */
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#define MSR_PR (1<<14) /* Supervisor/User privilege */
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#define MSR_PR (1<<14) /* Supervisor/User privilege */
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#define MSR_FP (1<<13) /* Floating Point enable */
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#define MSR_FP (1<<13) /* Floating Point enable */
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#define MSR_ME (1<<12) /* Machine Check enable */
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#define MSR_ME (1<<12) /* Machine Check enable */
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
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#define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
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#define MSR_SE (1<<10) /* Single Step */
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#define MSR_SE (1<<10) /* Single Step */
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_BE (1<<9) /* Branch Trace */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_IR (1<<5) /* Instruction MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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#define MSR_DR (1<<4) /* Data MMU enable */
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#define MSR_RI (1<<1) /* Recoverable Exception */
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#define MSR_RI (1<<1) /* Recoverable Exception */
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#define MSR_LE (1<<0) /* Little-Endian enable */
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#define MSR_LE (1<<0) /* Little-Endian enable */
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#define MSR_ MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
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#define MSR_ MSR_FP|MSR_FE0|MSR_FE1|MSR_ME
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#define MSR_USER MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
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#define MSR_USER MSR_|MSR_PR|MSR_EE|MSR_IR|MSR_DR
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/* Bit encodings for Hardware Implementation Register (HID0) */
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/* Bit encodings for Hardware Implementation Register (HID0) */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EMCP (1<<31) /* Enable Machine Check pin */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBA (1<<29) /* Enable Bus Address Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_EBD (1<<28) /* Enable Bus Data Parity */
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#define HID0_SBCLK (1<<27)
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#define HID0_SBCLK (1<<27)
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#define HID0_EICE (1<<26)
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#define HID0_EICE (1<<26)
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#define HID0_ECLK (1<<25)
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#define HID0_ECLK (1<<25)
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#define HID0_PAR (1<<24)
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#define HID0_PAR (1<<24)
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#define HID0_DOZE (1<<23)
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#define HID0_DOZE (1<<23)
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#define HID0_NAP (1<<22)
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#define HID0_NAP (1<<22)
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#define HID0_SLEEP (1<<21)
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#define HID0_SLEEP (1<<21)
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#define HID0_DPM (1<<20)
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#define HID0_DPM (1<<20)
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_ICE (1<<15) /* Instruction Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_DCE (1<<14) /* Data Cache Enable */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_DLOCK (1<<12) /* Data Cache Lock */
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#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
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#define HID0_ICFI (1<<11) /* Instruction Cache Flash Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#define HID0_DCI (1<<10) /* Data Cache Invalidate */
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#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
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#define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */
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#define HID0_BHTE (1<<2) /* Branch History Table Enable */
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#define HID0_BHTE (1<<2) /* Branch History Table Enable */
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#endif
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#endif
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