/* $Id: mbus.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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/* $Id: mbus.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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* mbus.h: Various defines for MBUS modules.
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* mbus.h: Various defines for MBUS modules.
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*
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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*/
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#ifndef _SPARC_MBUS_H
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#ifndef _SPARC_MBUS_H
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#define _SPARC_MBUS_H
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#define _SPARC_MBUS_H
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#include <asm/ross.h> /* HyperSparc stuff */
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#include <asm/ross.h> /* HyperSparc stuff */
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#include <asm/cypress.h> /* Cypress Chips */
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#include <asm/cypress.h> /* Cypress Chips */
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#include <asm/viking.h> /* Ugh, bug city... */
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#include <asm/viking.h> /* Ugh, bug city... */
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enum mbus_module {
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enum mbus_module {
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HyperSparc = 0,
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HyperSparc = 0,
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Cypress = 1,
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Cypress = 1,
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Cypress_vE = 2,
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Cypress_vE = 2,
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Cypress_vD = 3,
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Cypress_vD = 3,
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Swift_ok = 4,
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Swift_ok = 4,
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Swift_bad_c = 5,
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Swift_bad_c = 5,
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Swift_lots_o_bugs = 6,
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Swift_lots_o_bugs = 6,
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Tsunami = 7,
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Tsunami = 7,
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Viking_12 = 8,
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Viking_12 = 8,
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Viking_2x = 9,
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Viking_2x = 9,
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Viking_30 = 10,
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Viking_30 = 10,
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Viking_35 = 11,
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Viking_35 = 11,
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Viking_new = 12,
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Viking_new = 12,
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SRMMU_INVAL_MOD = 13,
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SRMMU_INVAL_MOD = 13,
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};
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};
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extern enum mbus_module srmmu_modtype;
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extern enum mbus_module srmmu_modtype;
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extern unsigned int viking_rev, swift_rev, cypress_rev;
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extern unsigned int viking_rev, swift_rev, cypress_rev;
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/* HW Mbus module bugs we have to deal with */
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/* HW Mbus module bugs we have to deal with */
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#define HWBUG_COPYBACK_BROKEN 0x00000001
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#define HWBUG_COPYBACK_BROKEN 0x00000001
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#define HWBUG_ASIFLUSH_BROKEN 0x00000002
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#define HWBUG_ASIFLUSH_BROKEN 0x00000002
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#define HWBUG_VACFLUSH_BITROT 0x00000004
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#define HWBUG_VACFLUSH_BITROT 0x00000004
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#define HWBUG_KERN_ACCBROKEN 0x00000008
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#define HWBUG_KERN_ACCBROKEN 0x00000008
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#define HWBUG_KERN_CBITBROKEN 0x00000010
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#define HWBUG_KERN_CBITBROKEN 0x00000010
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#define HWBUG_MODIFIED_BITROT 0x00000020
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#define HWBUG_MODIFIED_BITROT 0x00000020
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#define HWBUG_PC_BADFAULT_ADDR 0x00000040
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#define HWBUG_PC_BADFAULT_ADDR 0x00000040
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#define HWBUG_SUPERSCALAR_BAD 0x00000080
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#define HWBUG_SUPERSCALAR_BAD 0x00000080
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#define HWBUG_PACINIT_BITROT 0x00000100
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#define HWBUG_PACINIT_BITROT 0x00000100
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extern unsigned int hwbug_bitmask;
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extern unsigned int hwbug_bitmask;
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/* First the module type values. To find out which you have, just load
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/* First the module type values. To find out which you have, just load
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* the mmu control register from ASI_M_MMUREG alternate address space and
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* the mmu control register from ASI_M_MMUREG alternate address space and
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* shift the value right 28 bits.
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* shift the value right 28 bits.
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*/
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*/
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/* IMPL field means the company which produced the chip. */
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/* IMPL field means the company which produced the chip. */
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#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
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#define MBUS_VIKING 0x4 /* bleech, Texas Instruments Module */
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#define MBUS_LSI 0x3 /* LSI Logics */
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#define MBUS_LSI 0x3 /* LSI Logics */
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#define MBUS_ROSS 0x1 /* Ross is nice */
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#define MBUS_ROSS 0x1 /* Ross is nice */
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#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
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#define MBUS_FMI 0x0 /* Fujitsu Microelectronics/Swift */
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/* Ross Module versions */
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/* Ross Module versions */
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#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
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#define ROSS_604_REV_CDE 0x0 /* revisions c, d, and e */
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#define ROSS_604_REV_F 0x1 /* revision f */
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#define ROSS_604_REV_F 0x1 /* revision f */
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#define ROSS_605 0xf /* revision a, a.1, and a.2 */
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#define ROSS_605 0xf /* revision a, a.1, and a.2 */
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#define ROSS_605_REV_B 0xe /* revision b */
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#define ROSS_605_REV_B 0xe /* revision b */
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/* TI Viking Module versions */
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/* TI Viking Module versions */
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#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
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#define VIKING_REV_12 0x1 /* Version 1.2 or SPARCclassic's CPU */
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#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
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#define VIKING_REV_2 0x2 /* Version 2.1, 2.2, 2.3, and 2.4 */
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#define VIKING_REV_30 0x3 /* Version 3.0 */
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#define VIKING_REV_30 0x3 /* Version 3.0 */
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#define VIKING_REV_35 0x4 /* Version 3.5 */
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#define VIKING_REV_35 0x4 /* Version 3.5 */
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/* LSI Logics. */
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/* LSI Logics. */
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#define LSI_L64815 0x0
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#define LSI_L64815 0x0
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/* Fujitsu */
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/* Fujitsu */
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#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
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#define FMI_AURORA 0x4 /* MB8690x, a Swift module... */
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/* For multiprocessor support we need to be able to obtain the CPU id and
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/* For multiprocessor support we need to be able to obtain the CPU id and
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* the MBUS Module id.
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* the MBUS Module id.
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*/
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*/
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/* The CPU ID is encoded in the trap base register, 20 bits to the left of
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/* The CPU ID is encoded in the trap base register, 20 bits to the left of
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* bit zero, with 2 bits being significant.
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* bit zero, with 2 bits being significant.
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*/
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*/
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#define TBR_ID_SHIFT 20
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#define TBR_ID_SHIFT 20
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extern inline int get_cpuid(void)
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extern inline int get_cpuid(void)
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{
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{
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register int retval;
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register int retval;
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__asm__ __volatile__("rd %%tbr, %0\n\t"
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__asm__ __volatile__("rd %%tbr, %0\n\t"
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"srl %0, %1, %0\n\t" :
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"srl %0, %1, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"i" (TBR_ID_SHIFT));
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"i" (TBR_ID_SHIFT));
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return (retval & 3);
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return (retval & 3);
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}
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}
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extern inline int get_modid(void)
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extern inline int get_modid(void)
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{
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{
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return (get_cpuid() | 0x8);
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return (get_cpuid() | 0x8);
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}
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}
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#endif /* !(_SPARC_MBUS_H) */
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#endif /* !(_SPARC_MBUS_H) */
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