/* $Id: msi.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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/* $Id: msi.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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* msi.h: Defines specific to the MBus - Sbus - Interface.
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* msi.h: Defines specific to the MBus - Sbus - Interface.
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*
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1996 Eddie C. Dost (ecd@pool.informatik.rwth-aachen.de)
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* Copyright (C) 1996 Eddie C. Dost (ecd@pool.informatik.rwth-aachen.de)
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*/
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*/
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#ifndef _SPARC_MSI_H
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#ifndef _SPARC_MSI_H
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#define _SPARC_MSI_H
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#define _SPARC_MSI_H
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/*
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/*
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* Locations of MSI Registers.
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* Locations of MSI Registers.
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*/
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*/
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#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
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#define MSI_MBUS_ARBEN 0xe0001008 /* MBus Arbiter Enable register */
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/*
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/*
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* Useful bits in the MSI Registers.
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* Useful bits in the MSI Registers.
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*/
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*/
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#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
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#define MSI_ASYNC_MODE 0x80000000 /* Operate the MSI asynchronously */
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extern inline void msi_set_sync(void)
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extern inline void msi_set_sync(void)
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{
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{
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__asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
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__asm__ __volatile__ ("lda [%0] %1, %%g3\n\t"
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"andn %%g3, %2, %%g3\n\t"
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"andn %%g3, %2, %%g3\n\t"
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"sta %%g3, [%0] %1\n\t" : :
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"sta %%g3, [%0] %1\n\t" : :
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"r" (MSI_MBUS_ARBEN),
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"r" (MSI_MBUS_ARBEN),
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"i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
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"i" (ASI_M_CTL), "r" (MSI_ASYNC_MODE) : "g3");
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}
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}
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#endif /* !(_SPARC_MSI_H) */
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#endif /* !(_SPARC_MSI_H) */
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