/* $Id: pgtsrmmu.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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/* $Id: pgtsrmmu.h,v 1.1 2005-12-20 11:32:11 jcastillo Exp $
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* pgtsrmmu.h: SRMMU page table defines and code.
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* pgtsrmmu.h: SRMMU page table defines and code.
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*
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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*/
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#ifndef _SPARC_PGTSRMMU_H
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#ifndef _SPARC_PGTSRMMU_H
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#define _SPARC_PGTSRMMU_H
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#define _SPARC_PGTSRMMU_H
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#include <linux/config.h>
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#include <linux/config.h>
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#include <asm/page.h>
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#include <asm/page.h>
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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/* PMD_SHIFT determines the size of the area a second-level page table can map */
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#define SRMMU_PMD_SHIFT 18
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#define SRMMU_PMD_SHIFT 18
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#define SRMMU_PMD_SIZE (1UL << SRMMU_PMD_SHIFT)
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#define SRMMU_PMD_SIZE (1UL << SRMMU_PMD_SHIFT)
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#define SRMMU_PMD_MASK (~(SRMMU_PMD_SIZE-1))
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#define SRMMU_PMD_MASK (~(SRMMU_PMD_SIZE-1))
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#define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
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#define SRMMU_PMD_ALIGN(addr) (((addr)+SRMMU_PMD_SIZE-1)&SRMMU_PMD_MASK)
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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/* PGDIR_SHIFT determines what a third-level page table entry can map */
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#define SRMMU_PGDIR_SHIFT 24
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#define SRMMU_PGDIR_SHIFT 24
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#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
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#define SRMMU_PGDIR_SIZE (1UL << SRMMU_PGDIR_SHIFT)
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#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
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#define SRMMU_PGDIR_MASK (~(SRMMU_PGDIR_SIZE-1))
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#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
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#define SRMMU_PGDIR_ALIGN(addr) (((addr)+SRMMU_PGDIR_SIZE-1)&SRMMU_PGDIR_MASK)
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#define SRMMU_PTRS_PER_PTE 64
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#define SRMMU_PTRS_PER_PTE 64
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#define SRMMU_PTRS_PER_PMD 64
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#define SRMMU_PTRS_PER_PMD 64
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#define SRMMU_PTRS_PER_PGD 256
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#define SRMMU_PTRS_PER_PGD 256
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#define SRMMU_PTE_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
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#define SRMMU_PTE_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
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#define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
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#define SRMMU_PMD_TABLE_SIZE 0x100 /* 64 entries, 4 bytes a piece */
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#define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */
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#define SRMMU_PGD_TABLE_SIZE 0x400 /* 256 entries, 4 bytes a piece */
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#define SRMMU_VMALLOC_START (0xfe200000)
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#define SRMMU_VMALLOC_START (0xfe200000)
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/* Definition of the values in the ET field of PTD's and PTE's */
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/* Definition of the values in the ET field of PTD's and PTE's */
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#define SRMMU_ET_MASK 0x3
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#define SRMMU_ET_MASK 0x3
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#define SRMMU_ET_INVALID 0x0
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#define SRMMU_ET_INVALID 0x0
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#define SRMMU_ET_PTD 0x1
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#define SRMMU_ET_PTD 0x1
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#define SRMMU_ET_PTE 0x2
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#define SRMMU_ET_PTE 0x2
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#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
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#define SRMMU_ET_REPTE 0x3 /* AIEEE, SuperSparc II reverse endian page! */
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/* Physical page extraction from PTP's and PTE's. */
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/* Physical page extraction from PTP's and PTE's. */
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#define SRMMU_CTX_PMASK 0xfffffff0
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#define SRMMU_CTX_PMASK 0xfffffff0
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#define SRMMU_PTD_PMASK 0xfffffff0
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#define SRMMU_PTD_PMASK 0xfffffff0
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#define SRMMU_PTE_PMASK 0xffffff00
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#define SRMMU_PTE_PMASK 0xffffff00
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/* The pte non-page bits. Some notes:
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/* The pte non-page bits. Some notes:
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* 1) cache, dirty, valid, and ref are frobbable
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* 1) cache, dirty, valid, and ref are frobbable
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* for both supervisor and user pages.
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* for both supervisor and user pages.
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* 2) exec and write will only give the desired effect
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* 2) exec and write will only give the desired effect
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* on user pages
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* on user pages
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* 3) use priv and priv_readonly for changing the
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* 3) use priv and priv_readonly for changing the
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* characteristics of supervisor ptes
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* characteristics of supervisor ptes
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*/
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*/
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#define SRMMU_CACHE 0x80
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#define SRMMU_CACHE 0x80
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#define SRMMU_DIRTY 0x40
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#define SRMMU_DIRTY 0x40
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#define SRMMU_REF 0x20
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#define SRMMU_REF 0x20
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#define SRMMU_EXEC 0x08
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#define SRMMU_EXEC 0x08
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#define SRMMU_WRITE 0x04
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#define SRMMU_WRITE 0x04
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#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
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#define SRMMU_VALID 0x02 /* SRMMU_ET_PTE */
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#define SRMMU_PRIV 0x1c
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#define SRMMU_PRIV 0x1c
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#define SRMMU_PRIV_RDONLY 0x18
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#define SRMMU_PRIV_RDONLY 0x18
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#define SRMMU_CHG_MASK (SRMMU_REF | SRMMU_DIRTY | SRMMU_ET_PTE)
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#define SRMMU_CHG_MASK (SRMMU_REF | SRMMU_DIRTY | SRMMU_ET_PTE)
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/* Some day I will implement true fine grained access bits for
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/* Some day I will implement true fine grained access bits for
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* user pages because the SRMMU gives us the capabilities to
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* user pages because the SRMMU gives us the capabilities to
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* enforce all the protection levels that vma's can have.
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* enforce all the protection levels that vma's can have.
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* XXX But for now...
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* XXX But for now...
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*/
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*/
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#define SRMMU_PAGE_NONE __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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#define SRMMU_PAGE_NONE __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_PRIV | SRMMU_REF)
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SRMMU_PRIV | SRMMU_REF)
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#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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#define SRMMU_PAGE_SHARED __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
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SRMMU_EXEC | SRMMU_WRITE | SRMMU_REF)
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#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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#define SRMMU_PAGE_COPY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_REF)
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SRMMU_EXEC | SRMMU_REF)
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#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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#define SRMMU_PAGE_RDONLY __pgprot(SRMMU_VALID | SRMMU_CACHE | \
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SRMMU_EXEC | SRMMU_REF)
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SRMMU_EXEC | SRMMU_REF)
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#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV)
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#define SRMMU_PAGE_KERNEL __pgprot(SRMMU_VALID | SRMMU_CACHE | SRMMU_PRIV)
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/* SRMMU Register addresses in ASI 0x4. These are valid for all
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/* SRMMU Register addresses in ASI 0x4. These are valid for all
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* current SRMMU implementations that exist.
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* current SRMMU implementations that exist.
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*/
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*/
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#define SRMMU_CTRL_REG 0x00000000
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#define SRMMU_CTRL_REG 0x00000000
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#define SRMMU_CTXTBL_PTR 0x00000100
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#define SRMMU_CTXTBL_PTR 0x00000100
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#define SRMMU_CTX_REG 0x00000200
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#define SRMMU_CTX_REG 0x00000200
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#define SRMMU_FAULT_STATUS 0x00000300
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#define SRMMU_FAULT_STATUS 0x00000300
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#define SRMMU_FAULT_ADDR 0x00000400
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#define SRMMU_FAULT_ADDR 0x00000400
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/* Accessing the MMU control register. */
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/* Accessing the MMU control register. */
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extern inline unsigned int srmmu_get_mmureg(void)
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extern inline unsigned int srmmu_get_mmureg(void)
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{
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{
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unsigned int retval;
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unsigned int retval;
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__asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
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__asm__ __volatile__("lda [%%g0] %1, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"i" (ASI_M_MMUREGS));
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"i" (ASI_M_MMUREGS));
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return retval;
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return retval;
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}
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}
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extern inline void srmmu_set_mmureg(unsigned long regval)
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extern inline void srmmu_set_mmureg(unsigned long regval)
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{
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{
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__asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
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__asm__ __volatile__("sta %0, [%%g0] %1\n\t" : :
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"r" (regval), "i" (ASI_M_MMUREGS) : "memory");
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"r" (regval), "i" (ASI_M_MMUREGS) : "memory");
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}
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}
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extern inline void srmmu_set_ctable_ptr(unsigned long paddr)
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extern inline void srmmu_set_ctable_ptr(unsigned long paddr)
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{
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{
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paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
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paddr = ((paddr >> 4) & SRMMU_CTX_PMASK);
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#if CONFIG_AP1000
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#if CONFIG_AP1000
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/* weird memory system on the AP1000 */
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/* weird memory system on the AP1000 */
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paddr |= (0x8<<28);
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paddr |= (0x8<<28);
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#endif
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#endif
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
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"r" (paddr), "r" (SRMMU_CTXTBL_PTR),
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"r" (paddr), "r" (SRMMU_CTXTBL_PTR),
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"i" (ASI_M_MMUREGS) :
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"i" (ASI_M_MMUREGS) :
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"memory");
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"memory");
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}
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}
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extern inline unsigned long srmmu_get_ctable_ptr(void)
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extern inline unsigned long srmmu_get_ctable_ptr(void)
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{
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{
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unsigned int retval;
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unsigned int retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"r" (SRMMU_CTXTBL_PTR),
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"r" (SRMMU_CTXTBL_PTR),
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"i" (ASI_M_MMUREGS));
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"i" (ASI_M_MMUREGS));
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return (retval & SRMMU_CTX_PMASK) << 4;
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return (retval & SRMMU_CTX_PMASK) << 4;
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}
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}
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extern inline void srmmu_set_context(int context)
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extern inline void srmmu_set_context(int context)
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{
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{
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
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__asm__ __volatile__("sta %0, [%1] %2\n\t" : :
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"r" (context), "r" (SRMMU_CTX_REG),
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"r" (context), "r" (SRMMU_CTX_REG),
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"i" (ASI_M_MMUREGS) : "memory");
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"i" (ASI_M_MMUREGS) : "memory");
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}
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}
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extern inline int srmmu_get_context(void)
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extern inline int srmmu_get_context(void)
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{
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{
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register int retval;
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register int retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"r" (SRMMU_CTX_REG),
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"r" (SRMMU_CTX_REG),
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"i" (ASI_M_MMUREGS));
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"i" (ASI_M_MMUREGS));
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return retval;
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return retval;
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}
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}
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extern inline unsigned int srmmu_get_fstatus(void)
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extern inline unsigned int srmmu_get_fstatus(void)
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{
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{
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unsigned int retval;
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unsigned int retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
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"r" (SRMMU_FAULT_STATUS), "i" (ASI_M_MMUREGS));
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return retval;
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return retval;
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}
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}
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extern inline unsigned int srmmu_get_faddr(void)
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extern inline unsigned int srmmu_get_faddr(void)
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{
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{
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unsigned int retval;
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unsigned int retval;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
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"r" (SRMMU_FAULT_ADDR), "i" (ASI_M_MMUREGS));
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return retval;
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return retval;
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}
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}
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/* This is guaranteed on all SRMMU's. */
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/* This is guaranteed on all SRMMU's. */
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extern inline void srmmu_flush_whole_tlb(void)
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extern inline void srmmu_flush_whole_tlb(void)
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{
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (0x400), /* Flush entire TLB!! */
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"r" (0x400), /* Flush entire TLB!! */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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}
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/* These flush types are not available on all chips... */
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/* These flush types are not available on all chips... */
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extern inline void srmmu_flush_tlb_ctx(void)
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extern inline void srmmu_flush_tlb_ctx(void)
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{
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{
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (0x300), /* Flush TLB ctx.. */
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"r" (0x300), /* Flush TLB ctx.. */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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}
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extern inline void srmmu_flush_tlb_region(unsigned long addr)
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extern inline void srmmu_flush_tlb_region(unsigned long addr)
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{
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{
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addr &= SRMMU_PGDIR_MASK;
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addr &= SRMMU_PGDIR_MASK;
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (addr | 0x200), /* Flush TLB region.. */
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"r" (addr | 0x200), /* Flush TLB region.. */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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}
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extern inline void srmmu_flush_tlb_segment(unsigned long addr)
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extern inline void srmmu_flush_tlb_segment(unsigned long addr)
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{
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{
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addr &= SRMMU_PMD_MASK;
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addr &= SRMMU_PMD_MASK;
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (addr | 0x100), /* Flush TLB segment.. */
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"r" (addr | 0x100), /* Flush TLB segment.. */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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}
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extern inline void srmmu_flush_tlb_page(unsigned long page)
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extern inline void srmmu_flush_tlb_page(unsigned long page)
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{
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{
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page &= PAGE_MASK;
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page &= PAGE_MASK;
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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__asm__ __volatile__("sta %%g0, [%0] %1\n\t": :
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"r" (page), /* Flush TLB page.. */
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"r" (page), /* Flush TLB page.. */
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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"i" (ASI_M_FLUSH_PROBE) : "memory");
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}
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}
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extern inline unsigned long srmmu_hwprobe(unsigned long vaddr)
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extern inline unsigned long srmmu_hwprobe(unsigned long vaddr)
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{
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{
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unsigned long retval;
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unsigned long retval;
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vaddr &= PAGE_MASK;
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vaddr &= PAGE_MASK;
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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__asm__ __volatile__("lda [%1] %2, %0\n\t" :
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"=r" (retval) :
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"=r" (retval) :
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"r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
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"r" (vaddr | 0x400), "i" (ASI_M_FLUSH_PROBE));
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return retval;
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return retval;
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}
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}
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extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
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extern unsigned long (*srmmu_read_physical)(unsigned long paddr);
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extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
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extern void (*srmmu_write_physical)(unsigned long paddr, unsigned long word);
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#endif /* !(_SPARC_PGTSRMMU_H) */
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#endif /* !(_SPARC_PGTSRMMU_H) */
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