/* $Id: ultra.h,v 1.1 2005-12-20 11:32:12 jcastillo Exp $
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/* $Id: ultra.h,v 1.1 2005-12-20 11:32:12 jcastillo Exp $
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* ultra.h: Definitions and defines for the TI V9 UltraSparc.
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* ultra.h: Definitions and defines for the TI V9 UltraSparc.
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*
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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*/
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#ifndef _SPARC_ULTRA_H
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#ifndef _SPARC_ULTRA_H
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#define _SPARC_ULTRA_H
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#define _SPARC_ULTRA_H
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/* Spitfire MMU control register:
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/* Spitfire MMU control register:
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*
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*
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* ----------------------------------------------------------
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* ----------------------------------------------------------
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* | | IMPL | VERS | | MID | |
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* | | IMPL | VERS | | MID | |
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* ----------------------------------------------------------
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* ----------------------------------------------------------
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* 64 31-28 27-24 23-22 21-17 16 0
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* 64 31-28 27-24 23-22 21-17 16 0
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*
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*
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* IMPL: Implementation of this Spitfire.
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* IMPL: Implementation of this Spitfire.
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* VERS: Version of this Spitfire.
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* VERS: Version of this Spitfire.
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* MID: Module ID of this processor.
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* MID: Module ID of this processor.
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*/
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*/
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#define SPITFIRE_MIDMASK 0x00000000003e0000
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#define SPITFIRE_MIDMASK 0x00000000003e0000
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/* Spitfire Load Store Unit control register:
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/* Spitfire Load Store Unit control register:
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*
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*
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* ---------------------------------------------------------------------
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* ---------------------------------------------------------------------
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* | RSV | PWR | PWW | VWR | VWW | RSV | PMASK | DME | IME | DCE | ICE |
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* | RSV | PWR | PWW | VWR | VWW | RSV | PMASK | DME | IME | DCE | ICE |
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* ---------------------------------------------------------------------
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* ---------------------------------------------------------------------
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* 63-25 24 23 22 21 20 19-4 3 2 1 0
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* 63-25 24 23 22 21 20 19-4 3 2 1 0
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*
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*
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* PWR: Physical Watchpoint Read enable: 0=off 1=on
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* PWR: Physical Watchpoint Read enable: 0=off 1=on
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* PWW: Physical Watchpoint Write enable: 0=off 1=on
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* PWW: Physical Watchpoint Write enable: 0=off 1=on
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* VWR: Virtual Watchpoint Read enable: 0=off 1=on
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* VWR: Virtual Watchpoint Read enable: 0=off 1=on
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* VWW: Virtual Watchpoint Write enable: 0=off 1=on
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* VWW: Virtual Watchpoint Write enable: 0=off 1=on
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* PMASK: Parity MASK ???
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* PMASK: Parity MASK ???
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* DME: Data MMU Enable: 0=off 1=on
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* DME: Data MMU Enable: 0=off 1=on
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* IME: Instruction MMU Enable: 0=off 1=on
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* IME: Instruction MMU Enable: 0=off 1=on
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* DCE: Data Cache Enable: 0=off 1=on
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* DCE: Data Cache Enable: 0=off 1=on
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* ICE: Instruction Cache Enable: 0=off 1=on
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* ICE: Instruction Cache Enable: 0=off 1=on
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*/
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*/
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#define SPITFIRE_LSU_PWR 0x01000000
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#define SPITFIRE_LSU_PWR 0x01000000
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#define SPITFIRE_LSU_PWW 0x00800000
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#define SPITFIRE_LSU_PWW 0x00800000
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#define SPITFIRE_LSU_VWR 0x00400000
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#define SPITFIRE_LSU_VWR 0x00400000
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#define SPITFIRE_LSU_VWW 0x00200000
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#define SPITFIRE_LSU_VWW 0x00200000
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#define SPITFIRE_LSU_PMASK 0x000ffff0
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#define SPITFIRE_LSU_PMASK 0x000ffff0
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#define SPITFIRE_LSU_DME 0x00000008
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#define SPITFIRE_LSU_DME 0x00000008
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#define SPITFIRE_LSU_IME 0x00000004
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#define SPITFIRE_LSU_IME 0x00000004
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#define SPITFIRE_LSU_DCE 0x00000002
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#define SPITFIRE_LSU_DCE 0x00000002
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#define SPITFIRE_LSU_ICE 0x00000001
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#define SPITFIRE_LSU_ICE 0x00000001
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#endif /* !(_SPARC_ULTRA_H) */
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#endif /* !(_SPARC_ULTRA_H) */
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