/* $Id: scc.h,v 1.1 2005-12-20 11:32:26 jcastillo Exp $ */
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/* $Id: scc.h,v 1.1 2005-12-20 11:32:26 jcastillo Exp $ */
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#ifndef _SCC_H
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#ifndef _SCC_H
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#define _SCC_H
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#define _SCC_H
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#include <linux/if_ether.h>
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#include <linux/if_ether.h>
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/* selection of hardware types */
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/* selection of hardware types */
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#define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */
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#define PA0HZP 0x00 /* hardware type for PA0HZP SCC card and compatible */
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#define EAGLE 0x01 /* hardware type for EAGLE card */
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#define EAGLE 0x01 /* hardware type for EAGLE card */
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#define PC100 0x02 /* hardware type for PC100 card */
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#define PC100 0x02 /* hardware type for PC100 card */
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#define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
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#define PRIMUS 0x04 /* hardware type for PRIMUS-PC (DG9BL) card */
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#define DRSI 0x08 /* hardware type for DRSI PC*Packet card */
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#define DRSI 0x08 /* hardware type for DRSI PC*Packet card */
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#define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */
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#define BAYCOM 0x10 /* hardware type for BayCom (U)SCC */
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/* Paranoia check... */
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/* Paranoia check... */
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#define SCC_PARANOIA_CHECK /* tell the user if something is going wrong */
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#define SCC_PARANOIA_CHECK /* tell the user if something is going wrong */
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/* TTY ioctl() commands */
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/* TTY ioctl() commands */
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#define TIOCSCCCFG _IOW('Z', 0, sizeof(struct scc_hw_config)) /* set hardware parameters */
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#define TIOCSCCCFG _IOW('Z', 0, sizeof(struct scc_hw_config)) /* set hardware parameters */
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#define TIOCSCCINI _IO('Z', 1) /* init driver */
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#define TIOCSCCINI _IO('Z', 1) /* init driver */
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#define TIOCSCCCHANINI _IOW('Z', 2, sizeof(struct scc_modem)) /* init channel */
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#define TIOCSCCCHANINI _IOW('Z', 2, sizeof(struct scc_modem)) /* init channel */
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#define TIOCSCCSMEM _IOW('Z', 3, sizeof(struct scc_mem_config)) /* adjust buffer pools */
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#define TIOCSCCSMEM _IOW('Z', 3, sizeof(struct scc_mem_config)) /* adjust buffer pools */
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#define TIOCSCCGKISS _IOWR('Z', 4, sizeof(struct scc_kiss_cmd)) /* get kiss parameter */
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#define TIOCSCCGKISS _IOWR('Z', 4, sizeof(struct scc_kiss_cmd)) /* get kiss parameter */
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#define TIOCSCCSKISS _IOW('Z', 5, sizeof(struct scc_kiss_cmd)) /* set kiss parameter */
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#define TIOCSCCSKISS _IOW('Z', 5, sizeof(struct scc_kiss_cmd)) /* set kiss parameter */
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#define TIOCSCCGSTAT _IOR('Z', 6, sizeof(struct scc_stat)) /* get scc status */
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#define TIOCSCCGSTAT _IOR('Z', 6, sizeof(struct scc_stat)) /* get scc status */
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/* old TTY ioctl() commands */
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/* old TTY ioctl() commands */
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#define TIOCSCCCFG_OLD 0x2200
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#define TIOCSCCCFG_OLD 0x2200
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#define TIOCSCCINI_OLD 0x2201
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#define TIOCSCCINI_OLD 0x2201
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#define TIOCCHANINI_OLD 0x2202
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#define TIOCCHANINI_OLD 0x2202
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#define TIOCCHANMEM_OLD 0x2210
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#define TIOCCHANMEM_OLD 0x2210
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#define TIOCSKISS_OLD 0x2282
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#define TIOCSKISS_OLD 0x2282
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#define TIOCGKISS_OLD 0x2283
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#define TIOCGKISS_OLD 0x2283
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#define TIOCSCCSTAT_OLD 0x2284
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#define TIOCSCCSTAT_OLD 0x2284
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/* DEV ioctl() commands */
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/* DEV ioctl() commands */
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enum SCC_IOCTL_CMD {
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enum SCC_IOCTL_CMD {
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SIOCSCCRESERVED=SIOCDEVPRIVATE,
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SIOCSCCRESERVED=SIOCDEVPRIVATE,
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SIOCSCCCFG,
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SIOCSCCCFG,
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SIOCSCCINI,
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SIOCSCCINI,
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SIOCSCCCHANINI,
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SIOCSCCCHANINI,
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SIOCSCCSMEM,
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SIOCSCCSMEM,
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SIOCSCCGKISS,
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SIOCSCCGKISS,
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SIOCSCCSKISS,
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SIOCSCCSKISS,
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SIOCSCCGSTAT
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SIOCSCCGSTAT
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};
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};
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/* magic number */
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/* magic number */
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#define SCC_MAGIC 0x8530 /* ;-) */
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#define SCC_MAGIC 0x8530 /* ;-) */
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/* KISS protocol flags */
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/* KISS protocol flags */
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#define FEND 192
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#define FEND 192
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#define FESC 219
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#define FESC 219
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#define TFEND 220
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#define TFEND 220
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#define TFESC 221
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#define TFESC 221
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/* KISS state machine */
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/* KISS state machine */
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enum SCC_KISS_STATES {
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enum SCC_KISS_STATES {
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KISS_IDLE,
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KISS_IDLE,
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KISS_DATA,
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KISS_DATA,
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KISS_ESCAPE,
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KISS_ESCAPE,
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KISS_RXFRAME
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KISS_RXFRAME
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};
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};
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/* Device parameter control (from WAMPES) */
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/* Device parameter control (from WAMPES) */
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enum SCC_KISS_PARAMS {
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enum SCC_KISS_PARAMS {
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PARAM_TXDELAY=1,
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PARAM_TXDELAY=1,
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PARAM_PERSIST,
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PARAM_PERSIST,
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PARAM_SLOTTIME,
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PARAM_SLOTTIME,
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PARAM_TXTAIL,
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PARAM_TXTAIL,
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PARAM_FULLDUP,
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PARAM_FULLDUP,
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PARAM_SOFTDCD, /* was: PARAM_HW */
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PARAM_SOFTDCD, /* was: PARAM_HW */
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PARAM_MUTE, /* ??? */
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PARAM_MUTE, /* ??? */
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PARAM_DTR,
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PARAM_DTR,
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PARAM_RTS,
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PARAM_RTS,
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PARAM_SPEED,
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PARAM_SPEED,
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PARAM_ENDDELAY, /* ??? */
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PARAM_ENDDELAY, /* ??? */
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PARAM_GROUP,
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PARAM_GROUP,
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PARAM_IDLE,
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PARAM_IDLE,
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PARAM_MIN,
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PARAM_MIN,
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PARAM_MAXKEY,
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PARAM_MAXKEY,
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PARAM_WAIT,
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PARAM_WAIT,
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PARAM_MAXDEFER,
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PARAM_MAXDEFER,
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PARAM_TX,
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PARAM_TX,
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PARAM_HWEVENT=31,
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PARAM_HWEVENT=31,
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PARAM_RETURN=255 /* reset kiss mode */
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PARAM_RETURN=255 /* reset kiss mode */
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};
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};
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/* fulldup parameter */
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/* fulldup parameter */
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enum SCC_KISS_DUPLEX_MODES {
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enum SCC_KISS_DUPLEX_MODES {
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KISS_DUPLEX_HALF, /* normal CSMA operation */
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KISS_DUPLEX_HALF, /* normal CSMA operation */
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KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */
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KISS_DUPLEX_FULL, /* fullduplex, key down trx after transmission */
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KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */
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KISS_DUPLEX_LINK, /* fullduplex, key down trx after 'idletime' sec */
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KISS_DUPLEX_OPTIMA, /* fullduplex, let the protocol layer control the hw */
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KISS_DUPLEX_OPTIMA, /* fullduplex, let the protocol layer control the hw */
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};
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};
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/* misc. parameters */
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/* misc. parameters */
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#define TIMER_OFF 65535U /* to switch off timers */
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#define TIMER_OFF 65535U /* to switch off timers */
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#define NO_SUCH_PARAM 65534U /* param not implemented */
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#define NO_SUCH_PARAM 65534U /* param not implemented */
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/* HWEVENT parameter */
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/* HWEVENT parameter */
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enum SCC_HWEV_PARAMETERS {
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enum SCC_HWEV_PARAMETERS {
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HWEV_DCD_ON,
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HWEV_DCD_ON,
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HWEV_DCD_OFF,
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HWEV_DCD_OFF,
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HWEV_ALL_SENT
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HWEV_ALL_SENT
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};
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};
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/* channel grouping */
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/* channel grouping */
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#define RXGROUP 0x100 /* if set, only tx when all channels clear */
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#define RXGROUP 0x100 /* if set, only tx when all channels clear */
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#define TXGROUP 0x200 /* if set, don't transmit simultaneously */
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#define TXGROUP 0x200 /* if set, don't transmit simultaneously */
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/* Tx/Rx clock sources */
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/* Tx/Rx clock sources */
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enum SCC_CLK_SOURCES {
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enum SCC_CLK_SOURCES {
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CLK_DPLL, /* normal halfduplex operation */
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CLK_DPLL, /* normal halfduplex operation */
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CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */
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CLK_EXTERNAL, /* external clocking (G3RUH/DF9IC modems) */
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CLK_DIVIDER /* Rx = DPLL, Tx = divider (fullduplex with */
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CLK_DIVIDER /* Rx = DPLL, Tx = divider (fullduplex with */
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/* modems without clock regeneration */
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/* modems without clock regeneration */
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};
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};
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/* Tx state */
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/* Tx state */
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enum SCC_TX_STATES {
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enum SCC_TX_STATES {
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TXS_IDLE, /* Transmitter off, no data pending */
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TXS_IDLE, /* Transmitter off, no data pending */
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TXS_BUSY, /* waiting for permission to send / tailtime */
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TXS_BUSY, /* waiting for permission to send / tailtime */
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TXS_ACTIVE, /* Transmitter on, sending data */
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TXS_ACTIVE, /* Transmitter on, sending data */
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TXS_NEWFRAME, /* reset CRC and send (next) frame */
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TXS_NEWFRAME, /* reset CRC and send (next) frame */
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TXS_IDLE2, /* Transmitter on, no data pending */
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TXS_IDLE2, /* Transmitter on, no data pending */
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TXS_WAIT, /* Waiting for Mintime to expire */
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TXS_WAIT, /* Waiting for Mintime to expire */
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TXS_TIMEOUT /* We had a transmission timeout */
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TXS_TIMEOUT /* We had a transmission timeout */
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};
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};
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enum SCC_TX_KEY {TX_OFF, TX_ON}; /* command for scc_key_trx() */
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enum SCC_TX_KEY {TX_OFF, TX_ON}; /* command for scc_key_trx() */
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/* Buffer management */
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/* Buffer management */
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#define BT_RECEIVE 1 /* buffer allocated by receive */
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#define BT_RECEIVE 1 /* buffer allocated by receive */
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#define BT_TRANSMIT 2 /* buffer allocated by transmit */
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#define BT_TRANSMIT 2 /* buffer allocated by transmit */
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#define NULLBUF (struct mbuf *)0
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#define NULLBUF (struct mbuf *)0
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#define NULLBUFP (struct mbuf **)0
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#define NULLBUFP (struct mbuf **)0
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typedef unsigned short io_port; /* type definition for an 'io port address' */
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typedef unsigned short io_port; /* type definition for an 'io port address' */
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typedef unsigned short ioaddr; /* old def */
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typedef unsigned short ioaddr; /* old def */
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#ifdef SCC_DELAY
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#ifdef SCC_DELAY
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#define Inb(port) inb_p(port)
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#define Inb(port) inb_p(port)
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#define Outb(port, val) outb_p(val, port)
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#define Outb(port, val) outb_p(val, port)
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#else
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#else
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#define Inb(port) inb(port)
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#define Inb(port) inb(port)
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#define Outb(port, val) outb(val, port)
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#define Outb(port, val) outb(val, port)
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#endif
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#endif
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#define TIMER_OFF 65535U
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#define TIMER_OFF 65535U
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/* Basic message buffer structure */
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/* Basic message buffer structure */
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struct mbuf {
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struct mbuf {
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struct mbuf *next; /* Link to next buffer */
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struct mbuf *next; /* Link to next buffer */
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struct mbuf *prev; /* Link to previous buffer */
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struct mbuf *prev; /* Link to previous buffer */
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int cnt; /* Number of bytes stored in buffer */
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int cnt; /* Number of bytes stored in buffer */
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unsigned char *rw_ptr; /* read-write pointer */
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unsigned char *rw_ptr; /* read-write pointer */
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unsigned char data[0]; /* anchor for allocated buffer */
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unsigned char data[0]; /* anchor for allocated buffer */
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};
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};
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/* SCC channel control structure for KISS */
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/* SCC channel control structure for KISS */
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struct scc_kiss {
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struct scc_kiss {
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unsigned char txdelay; /* Transmit Delay 10 ms/cnt */
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unsigned char txdelay; /* Transmit Delay 10 ms/cnt */
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unsigned char persist; /* Persistence (0-255) as a % */
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unsigned char persist; /* Persistence (0-255) as a % */
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unsigned char slottime; /* Delay to wait on persistence hit */
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unsigned char slottime; /* Delay to wait on persistence hit */
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unsigned char tailtime; /* Delay after last byte written */
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unsigned char tailtime; /* Delay after last byte written */
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unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
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unsigned char fulldup; /* Full Duplex mode 0=CSMA 1=DUP 2=ALWAYS KEYED */
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unsigned char waittime; /* Waittime before any transmit attempt */
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unsigned char waittime; /* Waittime before any transmit attempt */
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unsigned int maxkeyup; /* Maximum time to transmit (seconds) */
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unsigned int maxkeyup; /* Maximum time to transmit (seconds) */
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unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */
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unsigned char mintime; /* Minimal offtime after MAXKEYUP timeout (seconds) */
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unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */
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unsigned int idletime; /* Maximum idle time in ALWAYS KEYED mode (seconds) */
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unsigned int maxdefer; /* Timer for CSMA channel busy limit */
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unsigned int maxdefer; /* Timer for CSMA channel busy limit */
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unsigned char tx_inhibit; /* Transmit is not allowed when set */
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unsigned char tx_inhibit; /* Transmit is not allowed when set */
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unsigned char group; /* Group ID for AX.25 TX interlocking */
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unsigned char group; /* Group ID for AX.25 TX interlocking */
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unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */
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unsigned char mode; /* 'normal' or 'hwctrl' mode (unused) */
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unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */
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unsigned char softdcd; /* Use DPLL instead of DCD pin for carrier detect */
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};
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};
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/* SCC statistical information */
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/* SCC statistical information */
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struct scc_stat {
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struct scc_stat {
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long rxints; /* Receiver interrupts */
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long rxints; /* Receiver interrupts */
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long txints; /* Transmitter interrupts */
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long txints; /* Transmitter interrupts */
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long exints; /* External/status interrupts */
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long exints; /* External/status interrupts */
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long spints; /* Special receiver interrupts */
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long spints; /* Special receiver interrupts */
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long txframes; /* Packets sent */
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long txframes; /* Packets sent */
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long rxframes; /* Number of Frames Actually Received */
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long rxframes; /* Number of Frames Actually Received */
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long rxerrs; /* CRC Errors */
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long rxerrs; /* CRC Errors */
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long txerrs; /* KISS errors */
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long txerrs; /* KISS errors */
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unsigned int nospace; /* "Out of buffers" */
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unsigned int nospace; /* "Out of buffers" */
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unsigned int rx_over; /* Receiver Overruns */
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unsigned int rx_over; /* Receiver Overruns */
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unsigned int tx_under; /* Transmitter Underruns */
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unsigned int tx_under; /* Transmitter Underruns */
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unsigned int tx_state; /* Transmitter state */
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unsigned int tx_state; /* Transmitter state */
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char tx_kiss_state; /* state of the kiss interpreter */
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char tx_kiss_state; /* state of the kiss interpreter */
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char rx_kiss_state; /* state of the kiss encoder */
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char rx_kiss_state; /* state of the kiss encoder */
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int tx_queued; /* tx frames enqueued */
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int tx_queued; /* tx frames enqueued */
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int rx_queued; /* rx frames enqueued */
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int rx_queued; /* rx frames enqueued */
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unsigned int rxbuffers; /* allocated rx_buffers */
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unsigned int rxbuffers; /* allocated rx_buffers */
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unsigned int txbuffers; /* allocated tx_buffers */
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unsigned int txbuffers; /* allocated tx_buffers */
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unsigned int bufsize; /* used buffersize */
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unsigned int bufsize; /* used buffersize */
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unsigned char is_netdev;/* If set: act as network instead of character device */
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unsigned char is_netdev;/* If set: act as network instead of character device */
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};
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};
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struct scc_modem {
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struct scc_modem {
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long speed; /* Line speed, bps */
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long speed; /* Line speed, bps */
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char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
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char clocksrc; /* 0 = DPLL, 1 = external, 2 = divider */
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char nrz; /* NRZ instead of NRZI */
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char nrz; /* NRZ instead of NRZI */
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};
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};
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struct scc_kiss_cmd {
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struct scc_kiss_cmd {
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int command; /* one of the KISS-Commands defined above */
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int command; /* one of the KISS-Commands defined above */
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unsigned param; /* KISS-Param */
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unsigned param; /* KISS-Param */
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};
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};
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struct scc_hw_config {
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struct scc_hw_config {
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io_port data_a; /* data port channel A */
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io_port data_a; /* data port channel A */
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io_port ctrl_a; /* control port channel A */
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io_port ctrl_a; /* control port channel A */
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io_port data_b; /* data port channel B */
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io_port data_b; /* data port channel B */
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io_port ctrl_b; /* control port channel B */
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io_port ctrl_b; /* control port channel B */
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io_port vector_latch; /* INTACK-Latch (#) */
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io_port vector_latch; /* INTACK-Latch (#) */
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io_port special; /* special function port */
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io_port special; /* special function port */
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int irq; /* irq */
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int irq; /* irq */
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long clock; /* clock */
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long clock; /* clock */
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char option; /* command for function port */
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char option; /* command for function port */
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char brand; /* hardware type */
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char brand; /* hardware type */
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char escc; /* use ext. features of a 8580/85180/85280 */
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char escc; /* use ext. features of a 8580/85180/85280 */
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};
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};
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/* (#) only one INTACK latch allowed. */
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/* (#) only one INTACK latch allowed. */
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struct scc_mem_config {
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struct scc_mem_config {
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unsigned int rxbuffers;
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unsigned int rxbuffers;
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unsigned int txbuffers;
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unsigned int txbuffers;
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unsigned int bufsize;
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unsigned int bufsize;
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};
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};
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/* SCC channel structure */
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/* SCC channel structure */
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struct scc_channel {
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struct scc_channel {
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int magic; /* magic word */
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int magic; /* magic word */
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int init; /* channel exists? */
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int init; /* channel exists? */
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struct tty_struct *tty; /* link to tty control structure */
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struct tty_struct *tty; /* link to tty control structure */
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char tty_opened; /* No. of open() calls... */
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char tty_opened; /* No. of open() calls... */
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char throttled; /* driver is throttled */
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char throttled; /* driver is throttled */
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struct device *dev; /* link to device control structure */
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struct device *dev; /* link to device control structure */
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struct enet_statistics dev_stat;
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struct enet_statistics dev_stat;
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/* device statistics */
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/* device statistics */
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char brand; /* manufacturer of the board */
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char brand; /* manufacturer of the board */
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long clock; /* used clock */
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long clock; /* used clock */
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io_port ctrl; /* I/O address of CONTROL register */
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io_port ctrl; /* I/O address of CONTROL register */
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io_port data; /* I/O address of DATA register */
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io_port data; /* I/O address of DATA register */
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io_port special; /* I/O address of special function port */
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io_port special; /* I/O address of special function port */
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int irq; /* Number of Interrupt */
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int irq; /* Number of Interrupt */
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char option;
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char option;
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char enhanced; /* Enhanced SCC support */
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char enhanced; /* Enhanced SCC support */
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unsigned char wreg[16]; /* Copy of last written value in WRx */
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unsigned char wreg[16]; /* Copy of last written value in WRx */
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unsigned char status; /* Copy of R0 at last external interrupt */
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unsigned char status; /* Copy of R0 at last external interrupt */
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struct scc_kiss kiss; /* control structure for KISS params */
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struct scc_kiss kiss; /* control structure for KISS params */
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struct scc_stat stat; /* statistical information */
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struct scc_stat stat; /* statistical information */
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struct scc_modem modem; /* modem information */
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struct scc_modem modem; /* modem information */
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char mempool; /* pool empty or allocated? */
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char mempool; /* pool empty or allocated? */
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struct mbuf *rx_buffer_pool; /* free buffers for rx/tx frames are */
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struct mbuf *rx_buffer_pool; /* free buffers for rx/tx frames are */
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struct mbuf *tx_buffer_pool; /* linked in these ring chains */
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struct mbuf *tx_buffer_pool; /* linked in these ring chains */
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struct mbuf *rx_queue; /* chain of received frames */
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struct mbuf *rx_queue; /* chain of received frames */
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struct mbuf *tx_queue; /* chain of frames due to transmit */
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struct mbuf *tx_queue; /* chain of frames due to transmit */
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struct mbuf *rx_bp; /* pointer to frame currently received */
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struct mbuf *rx_bp; /* pointer to frame currently received */
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struct mbuf *tx_bp; /* pointer to frame currently transmitted */
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struct mbuf *tx_bp; /* pointer to frame currently transmitted */
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struct mbuf *kiss_decode_bp; /* frame we are receiving from tty */
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struct mbuf *kiss_decode_bp; /* frame we are receiving from tty */
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struct mbuf *kiss_encode_bp; /* frame we are sending to tty */
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struct mbuf *kiss_encode_bp; /* frame we are sending to tty */
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|
/* Timer */
|
/* Timer */
|
|
|
struct timer_list tx_t; /* tx timer for this channel */
|
struct timer_list tx_t; /* tx timer for this channel */
|
struct timer_list tx_wdog;
|
struct timer_list tx_wdog;
|
/* tx watchdogs */
|
/* tx watchdogs */
|
struct timer_list rx_t; /* rx timer */
|
struct timer_list rx_t; /* rx timer */
|
};
|
};
|
|
|
|
|
/* 8530 Serial Communications Controller Register definitions */
|
/* 8530 Serial Communications Controller Register definitions */
|
#define FLAG 0x7e
|
#define FLAG 0x7e
|
|
|
/* Write Register 0 */
|
/* Write Register 0 */
|
#define R0 0 /* Register selects */
|
#define R0 0 /* Register selects */
|
#define R1 1
|
#define R1 1
|
#define R2 2
|
#define R2 2
|
#define R3 3
|
#define R3 3
|
#define R4 4
|
#define R4 4
|
#define R5 5
|
#define R5 5
|
#define R6 6
|
#define R6 6
|
#define R7 7
|
#define R7 7
|
#define R8 8
|
#define R8 8
|
#define R9 9
|
#define R9 9
|
#define R10 10
|
#define R10 10
|
#define R11 11
|
#define R11 11
|
#define R12 12
|
#define R12 12
|
#define R13 13
|
#define R13 13
|
#define R14 14
|
#define R14 14
|
#define R15 15
|
#define R15 15
|
|
|
#define NULLCODE 0 /* Null Code */
|
#define NULLCODE 0 /* Null Code */
|
#define POINT_HIGH 0x8 /* Select upper half of registers */
|
#define POINT_HIGH 0x8 /* Select upper half of registers */
|
#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
|
#define RES_EXT_INT 0x10 /* Reset Ext. Status Interrupts */
|
#define SEND_ABORT 0x18 /* HDLC Abort */
|
#define SEND_ABORT 0x18 /* HDLC Abort */
|
#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
|
#define RES_RxINT_FC 0x20 /* Reset RxINT on First Character */
|
#define RES_Tx_P 0x28 /* Reset TxINT Pending */
|
#define RES_Tx_P 0x28 /* Reset TxINT Pending */
|
#define ERR_RES 0x30 /* Error Reset */
|
#define ERR_RES 0x30 /* Error Reset */
|
#define RES_H_IUS 0x38 /* Reset highest IUS */
|
#define RES_H_IUS 0x38 /* Reset highest IUS */
|
|
|
#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
|
#define RES_Rx_CRC 0x40 /* Reset Rx CRC Checker */
|
#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
|
#define RES_Tx_CRC 0x80 /* Reset Tx CRC Checker */
|
#define RES_EOM_L 0xC0 /* Reset EOM latch */
|
#define RES_EOM_L 0xC0 /* Reset EOM latch */
|
|
|
/* Write Register 1 */
|
/* Write Register 1 */
|
|
|
#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
|
#define EXT_INT_ENAB 0x1 /* Ext Int Enable */
|
#define TxINT_ENAB 0x2 /* Tx Int Enable */
|
#define TxINT_ENAB 0x2 /* Tx Int Enable */
|
#define PAR_SPEC 0x4 /* Parity is special condition */
|
#define PAR_SPEC 0x4 /* Parity is special condition */
|
|
|
#define RxINT_DISAB 0 /* Rx Int Disable */
|
#define RxINT_DISAB 0 /* Rx Int Disable */
|
#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
|
#define RxINT_FCERR 0x8 /* Rx Int on First Character Only or Error */
|
#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
|
#define INT_ALL_Rx 0x10 /* Int on all Rx Characters or error */
|
#define INT_ERR_Rx 0x18 /* Int on error only */
|
#define INT_ERR_Rx 0x18 /* Int on error only */
|
|
|
#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
|
#define WT_RDY_RT 0x20 /* Wait/Ready on R/T */
|
#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
|
#define WT_FN_RDYFN 0x40 /* Wait/FN/Ready FN */
|
#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
|
#define WT_RDY_ENAB 0x80 /* Wait/Ready Enable */
|
|
|
/* Write Register 2 (Interrupt Vector) */
|
/* Write Register 2 (Interrupt Vector) */
|
|
|
/* Write Register 3 */
|
/* Write Register 3 */
|
|
|
#define RxENABLE 0x1 /* Rx Enable */
|
#define RxENABLE 0x1 /* Rx Enable */
|
#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
|
#define SYNC_L_INH 0x2 /* Sync Character Load Inhibit */
|
#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
|
#define ADD_SM 0x4 /* Address Search Mode (SDLC) */
|
#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
|
#define RxCRC_ENAB 0x8 /* Rx CRC Enable */
|
#define ENT_HM 0x10 /* Enter Hunt Mode */
|
#define ENT_HM 0x10 /* Enter Hunt Mode */
|
#define AUTO_ENAB 0x20 /* Auto Enables */
|
#define AUTO_ENAB 0x20 /* Auto Enables */
|
#define Rx5 0x0 /* Rx 5 Bits/Character */
|
#define Rx5 0x0 /* Rx 5 Bits/Character */
|
#define Rx7 0x40 /* Rx 7 Bits/Character */
|
#define Rx7 0x40 /* Rx 7 Bits/Character */
|
#define Rx6 0x80 /* Rx 6 Bits/Character */
|
#define Rx6 0x80 /* Rx 6 Bits/Character */
|
#define Rx8 0xc0 /* Rx 8 Bits/Character */
|
#define Rx8 0xc0 /* Rx 8 Bits/Character */
|
|
|
/* Write Register 4 */
|
/* Write Register 4 */
|
|
|
#define PAR_ENA 0x1 /* Parity Enable */
|
#define PAR_ENA 0x1 /* Parity Enable */
|
#define PAR_EVEN 0x2 /* Parity Even/Odd* */
|
#define PAR_EVEN 0x2 /* Parity Even/Odd* */
|
|
|
#define SYNC_ENAB 0 /* Sync Modes Enable */
|
#define SYNC_ENAB 0 /* Sync Modes Enable */
|
#define SB1 0x4 /* 1 stop bit/char */
|
#define SB1 0x4 /* 1 stop bit/char */
|
#define SB15 0x8 /* 1.5 stop bits/char */
|
#define SB15 0x8 /* 1.5 stop bits/char */
|
#define SB2 0xc /* 2 stop bits/char */
|
#define SB2 0xc /* 2 stop bits/char */
|
|
|
#define MONSYNC 0 /* 8 Bit Sync character */
|
#define MONSYNC 0 /* 8 Bit Sync character */
|
#define BISYNC 0x10 /* 16 bit sync character */
|
#define BISYNC 0x10 /* 16 bit sync character */
|
#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
|
#define SDLC 0x20 /* SDLC Mode (01111110 Sync Flag) */
|
#define EXTSYNC 0x30 /* External Sync Mode */
|
#define EXTSYNC 0x30 /* External Sync Mode */
|
|
|
#define X1CLK 0x0 /* x1 clock mode */
|
#define X1CLK 0x0 /* x1 clock mode */
|
#define X16CLK 0x40 /* x16 clock mode */
|
#define X16CLK 0x40 /* x16 clock mode */
|
#define X32CLK 0x80 /* x32 clock mode */
|
#define X32CLK 0x80 /* x32 clock mode */
|
#define X64CLK 0xC0 /* x64 clock mode */
|
#define X64CLK 0xC0 /* x64 clock mode */
|
|
|
/* Write Register 5 */
|
/* Write Register 5 */
|
|
|
#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
|
#define TxCRC_ENAB 0x1 /* Tx CRC Enable */
|
#define RTS 0x2 /* RTS */
|
#define RTS 0x2 /* RTS */
|
#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
|
#define SDLC_CRC 0x4 /* SDLC/CRC-16 */
|
#define TxENAB 0x8 /* Tx Enable */
|
#define TxENAB 0x8 /* Tx Enable */
|
#define SND_BRK 0x10 /* Send Break */
|
#define SND_BRK 0x10 /* Send Break */
|
#define Tx5 0x0 /* Tx 5 bits (or less)/character */
|
#define Tx5 0x0 /* Tx 5 bits (or less)/character */
|
#define Tx7 0x20 /* Tx 7 bits/character */
|
#define Tx7 0x20 /* Tx 7 bits/character */
|
#define Tx6 0x40 /* Tx 6 bits/character */
|
#define Tx6 0x40 /* Tx 6 bits/character */
|
#define Tx8 0x60 /* Tx 8 bits/character */
|
#define Tx8 0x60 /* Tx 8 bits/character */
|
#define DTR 0x80 /* DTR */
|
#define DTR 0x80 /* DTR */
|
|
|
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
|
/* Write Register 6 (Sync bits 0-7/SDLC Address Field) */
|
|
|
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
|
/* Write Register 7 (Sync bits 8-15/SDLC 01111110) */
|
|
|
/* Write Register 8 (transmit buffer) */
|
/* Write Register 8 (transmit buffer) */
|
|
|
/* Write Register 9 (Master interrupt control) */
|
/* Write Register 9 (Master interrupt control) */
|
#define VIS 1 /* Vector Includes Status */
|
#define VIS 1 /* Vector Includes Status */
|
#define NV 2 /* No Vector */
|
#define NV 2 /* No Vector */
|
#define DLC 4 /* Disable Lower Chain */
|
#define DLC 4 /* Disable Lower Chain */
|
#define MIE 8 /* Master Interrupt Enable */
|
#define MIE 8 /* Master Interrupt Enable */
|
#define STATHI 0x10 /* Status high */
|
#define STATHI 0x10 /* Status high */
|
#define NORESET 0 /* No reset on write to R9 */
|
#define NORESET 0 /* No reset on write to R9 */
|
#define CHRB 0x40 /* Reset channel B */
|
#define CHRB 0x40 /* Reset channel B */
|
#define CHRA 0x80 /* Reset channel A */
|
#define CHRA 0x80 /* Reset channel A */
|
#define FHWRES 0xc0 /* Force hardware reset */
|
#define FHWRES 0xc0 /* Force hardware reset */
|
|
|
/* Write Register 10 (misc control bits) */
|
/* Write Register 10 (misc control bits) */
|
#define BIT6 1 /* 6 bit/8bit sync */
|
#define BIT6 1 /* 6 bit/8bit sync */
|
#define LOOPMODE 2 /* SDLC Loop mode */
|
#define LOOPMODE 2 /* SDLC Loop mode */
|
#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
|
#define ABUNDER 4 /* Abort/flag on SDLC xmit underrun */
|
#define MARKIDLE 8 /* Mark/flag on idle */
|
#define MARKIDLE 8 /* Mark/flag on idle */
|
#define GAOP 0x10 /* Go active on poll */
|
#define GAOP 0x10 /* Go active on poll */
|
#define NRZ 0 /* NRZ mode */
|
#define NRZ 0 /* NRZ mode */
|
#define NRZI 0x20 /* NRZI mode */
|
#define NRZI 0x20 /* NRZI mode */
|
#define FM1 0x40 /* FM1 (transition = 1) */
|
#define FM1 0x40 /* FM1 (transition = 1) */
|
#define FM0 0x60 /* FM0 (transition = 0) */
|
#define FM0 0x60 /* FM0 (transition = 0) */
|
#define CRCPS 0x80 /* CRC Preset I/O */
|
#define CRCPS 0x80 /* CRC Preset I/O */
|
|
|
/* Write Register 11 (Clock Mode control) */
|
/* Write Register 11 (Clock Mode control) */
|
#define TRxCXT 0 /* TRxC = Xtal output */
|
#define TRxCXT 0 /* TRxC = Xtal output */
|
#define TRxCTC 1 /* TRxC = Transmit clock */
|
#define TRxCTC 1 /* TRxC = Transmit clock */
|
#define TRxCBR 2 /* TRxC = BR Generator Output */
|
#define TRxCBR 2 /* TRxC = BR Generator Output */
|
#define TRxCDP 3 /* TRxC = DPLL output */
|
#define TRxCDP 3 /* TRxC = DPLL output */
|
#define TRxCOI 4 /* TRxC O/I */
|
#define TRxCOI 4 /* TRxC O/I */
|
#define TCRTxCP 0 /* Transmit clock = RTxC pin */
|
#define TCRTxCP 0 /* Transmit clock = RTxC pin */
|
#define TCTRxCP 8 /* Transmit clock = TRxC pin */
|
#define TCTRxCP 8 /* Transmit clock = TRxC pin */
|
#define TCBR 0x10 /* Transmit clock = BR Generator output */
|
#define TCBR 0x10 /* Transmit clock = BR Generator output */
|
#define TCDPLL 0x18 /* Transmit clock = DPLL output */
|
#define TCDPLL 0x18 /* Transmit clock = DPLL output */
|
#define RCRTxCP 0 /* Receive clock = RTxC pin */
|
#define RCRTxCP 0 /* Receive clock = RTxC pin */
|
#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
|
#define RCTRxCP 0x20 /* Receive clock = TRxC pin */
|
#define RCBR 0x40 /* Receive clock = BR Generator output */
|
#define RCBR 0x40 /* Receive clock = BR Generator output */
|
#define RCDPLL 0x60 /* Receive clock = DPLL output */
|
#define RCDPLL 0x60 /* Receive clock = DPLL output */
|
#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
|
#define RTxCX 0x80 /* RTxC Xtal/No Xtal */
|
|
|
/* Write Register 12 (lower byte of baud rate generator time constant) */
|
/* Write Register 12 (lower byte of baud rate generator time constant) */
|
|
|
/* Write Register 13 (upper byte of baud rate generator time constant) */
|
/* Write Register 13 (upper byte of baud rate generator time constant) */
|
|
|
/* Write Register 14 (Misc control bits) */
|
/* Write Register 14 (Misc control bits) */
|
#define BRENABL 1 /* Baud rate generator enable */
|
#define BRENABL 1 /* Baud rate generator enable */
|
#define BRSRC 2 /* Baud rate generator source */
|
#define BRSRC 2 /* Baud rate generator source */
|
#define DTRREQ 4 /* DTR/Request function */
|
#define DTRREQ 4 /* DTR/Request function */
|
#define AUTOECHO 8 /* Auto Echo */
|
#define AUTOECHO 8 /* Auto Echo */
|
#define LOOPBAK 0x10 /* Local loopback */
|
#define LOOPBAK 0x10 /* Local loopback */
|
#define SEARCH 0x20 /* Enter search mode */
|
#define SEARCH 0x20 /* Enter search mode */
|
#define RMC 0x40 /* Reset missing clock */
|
#define RMC 0x40 /* Reset missing clock */
|
#define DISDPLL 0x60 /* Disable DPLL */
|
#define DISDPLL 0x60 /* Disable DPLL */
|
#define SSBR 0x80 /* Set DPLL source = BR generator */
|
#define SSBR 0x80 /* Set DPLL source = BR generator */
|
#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
|
#define SSRTxC 0xa0 /* Set DPLL source = RTxC */
|
#define SFMM 0xc0 /* Set FM mode */
|
#define SFMM 0xc0 /* Set FM mode */
|
#define SNRZI 0xe0 /* Set NRZI mode */
|
#define SNRZI 0xe0 /* Set NRZI mode */
|
|
|
/* Write Register 15 (external/status interrupt control) */
|
/* Write Register 15 (external/status interrupt control) */
|
#define ZCIE 2 /* Zero count IE */
|
#define ZCIE 2 /* Zero count IE */
|
#define DCDIE 8 /* DCD IE */
|
#define DCDIE 8 /* DCD IE */
|
#define SYNCIE 0x10 /* Sync/hunt IE */
|
#define SYNCIE 0x10 /* Sync/hunt IE */
|
#define CTSIE 0x20 /* CTS IE */
|
#define CTSIE 0x20 /* CTS IE */
|
#define TxUIE 0x40 /* Tx Underrun/EOM IE */
|
#define TxUIE 0x40 /* Tx Underrun/EOM IE */
|
#define BRKIE 0x80 /* Break/Abort IE */
|
#define BRKIE 0x80 /* Break/Abort IE */
|
|
|
|
|
/* Read Register 0 */
|
/* Read Register 0 */
|
#define Rx_CH_AV 0x1 /* Rx Character Available */
|
#define Rx_CH_AV 0x1 /* Rx Character Available */
|
#define ZCOUNT 0x2 /* Zero count */
|
#define ZCOUNT 0x2 /* Zero count */
|
#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
|
#define Tx_BUF_EMP 0x4 /* Tx Buffer empty */
|
#define DCD 0x8 /* DCD */
|
#define DCD 0x8 /* DCD */
|
#define SYNC_HUNT 0x10 /* Sync/hunt */
|
#define SYNC_HUNT 0x10 /* Sync/hunt */
|
#define CTS 0x20 /* CTS */
|
#define CTS 0x20 /* CTS */
|
#define TxEOM 0x40 /* Tx underrun */
|
#define TxEOM 0x40 /* Tx underrun */
|
#define BRK_ABRT 0x80 /* Break/Abort */
|
#define BRK_ABRT 0x80 /* Break/Abort */
|
|
|
/* Read Register 1 */
|
/* Read Register 1 */
|
#define ALL_SNT 0x1 /* All sent */
|
#define ALL_SNT 0x1 /* All sent */
|
/* Residue Data for 8 Rx bits/char programmed */
|
/* Residue Data for 8 Rx bits/char programmed */
|
#define RES3 0x8 /* 0/3 */
|
#define RES3 0x8 /* 0/3 */
|
#define RES4 0x4 /* 0/4 */
|
#define RES4 0x4 /* 0/4 */
|
#define RES5 0xc /* 0/5 */
|
#define RES5 0xc /* 0/5 */
|
#define RES6 0x2 /* 0/6 */
|
#define RES6 0x2 /* 0/6 */
|
#define RES7 0xa /* 0/7 */
|
#define RES7 0xa /* 0/7 */
|
#define RES8 0x6 /* 0/8 */
|
#define RES8 0x6 /* 0/8 */
|
#define RES18 0xe /* 1/8 */
|
#define RES18 0xe /* 1/8 */
|
#define RES28 0x0 /* 2/8 */
|
#define RES28 0x0 /* 2/8 */
|
/* Special Rx Condition Interrupts */
|
/* Special Rx Condition Interrupts */
|
#define PAR_ERR 0x10 /* Parity error */
|
#define PAR_ERR 0x10 /* Parity error */
|
#define Rx_OVR 0x20 /* Rx Overrun Error */
|
#define Rx_OVR 0x20 /* Rx Overrun Error */
|
#define CRC_ERR 0x40 /* CRC/Framing Error */
|
#define CRC_ERR 0x40 /* CRC/Framing Error */
|
#define END_FR 0x80 /* End of Frame (SDLC) */
|
#define END_FR 0x80 /* End of Frame (SDLC) */
|
|
|
/* Read Register 2 (channel B only) - Interrupt vector */
|
/* Read Register 2 (channel B only) - Interrupt vector */
|
|
|
#define VECTOR_MASK 0x06
|
#define VECTOR_MASK 0x06
|
|
|
#define TXINT 0x00
|
#define TXINT 0x00
|
#define EXINT 0x02
|
#define EXINT 0x02
|
#define RXINT 0x04
|
#define RXINT 0x04
|
#define SPINT 0x06
|
#define SPINT 0x06
|
|
|
|
|
/* Read Register 3 (interrupt pending register) ch a only */
|
/* Read Register 3 (interrupt pending register) ch a only */
|
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
|
#define CHBEXT 0x1 /* Channel B Ext/Stat IP */
|
#define CHBTxIP 0x2 /* Channel B Tx IP */
|
#define CHBTxIP 0x2 /* Channel B Tx IP */
|
#define CHBRxIP 0x4 /* Channel B Rx IP */
|
#define CHBRxIP 0x4 /* Channel B Rx IP */
|
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
|
#define CHAEXT 0x8 /* Channel A Ext/Stat IP */
|
#define CHATxIP 0x10 /* Channel A Tx IP */
|
#define CHATxIP 0x10 /* Channel A Tx IP */
|
#define CHARxIP 0x20 /* Channel A Rx IP */
|
#define CHARxIP 0x20 /* Channel A Rx IP */
|
|
|
/* Read Register 8 (receive data register) */
|
/* Read Register 8 (receive data register) */
|
|
|
/* Read Register 10 (misc status bits) */
|
/* Read Register 10 (misc status bits) */
|
#define ONLOOP 2 /* On loop */
|
#define ONLOOP 2 /* On loop */
|
#define LOOPSEND 0x10 /* Loop sending */
|
#define LOOPSEND 0x10 /* Loop sending */
|
#define CLK2MIS 0x40 /* Two clocks missing */
|
#define CLK2MIS 0x40 /* Two clocks missing */
|
#define CLK1MIS 0x80 /* One clock missing */
|
#define CLK1MIS 0x80 /* One clock missing */
|
|
|
/* Read Register 12 (lower byte of baud rate generator constant) */
|
/* Read Register 12 (lower byte of baud rate generator constant) */
|
|
|
/* Read Register 13 (upper byte of baud rate generator constant) */
|
/* Read Register 13 (upper byte of baud rate generator constant) */
|
|
|
/* Read Register 15 (value of WR 15) */
|
/* Read Register 15 (value of WR 15) */
|
|
|
|
|
/* 8536 register definitions */
|
/* 8536 register definitions */
|
|
|
#define CIO_MICR 0x00 /* Master interrupt control register */
|
#define CIO_MICR 0x00 /* Master interrupt control register */
|
#define CIO_MCCR 0x01 /* Master configuration control register */
|
#define CIO_MCCR 0x01 /* Master configuration control register */
|
#define CIO_CTMS1 0x1c /* Counter/timer mode specification #1 */
|
#define CIO_CTMS1 0x1c /* Counter/timer mode specification #1 */
|
#define CIO_CTMS2 0x1d /* Counter/timer mode specification #2 */
|
#define CIO_CTMS2 0x1d /* Counter/timer mode specification #2 */
|
#define CIO_CTMS3 0x1e /* Counter/timer mode specification #3 */
|
#define CIO_CTMS3 0x1e /* Counter/timer mode specification #3 */
|
#define CIO_IVR 0x04 /* Interrupt vector register */
|
#define CIO_IVR 0x04 /* Interrupt vector register */
|
|
|
#define CIO_CSR1 0x0a /* Command and status register CTC #1 */
|
#define CIO_CSR1 0x0a /* Command and status register CTC #1 */
|
#define CIO_CSR2 0x0b /* Command and status register CTC #2 */
|
#define CIO_CSR2 0x0b /* Command and status register CTC #2 */
|
#define CIO_CSR3 0x0c /* Command and status register CTC #3 */
|
#define CIO_CSR3 0x0c /* Command and status register CTC #3 */
|
|
|
#define CIO_CT1MSB 0x16 /* CTC #1 Timer constant - MSB */
|
#define CIO_CT1MSB 0x16 /* CTC #1 Timer constant - MSB */
|
#define CIO_CT1LSB 0x17 /* CTC #1 Timer constant - LSB */
|
#define CIO_CT1LSB 0x17 /* CTC #1 Timer constant - LSB */
|
#define CIO_CT2MSB 0x18 /* CTC #2 Timer constant - MSB */
|
#define CIO_CT2MSB 0x18 /* CTC #2 Timer constant - MSB */
|
#define CIO_CT2LSB 0x19 /* CTC #2 Timer constant - LSB */
|
#define CIO_CT2LSB 0x19 /* CTC #2 Timer constant - LSB */
|
#define CIO_CT3MSB 0x1a /* CTC #3 Timer constant - MSB */
|
#define CIO_CT3MSB 0x1a /* CTC #3 Timer constant - MSB */
|
#define CIO_CT3LSB 0x1b /* CTC #3 Timer constant - LSB */
|
#define CIO_CT3LSB 0x1b /* CTC #3 Timer constant - LSB */
|
#define CIO_PDCA 0x23 /* Port A data direction control */
|
#define CIO_PDCA 0x23 /* Port A data direction control */
|
#define CIO_PDCB 0x2b /* Port B data direction control */
|
#define CIO_PDCB 0x2b /* Port B data direction control */
|
|
|
#define CIO_GCB 0x04 /* CTC Gate command bit */
|
#define CIO_GCB 0x04 /* CTC Gate command bit */
|
#define CIO_TCB 0x02 /* CTC Trigger command bit */
|
#define CIO_TCB 0x02 /* CTC Trigger command bit */
|
#define CIO_IE 0xc0 /* CTC Interrupt enable (set) */
|
#define CIO_IE 0xc0 /* CTC Interrupt enable (set) */
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#define CIO_CIP 0x20 /* CTC Clear interrupt pending */
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#define CIO_CIP 0x20 /* CTC Clear interrupt pending */
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#define CIO_IP 0x20 /* CTC Interrupt pending */
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#define CIO_IP 0x20 /* CTC Interrupt pending */
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/* 8580/85180/85280 Enhanced SCC register definitions */
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/* 8580/85180/85280 Enhanced SCC register definitions */
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/* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
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/* Write Register 7' (SDLC/HDLC Programmable Enhancements) */
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#define AUTOTXF 0x01 /* Auto Tx Flag */
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#define AUTOTXF 0x01 /* Auto Tx Flag */
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#define AUTOEOM 0x02 /* Auto EOM Latch Reset */
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#define AUTOEOM 0x02 /* Auto EOM Latch Reset */
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#define AUTORTS 0x04 /* Auto RTS */
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#define AUTORTS 0x04 /* Auto RTS */
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#define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
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#define TXDNRZI 0x08 /* TxD Pulled High in SDLC NRZI mode */
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#define FASTDTR 0x10 /* Fast DTR/REQ Mode */
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#define FASTDTR 0x10 /* Fast DTR/REQ Mode */
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#define CRCCBCR 0x20 /* CRC Check Bytes Completely Received */
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#define CRCCBCR 0x20 /* CRC Check Bytes Completely Received */
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#define EXTRDEN 0x40 /* Extended Read Enabled */
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#define EXTRDEN 0x40 /* Extended Read Enabled */
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/* Write Register 15 (external/status interrupt control) */
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/* Write Register 15 (external/status interrupt control) */
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#define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
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#define SHDLCE 1 /* SDLC/HDLC Enhancements Enable */
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#define FIFOE 4 /* FIFO Enable */
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#define FIFOE 4 /* FIFO Enable */
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/* Read Register 6 (frame status FIFO) */
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/* Read Register 6 (frame status FIFO) */
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#define BCLSB 0xff /* LSB of 14 bits count */
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#define BCLSB 0xff /* LSB of 14 bits count */
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/* Read Register 7 (frame status FIFO) */
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/* Read Register 7 (frame status FIFO) */
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#define BCMSB 0x3f /* MSB of 14 bits count */
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#define BCMSB 0x3f /* MSB of 14 bits count */
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#define FDA 0x40 /* FIFO Data Available Status */
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#define FDA 0x40 /* FIFO Data Available Status */
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#define FOY 0x80 /* FIFO Overflow Status */
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#define FOY 0x80 /* FIFO Overflow Status */
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#endif /* _SCC_H */
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#endif /* _SCC_H */
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/* global functions */
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/* global functions */
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extern int scc_init(void);
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extern int scc_init(void);
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