# Copyright (C) 1991-2009 Altera Corporation
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# Copyright (C) 1991-2009 Altera Corporation
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# Your use of Altera Corporation's design tools, logic functions
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# Your use of Altera Corporation's design tools, logic functions
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# and other software and tools, and its AMPP partner logic
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# and other software and tools, and its AMPP partner logic
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# functions, and any output files from any of the foregoing
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# functions, and any output files from any of the foregoing
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# (including device programming or simulation files), and any
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# (including device programming or simulation files), and any
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# associated documentation or information are expressly subject
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# associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License
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# to the terms and conditions of the Altera Program License
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# Subscription Agreement, Altera MegaCore Function License
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# Subscription Agreement, Altera MegaCore Function License
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# Agreement, or other applicable license agreement, including,
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# Agreement, or other applicable license agreement, including,
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# without limitation, that your use is for the sole purpose of
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# without limitation, that your use is for the sole purpose of
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# programming logic devices manufactured by Altera and sold by
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# programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the
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# Altera or its authorized distributors. Please refer to the
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# applicable agreement for further details.
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# applicable agreement for further details.
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# Quartus II: Generate Tcl File for Project
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# Quartus II: Generate Tcl File for Project
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# File: setup_prj.tcl
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# File: setup_prj.tcl
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# Generated on: Thu Nov 5 13:19:06 2009
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# Generated on: Sun Nov 29 16:35:34 2009
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# Load Quartus II Tcl Project package
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# Load Quartus II Tcl Project package
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package require ::quartus::project
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package require ::quartus::project
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set need_to_close_project 0
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set need_to_close_project 0
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set make_assignments 1
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set make_assignments 1
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# Check that the right project is open
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# Check that the right project is open
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if {[is_project_open]} {
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if {[is_project_open]} {
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if {[string compare $quartus(project) "or1k_soc_top"]} {
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if {[string compare $quartus(project) "or1k_soc_top"]} {
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puts "Project or1k_soc_top is not open"
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puts "Project or1k_soc_top is not open"
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set make_assignments 0
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set make_assignments 0
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}
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}
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} else {
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} else {
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# Only open if not already open
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# Only open if not already open
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if {[project_exists or1k_soc_top]} {
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if {[project_exists or1k_soc_top]} {
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project_open -revision or1k_soc_top or1k_soc_top
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project_open -revision or1k_soc_top or1k_soc_top
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} else {
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} else {
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project_new -revision or1k_soc_top or1k_soc_top
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project_new -revision or1k_soc_top or1k_soc_top
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}
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}
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set need_to_close_project 1
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set need_to_close_project 1
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}
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}
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# Make assignments
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# Make assignments
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if {$make_assignments} {
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if {$make_assignments} {
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name FAMILY "Cyclone III"
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set_global_assignment -name DEVICE EP3C25F324C6
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set_global_assignment -name DEVICE EP3C25F324C6
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:58 OCTOBER 02, 2009"
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set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:58 OCTOBER 02, 2009"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
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set_global_assignment -name SIMULATION_MODE FUNCTIONAL
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set_global_assignment -name SIMULATION_MODE FUNCTIONAL
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set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
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set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS OFF
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)"
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
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set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
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set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY OFF -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "2.5 V"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS TEST_BENCH_MODE -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_NATIVELINK_SIMULATION_TEST_BENCH or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_TEST_BENCH_NAME or1k_soc_top -section_id eda_simulation
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id or1k_soc_top
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set_global_assignment -name EDA_DESIGN_INSTANCE_NAME i1 -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "600 us" -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_RUN_SIM_FOR "600 us" -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or1k_soc_top_vlg_vec_tst -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_MODULE_NAME or1k_soc_top_vlg_vec_tst -section_id or1k_soc_top
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set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
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set_global_assignment -name FITTER_EFFORT "AUTO FIT"
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
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set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
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set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
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set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP OFF
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set_global_assignment -name MISC_FILE /opt/workspace/xzeng/esig/trunk/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name MISC_FILE /opt/workspace/xzeng/esig/trunk/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_pll.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_auk_ddr_hp_controller_wrapper.vo -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq.vhd -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy_seq.vhd -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_alt_mem_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_controller_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_controller_phy.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_mem_model.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_mem_model.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_full_mem_model.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_full_mem_model.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_example_top_tb.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/testbench/altera_ddr_example_top_tb.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_ex_lfsr8.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_ex_lfsr8.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_driver.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_driver.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_top.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_example_top.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE or1k_soc_top_tb.v -section_id or1k_soc_top
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set_global_assignment -name EDA_TEST_BENCH_FILE or1k_soc_top_tb.v -section_id or1k_soc_top
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
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set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
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set_global_assignment -name MISC_FILE /home/xzeng/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name MISC_FILE /home/xzeng/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
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set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/timescale.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/timescale.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/initSD.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/initSD.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSDBlock.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSDBlock.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSPIWireData.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/readWriteSPIWireData.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sendCmd.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sendCmd.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_dpMem_dc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_dpMem_dc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_fifoRTL.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_fifoRTL.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_RxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/sm_TxFifoBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiCtrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiCtrl.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMaster_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMasterWishBoneBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiMasterWishBoneBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiTxRxData.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/spiTxRxData.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/ctrlStsRegBI.v
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set_global_assignment -name VERILOG_FILE ../../rtl/mmc_sd/RTL/ctrlStsRegBI.v
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set_global_assignment -name SDC_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_timing.sdc
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set_global_assignment -name SDC_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_phy_ddr_timing.sdc
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/timescale.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/timescale.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_shift.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_shift.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_top.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_clgen.v
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set_global_assignment -name VERILOG_FILE ../../rtl/spi/rtl/verilog/spi_clgen.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/xilinx_dist_ram_16x32.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_cop.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_cop.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_crc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_crc.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_defines.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_fifo.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_maccontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_maccontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_macstatus.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_macstatus.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_miim.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_miim.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_outputcontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_outputcontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_random.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_random.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_receivecontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_receivecontrol.v
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set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_register.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_register.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_registers.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_registers.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxaddrcheck.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxcounters.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxcounters.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxethmac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxethmac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxstatem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_rxstatem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_shiftreg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_shiftreg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_spram_256x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_spram_256x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_transmitcontrol.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txcounters.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txcounters.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txethmac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txethmac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txstatem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_txstatem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_wishbone.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_wishbone.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_clockgen.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/ethernet/rtl/verilog/eth_clockgen.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_wb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_wb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_debug_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_debug_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_receiver.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_receiver.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_regs.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_regs.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_rfifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_rfifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_sync_flops.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_sync_flops.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_tfifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_tfifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_transmitter.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/uart_transmitter.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/raminfr.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/uart16550/rtl/verilog/raminfr.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_wb_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_wb_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_cs_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_dp.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_dp.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_incn_r.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_incn_r.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_mem_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_mem_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_obct_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rd_fifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_refresh.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_refresh.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_timing.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_timing.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/mem_if/rtl/verilog/mc_adr_sel.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ram/altera_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/flash_sram/flash_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/flash_sram/flash_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/gpio/rtl/verilog/gpio_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1k_soc_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_master_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_msel.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_dec.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_pri_enc.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_slave_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/wb_conmax/rtl/verilog/wb_conmax_arb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/timescale.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_amultp2_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cfgr.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cfgr.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cpu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_cpu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ctrl.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ctrl.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_fsm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_tag.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dc_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_tlb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dmmu_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_256x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_dpram_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_du.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_du.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_except.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_except.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_freeze.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_freeze.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_genpc.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_genpc.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_gmultp2_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_fsm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_ram.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_tag.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_ic_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_if.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_tlb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_immu_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_iwb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_lsu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_lsu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mem2reg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_mult_mac.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_operandmuxes.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pic.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pic.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_pm.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_qmem_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_reg2mem.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rf.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_rfram_generic.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sb_fifo.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x32_bw.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_1024x8.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_128x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x32_bw.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_2048x8.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_256x21.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_32x24.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_512x20.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x14.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x22.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_spram_64x24.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sprs.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_sprs.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tpram_32x32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tt.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_tt.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wbmux.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_wbmux.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_xcv_ram32x8d.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_alu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/or1200/rtl/verilog/or1200_alu.v
|
set_global_assignment -name QIP_FILE ../../rtl/altera_pll/altera_pll.qip
|
set_global_assignment -name QIP_FILE ../../rtl/altera_pll/altera_pll.qip
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/altera_ddr_ctrl/altera_ddr_top.v
|
set_global_assignment -name VECTOR_WAVEFORM_FILE or1k_soc_top.vwf
|
set_global_assignment -name VECTOR_WAVEFORM_FILE or1k_soc_top.vwf
|
set_global_assignment -name VECTOR_WAVEFORM_FILE altera_ram.vwf
|
set_global_assignment -name VECTOR_WAVEFORM_FILE altera_ram.vwf
|
set_global_assignment -name QIP_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.qip
|
set_global_assignment -name QIP_FILE ../../rtl/altera_ddr_ctrl/altera_ddr.qip
|
set_global_assignment -name VHDL_FILE ../../rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
|
set_global_assignment -name VHDL_FILE ../../rtl/altera_ddr_ctrl/auk_ddr_hp_controller.vhd
|
set_global_assignment -name MISC_FILE /opt/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
|
set_global_assignment -name MISC_FILE /opt/project/esig/or1k_soc/prj/altera/or1k_soc_top.dpf
|
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE or1k_soc_top.vwf
|
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE or1k_soc_top.vwf
|
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE altera_ram.vwf
|
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE altera_ram.vwf
|
set_global_assignment -name VHDL_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
|
set_global_assignment -name VHDL_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/altera_virtual_jtag/rtl/vhdl/altera_virtual_jtag.vhd
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_module.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_module.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_or1k_status_reg.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_top.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_biu.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_wb_defines.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
|
set_global_assignment -name VERILOG_FILE ../../rtl/adv_debug_sys/tags/ADS_RELEASE_1_2_0/Hardware/adv_dbg_if/rtl/verilog/adbg_crc32.v
|
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
|
set_global_assignment -name EDA_TEST_BENCH_FILE ../../../../../altera9.0/quartus/libraries/megafunctions/sld_virtual_jtag.v -section_id or1k_soc_top
|
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
set_global_assignment -name ENABLE_SIGNALTAP OFF
|
set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
|
set_global_assignment -name USE_SIGNALTAP_FILE sd_loader_test.stp
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
|
set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
|
set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
|
set_global_assignment -name SEARCH_PATH ../../rtl/altera_ddr_ctrl/.
|
set_global_assignment -name SEARCH_PATH "../../rtl/altera_ddr_ctrl/ddr_high_performance_controller-library"
|
set_global_assignment -name SEARCH_PATH "../../rtl/altera_ddr_ctrl/ddr_high_performance_controller-library"
|
|
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
|
|
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
set_location_assignment PIN_B9 -to wb_clk_pad_i
|
set_location_assignment PIN_B9 -to wb_clk_pad_i
|
set_location_assignment PIN_V9 -to ddr_pll_clk_pad_i
|
set_location_assignment PIN_V9 -to ddr_pll_clk_pad_i
|
set_location_assignment PIN_N2 -to rst_n_pad_i
|
set_location_assignment PIN_N2 -to rst_n_pad_i
|
set_location_assignment PIN_E18 -to uart_srx_pad_i
|
set_location_assignment PIN_E18 -to uart_srx_pad_i
|
set_location_assignment PIN_H17 -to uart_stx_pad_o
|
set_location_assignment PIN_H17 -to uart_stx_pad_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[12]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[12]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[9]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[9]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[8]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[8]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[11]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[11]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[10]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[10]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_we_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_we_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[2]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[2]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[3]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[3]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[4]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[4]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[5]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[5]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[6]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[6]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[7]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[7]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[9]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[9]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[10]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[10]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[11]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[11]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[12]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[12]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[13]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[13]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[14]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[14]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[15]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[15]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cs_n_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cs_n_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_n_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_n_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cke_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cke_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cas_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_cas_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_clk_io[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ba_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[2]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[2]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[3]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[3]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[4]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[4]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[5]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[5]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[6]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[6]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[7]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_addr_o[7]
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ras_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_ras_n_o
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[0]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dm_o[1]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[8]
|
set_instance_assignment -name IO_STANDARD "SSTL-2 CLASS I" -to ddr_mem_dq_io[8]
|
set_location_assignment PIN_U16 -to ddr_mem_addr_o[12]
|
set_location_assignment PIN_U16 -to ddr_mem_addr_o[12]
|
set_location_assignment PIN_V17 -to ddr_mem_addr_o[11]
|
set_location_assignment PIN_V17 -to ddr_mem_addr_o[11]
|
set_location_assignment PIN_U17 -to ddr_mem_addr_o[10]
|
set_location_assignment PIN_U17 -to ddr_mem_addr_o[10]
|
set_location_assignment PIN_V13 -to ddr_mem_addr_o[9]
|
set_location_assignment PIN_V13 -to ddr_mem_addr_o[9]
|
set_location_assignment PIN_T13 -to ddr_mem_addr_o[8]
|
set_location_assignment PIN_T13 -to ddr_mem_addr_o[8]
|
set_location_assignment PIN_T14 -to ddr_mem_addr_o[7]
|
set_location_assignment PIN_T14 -to ddr_mem_addr_o[7]
|
set_location_assignment PIN_P6 -to ddr_mem_addr_o[6]
|
set_location_assignment PIN_P6 -to ddr_mem_addr_o[6]
|
set_location_assignment PIN_P7 -to ddr_mem_addr_o[5]
|
set_location_assignment PIN_P7 -to ddr_mem_addr_o[5]
|
set_location_assignment PIN_P8 -to ddr_mem_addr_o[4]
|
set_location_assignment PIN_P8 -to ddr_mem_addr_o[4]
|
set_location_assignment PIN_U8 -to ddr_mem_addr_o[3]
|
set_location_assignment PIN_U8 -to ddr_mem_addr_o[3]
|
set_location_assignment PIN_U7 -to ddr_mem_addr_o[2]
|
set_location_assignment PIN_U7 -to ddr_mem_addr_o[2]
|
set_location_assignment PIN_U5 -to ddr_mem_addr_o[1]
|
set_location_assignment PIN_U5 -to ddr_mem_addr_o[1]
|
set_location_assignment PIN_U1 -to ddr_mem_addr_o[0]
|
set_location_assignment PIN_U1 -to ddr_mem_addr_o[0]
|
set_location_assignment PIN_V12 -to ddr_mem_ba_o[1]
|
set_location_assignment PIN_V12 -to ddr_mem_ba_o[1]
|
set_location_assignment PIN_V11 -to ddr_mem_ba_o[0]
|
set_location_assignment PIN_V11 -to ddr_mem_ba_o[0]
|
set_location_assignment PIN_T4 -to ddr_mem_cas_n_o
|
set_location_assignment PIN_T4 -to ddr_mem_cas_n_o
|
set_location_assignment PIN_R13 -to ddr_mem_cke_o[0]
|
set_location_assignment PIN_R13 -to ddr_mem_cke_o[0]
|
set_location_assignment PIN_U2 -to ddr_mem_clk_io[0]
|
set_location_assignment PIN_U2 -to ddr_mem_clk_io[0]
|
set_location_assignment PIN_V2 -to ddr_mem_clk_n_io[0]
|
set_location_assignment PIN_V2 -to ddr_mem_clk_n_io[0]
|
set_location_assignment PIN_V1 -to ddr_mem_cs_n_o[0]
|
set_location_assignment PIN_V1 -to ddr_mem_cs_n_o[0]
|
set_location_assignment PIN_V8 -to ddr_mem_dm_o[1]
|
set_location_assignment PIN_V8 -to ddr_mem_dm_o[1]
|
set_location_assignment PIN_V3 -to ddr_mem_dm_o[0]
|
set_location_assignment PIN_V3 -to ddr_mem_dm_o[0]
|
set_location_assignment PIN_U15 -to ddr_mem_we_n_o
|
set_location_assignment PIN_U15 -to ddr_mem_we_n_o
|
set_location_assignment PIN_V16 -to ddr_mem_ras_n_o
|
set_location_assignment PIN_V16 -to ddr_mem_ras_n_o
|
set_location_assignment PIN_U3 -to ddr_mem_dqs_io[0]
|
set_location_assignment PIN_U3 -to ddr_mem_dqs_io[0]
|
set_location_assignment PIN_T8 -to ddr_mem_dqs_io[1]
|
set_location_assignment PIN_T8 -to ddr_mem_dqs_io[1]
|
set_location_assignment PIN_U4 -to ddr_mem_dq_io[0]
|
set_location_assignment PIN_U4 -to ddr_mem_dq_io[0]
|
set_location_assignment PIN_V4 -to ddr_mem_dq_io[1]
|
set_location_assignment PIN_V4 -to ddr_mem_dq_io[1]
|
set_location_assignment PIN_R8 -to ddr_mem_dq_io[2]
|
set_location_assignment PIN_R8 -to ddr_mem_dq_io[2]
|
set_location_assignment PIN_V5 -to ddr_mem_dq_io[3]
|
set_location_assignment PIN_V5 -to ddr_mem_dq_io[3]
|
set_location_assignment PIN_P9 -to ddr_mem_dq_io[4]
|
set_location_assignment PIN_P9 -to ddr_mem_dq_io[4]
|
set_location_assignment PIN_U6 -to ddr_mem_dq_io[5]
|
set_location_assignment PIN_U6 -to ddr_mem_dq_io[5]
|
set_location_assignment PIN_V6 -to ddr_mem_dq_io[6]
|
set_location_assignment PIN_V6 -to ddr_mem_dq_io[6]
|
set_location_assignment PIN_V7 -to ddr_mem_dq_io[7]
|
set_location_assignment PIN_V7 -to ddr_mem_dq_io[7]
|
set_location_assignment PIN_U13 -to ddr_mem_dq_io[8]
|
set_location_assignment PIN_U13 -to ddr_mem_dq_io[8]
|
set_location_assignment PIN_U12 -to ddr_mem_dq_io[9]
|
set_location_assignment PIN_U12 -to ddr_mem_dq_io[9]
|
set_location_assignment PIN_U11 -to ddr_mem_dq_io[10]
|
set_location_assignment PIN_U11 -to ddr_mem_dq_io[10]
|
set_location_assignment PIN_V15 -to ddr_mem_dq_io[11]
|
set_location_assignment PIN_V15 -to ddr_mem_dq_io[11]
|
set_location_assignment PIN_U14 -to ddr_mem_dq_io[12]
|
set_location_assignment PIN_U14 -to ddr_mem_dq_io[12]
|
set_location_assignment PIN_R11 -to ddr_mem_dq_io[13]
|
set_location_assignment PIN_R11 -to ddr_mem_dq_io[13]
|
set_location_assignment PIN_P10 -to ddr_mem_dq_io[14]
|
set_location_assignment PIN_P10 -to ddr_mem_dq_io[14]
|
set_location_assignment PIN_V14 -to ddr_mem_dq_io[15]
|
set_location_assignment PIN_V14 -to ddr_mem_dq_io[15]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_n_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_clk_n_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cs_n_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cs_n_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cke_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cke_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[2]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[2]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[3]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[3]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[4]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[4]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[5]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[5]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[6]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[6]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[7]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[7]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[8]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[8]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[9]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[9]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[10]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[10]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[11]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[11]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[12]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_addr_o[12]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ba_o[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ras_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_ras_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cas_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_cas_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_we_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to ddr_mem_we_n_o
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[2]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[2]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[3]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[3]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[4]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[4]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[5]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[5]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[6]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[6]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[7]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[7]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[8]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[8]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[9]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[9]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[10]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[10]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[11]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[11]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[12]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[12]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[13]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[13]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[14]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[14]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[15]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dq_io[15]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[1]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW 12MA -to ddr_mem_dm_o[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[2]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[2]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[3]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[3]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[4]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[4]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[5]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[5]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[6]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[6]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[7]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[7]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[8]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[8]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[9]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[9]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[10]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[10]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[11]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[11]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[12]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[12]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[13]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[13]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[14]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[14]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[15]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dq_io[15]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dqs_io[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[0]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[1]
|
set_instance_assignment -name OUTPUT_ENABLE_GROUP 711165762 -to ddr_mem_dm_o[1]
|
set_instance_assignment -name CKN_CK_PAIR ON -from ddr_mem_clk_n_io[0] -to ddr_mem_clk_io[0]
|
set_instance_assignment -name CKN_CK_PAIR ON -from ddr_mem_clk_n_io[0] -to ddr_mem_clk_io[0]
|
set_location_assignment PIN_P13 -to gpio_a_pad_io[0]
|
set_location_assignment PIN_P13 -to gpio_a_pad_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to gpio_a_pad_io[0]
|
set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to gpio_a_pad_io[0]
|
set_location_assignment PIN_M2 -to sd_card_clk_pad_o
|
set_location_assignment PIN_M2 -to sd_card_clk_pad_o
|
set_location_assignment PIN_N8 -to sd_card_cs_n_pad_o
|
set_location_assignment PIN_N8 -to sd_card_cs_n_pad_o
|
set_location_assignment PIN_M3 -to sd_card_data_pad_i
|
set_location_assignment PIN_M3 -to sd_card_data_pad_i
|
set_location_assignment PIN_L6 -to sd_card_data_pad_o
|
set_location_assignment PIN_L6 -to sd_card_data_pad_o
|
set_location_assignment PIN_N18 -to eth_tx_clk_pad_i
|
set_location_assignment PIN_N18 -to eth_tx_clk_pad_i
|
set_location_assignment PIN_L17 -to eth_tx_en_pad_o
|
set_location_assignment PIN_L17 -to eth_tx_en_pad_o
|
set_location_assignment PIN_M18 -to eth_txd_pad_o[0]
|
set_location_assignment PIN_M18 -to eth_txd_pad_o[0]
|
set_location_assignment PIN_L14 -to eth_txd_pad_o[1]
|
set_location_assignment PIN_L14 -to eth_txd_pad_o[1]
|
set_location_assignment PIN_L15 -to eth_txd_pad_o[2]
|
set_location_assignment PIN_L15 -to eth_txd_pad_o[2]
|
set_location_assignment PIN_P17 -to eth_txd_pad_o[3]
|
set_location_assignment PIN_P17 -to eth_txd_pad_o[3]
|
set_location_assignment PIN_F17 -to eth_rx_clk_pad_i
|
set_location_assignment PIN_F17 -to eth_rx_clk_pad_i
|
set_location_assignment PIN_G18 -to eth_rx_dv_pad_i
|
set_location_assignment PIN_G18 -to eth_rx_dv_pad_i
|
set_location_assignment PIN_L3 -to eth_crs_pad_i
|
set_location_assignment PIN_L3 -to eth_crs_pad_i
|
set_location_assignment PIN_L4 -to eth_rx_er_pad_i
|
set_location_assignment PIN_L4 -to eth_rx_er_pad_i
|
set_location_assignment PIN_G17 -to eth_col_pad_i
|
set_location_assignment PIN_G17 -to eth_col_pad_i
|
set_location_assignment PIN_P2 -to eth_rxd_pad_i[0]
|
set_location_assignment PIN_P2 -to eth_rxd_pad_i[0]
|
set_location_assignment PIN_P1 -to eth_rxd_pad_i[1]
|
set_location_assignment PIN_P1 -to eth_rxd_pad_i[1]
|
set_location_assignment PIN_T3 -to eth_rxd_pad_i[2]
|
set_location_assignment PIN_T3 -to eth_rxd_pad_i[2]
|
set_location_assignment PIN_R3 -to eth_rxd_pad_i[3]
|
set_location_assignment PIN_R3 -to eth_rxd_pad_i[3]
|
set_location_assignment PIN_P18 -to eth_mdc_pad_o
|
set_location_assignment PIN_P18 -to eth_mdc_pad_o
|
set_location_assignment PIN_N7 -to eth_mdio_pad_io
|
set_location_assignment PIN_N7 -to eth_mdio_pad_io
|
set_location_assignment PIN_H18 -to eth_reset_n_pad_o
|
set_location_assignment PIN_H18 -to eth_reset_n_pad_o
|
set_location_assignment PIN_N9 -to led3_pad_o
|
set_location_assignment PIN_N9 -to led3_pad_o
|
|
|
# Commit assignments
|
# Commit assignments
|
export_assignments
|
export_assignments
|
|
|
# Close project
|
# Close project
|
if {$need_to_close_project} {
|
if {$need_to_close_project} {
|
project_close
|
project_close
|
}
|
}
|
}
|
}
|
|
|
