/*
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/*
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* SD/MMC card bootloader for OR1k SoC
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* SD/MMC card bootloader for OR1k SoC
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*
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*
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* Copyright (c) 2008 by:
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* Copyright (c) 2008 by:
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* Xianfeng Zeng <xianfeng.zeng@gmail.com, Xianfeng.zeng@SierraAtlantic.com>
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* Xianfeng Zeng <xianfeng.zeng@gmail.com, Xianfeng.zeng@SierraAtlantic.com>
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the BSD Licence, GNU General Public License
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* it under the terms of the BSD Licence, GNU General Public License
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* as published by the Free Software Foundation; either version 2 of the
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* as published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version
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* License, or (at your option) any later version
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*
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*
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* ChangeLog:
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* ChangeLog:
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* 2009-10-05 12:56:55 xzeng
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* 2009-10-05 12:56:55 xzeng
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* Init.
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* Init.
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*
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*
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*/
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*/
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#define INCLUDED_FROM_C_FILE
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#define INCLUDED_FROM_C_FILE
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#include "orsocdef.h"
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#include "orsocdef.h"
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#include "board.h"
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#include "board.h"
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#define DEBUG 1
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#define DEBUG 1
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#define barrier() __asm__ __volatile__("": : :"memory")
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#define barrier() __asm__ __volatile__("": : :"memory")
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#ifdef DEBUG
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#ifdef DEBUG
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void putc(int c)
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void or1k_putc(int c)
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{
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{
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while ( 0x20 != (REG8(UART_BASE_ADD+5) & 0x20) )
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while ( 0x20 != (REG8(UART_BASE_ADD+5) & 0x20) )
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;
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;
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REG8(UART_BASE_ADD) = c;
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REG8(UART_BASE_ADD) = c;
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}
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}
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void print(unsigned char *c)
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void print(unsigned char *c)
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{
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{
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uint32 i;
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uint32 i;
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if (c == NULL)
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if (c == NULL)
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return;
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return;
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for (i = 0; c[i] != 0; i++) {
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for (i = 0; c[i] != 0; i++) {
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putc(c[i]);
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or1k_putc(c[i]);
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}
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}
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}
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}
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void print32bit (long unsigned int val)
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void print32bit (long unsigned int val)
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{
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{
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int i;
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int i;
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unsigned long int myNibble;
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unsigned long int myNibble;
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char myChar;
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char myChar;
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for (i=0;i<8;i++) {
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for (i=0;i<8;i++) {
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myNibble = (val >> 28) & 0xfUL;
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myNibble = (val >> 28) & 0xfUL;
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if (myNibble <= 0x9)
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if (myNibble <= 0x9)
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myChar = (char) myNibble + 0x30;
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myChar = (char) myNibble + 0x30;
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else
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else
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myChar = (char) myNibble + 0x37;
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myChar = (char) myNibble + 0x37;
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putc (myChar);
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or1k_putc (myChar);
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val = val << 4;
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val = val << 4;
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}
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}
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putc ('\n');
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or1k_putc ('\n');
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putc ('\r');
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or1k_putc ('\r');
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}
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}
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#else
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#else
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#define putc(a)
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#define or1k_putc(a)
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#define print(a)
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#define print(a)
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#endif
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#endif
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void do_sleep()
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void do_sleep()
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{
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{
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uint32 i;
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uint32 i;
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for (i = 0; i < 200000; i++)
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for (i = 0; i < 200000; i++)
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;
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;
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}
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}
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void do_sleep2()
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void do_sleep2()
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{
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{
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uint32 i;
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uint32 i;
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for (i = 0; i < 1000; i++)
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for (i = 0; i < 1000; i++)
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;
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;
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}
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}
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/******************************************************************************/
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/******************************************************************************/
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/* G P I O W R I T E */
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/* G P I O W R I T E */
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/******************************************************************************/
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/******************************************************************************/
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// Write to the GPIO (32 bits)
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// Write to the GPIO (32 bits)
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void GPIO_Write(uint32 GPIO_data)
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void GPIO_Write(uint32 GPIO_data)
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{
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{
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REG32(GPIO_BASE + RGPIO_OUT) = GPIO_data;
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REG32(GPIO_BASE + RGPIO_OUT) = GPIO_data;
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}
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}
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/******************************************************************************/
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/******************************************************************************/
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/* F O R s p i M A S T E R */
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/* F O R s p i M A S T E R */
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/******************************************************************************/
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/******************************************************************************/
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//Initialize
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//Initialize
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int spiMaster_init()
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int spiMaster_init()
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{
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{
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uint8 data;
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uint8 data;
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int i;
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int i;
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REG8(SD_BASE_ADD + SD_CLK_DEL_REG) = 0x1;
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REG8(SD_BASE_ADD + SD_CLK_DEL_REG) = 0x1;
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for (i = 0; i < 5; i++) {
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for (i = 0; i < 5; i++) {
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REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_INIT_SD;
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REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_INIT_SD;
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 1; // TRANS_START;
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 1; // TRANS_START;
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do_sleep();
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do_sleep();
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while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
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while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
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;
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;
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}
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}
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data = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0x3;
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data = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0x3;
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if (data == 0) {
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if (data == 0) {
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return 0;
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return 0;
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}
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}
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}
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}
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return data;
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return data;
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}
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}
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unsigned char data[512];
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unsigned char data[512];
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int copy_sd2ddr(void)
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int copy_sd2ddr(void)
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{
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{
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int i, j;
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int i, j;
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uint8 data;
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uint8 data;
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unsigned char transError;
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unsigned char transError;
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uint32 blockCnt;
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uint32 blockCnt;
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uint32 numBlocks = 2 * 1024 * 10; // How mang blocks will be copied
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uint32 numBlocks = 2 * 1024 * 10; // How mang blocks will be copied
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uint32 ddr_offset = 0;
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uint32 ddr_offset = 0;
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print("Start copying SD image to DDR SDRAM...\n\r");
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print("\n\r");
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print("Copying SD image to DDR SDRAM...\n\r");
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print("Blocks:");
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print("Blocks:");
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print32bit((long unsigned int)numBlocks);
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print32bit((long unsigned int)numBlocks);
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for (blockCnt = 0; blockCnt < numBlocks; blockCnt++) {
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for (blockCnt = 0; blockCnt < numBlocks; blockCnt++) {
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REG8(SD_BASE_ADD + SD_ADDR_7_0_REG) = 0;
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REG8(SD_BASE_ADD + SD_ADDR_7_0_REG) = 0;
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REG8(SD_BASE_ADD + SD_ADDR_15_8_REG) = (unsigned char) ((ddr_offset >> 8) & 0xff);
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REG8(SD_BASE_ADD + SD_ADDR_15_8_REG) = (unsigned char) ((ddr_offset >> 8) & 0xff);
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REG8(SD_BASE_ADD + SD_ADDR_23_16_REG) = (unsigned char) ((ddr_offset >> 16) & 0xff);
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REG8(SD_BASE_ADD + SD_ADDR_23_16_REG) = (unsigned char) ((ddr_offset >> 16) & 0xff);
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REG8(SD_BASE_ADD + SD_ADDR_31_24_REG) = (unsigned char) ((ddr_offset >> 24) & 0xff);
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REG8(SD_BASE_ADD + SD_ADDR_31_24_REG) = (unsigned char) ((ddr_offset >> 24) & 0xff);
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REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_RW_READ_SD_BLOCK;
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REG8(SD_BASE_ADD + SD_TRANS_TYPE_REG) = SD_RW_READ_SD_BLOCK;
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REG8(SD_BASE_ADD + SD_RX_FIFO_CONTROL_REG) = 0x1; // Clean the RX FIFO
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REG8(SD_BASE_ADD + SD_RX_FIFO_CONTROL_REG) = 0x1; // Clean the RX FIFO
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1; //TRANS_START
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1; //TRANS_START
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while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
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while (REG8(SD_BASE_ADD + SD_TRANS_STS_REG) & 0x1) { // exit while !TRABS_BUSY
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;
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;
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}
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}
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transError = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0xc;
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transError = REG8(SD_BASE_ADD + SD_TRANS_ERROR_REG) & 0xc;
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if ( transError == SD_READ_NO_ERROR) {
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if ( transError == SD_READ_NO_ERROR) {
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for (i = 0; i < 512; i++) {
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for (i = 0; i < 512; i++) {
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data = REG8(SD_BASE_ADD + SD_RX_FIFO_DATA_REG) ;
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data = REG8(SD_BASE_ADD + SD_RX_FIFO_DATA_REG) ;
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REG8(DDR_SDRAM_BASE_ADDR + ddr_offset + i) = data ;
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REG8(DDR_SDRAM_BASE_ADDR + ddr_offset + i) = data ;
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// print32bit((long unsigned int)data);
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// print32bit((long unsigned int)data);
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}
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}
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if ((blockCnt % 0x40) == 0) {
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if ((blockCnt % 0x40) == 0) {
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putc('.');
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or1k_putc('.');
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j++;
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j++;
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}
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}
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if (j == 20) {
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if (j == 20) {
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j = 0;
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j = 0;
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print("\n\r");
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print("\n\r");
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}
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}
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ddr_offset += 512;
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ddr_offset += 512;
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} else {
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} else {
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putc('R');
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or1k_putc('R');
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j++;
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j++;
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if (j == 20) {
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if (j == 20) {
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j = 0;
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j = 0;
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print("\n\r");
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print("\n\r");
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}
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}
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spiMaster_init(); // Init again and retry
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spiMaster_init(); // Init again and retry
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blockCnt--; // read the same block again
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blockCnt--; // read the same block again
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}
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}
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}
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}
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print("\r\nSD Copy Done!\n\r");
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print("\r\nSD Copy Done!\n\r");
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}
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}
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/******************************************************************************/
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/******************************************************************************/
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/* TEST EXTERNAL DDR SDRAM */
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/* TEST EXTERNAL DDR SDRAM */
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/******************************************************************************/
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/******************************************************************************/
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void ddr_sdram_sample_test()
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void ddr_sdram_sample_test()
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{
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{
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uint32 int32;
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uint32 int32;
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uint16 int16;
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uint16 int16;
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uint8 int8;
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uint8 int8;
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int i;
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int i;
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REG32(DDR_SDRAM_BASE_ADDR) = 0x12345678;
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REG32(DDR_SDRAM_BASE_ADDR) = 0x12345678;
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int32 = REG32(DDR_SDRAM_BASE_ADDR);
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int32 = REG32(DDR_SDRAM_BASE_ADDR);
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REG16(DDR_SDRAM_BASE_ADDR + 10) = 0x55aa;
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REG16(DDR_SDRAM_BASE_ADDR + 10) = 0x55aa;
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int16 = REG16(DDR_SDRAM_BASE_ADDR + 10);
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int16 = REG16(DDR_SDRAM_BASE_ADDR + 10);
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REG8(DDR_SDRAM_BASE_ADDR + 20) = 0x5a;
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REG8(DDR_SDRAM_BASE_ADDR + 20) = 0x5a;
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int8 = REG8(DDR_SDRAM_BASE_ADDR + 20);
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int8 = REG8(DDR_SDRAM_BASE_ADDR + 20);
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if (REG8(DDR_SDRAM_BASE_ADDR + 20) != 0x5a)
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if (REG8(DDR_SDRAM_BASE_ADDR + 20) != 0x5a)
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print ("DDR SDRAM accesses short type Error:20!\n\r");
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print ("DDR SDRAM accesses short type Error:20!\n\r");
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REG8(DDR_SDRAM_BASE_ADDR + 100) = 0x12;
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REG8(DDR_SDRAM_BASE_ADDR + 100) = 0x12;
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REG8(DDR_SDRAM_BASE_ADDR + 101) = 0x34;
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REG8(DDR_SDRAM_BASE_ADDR + 101) = 0x34;
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REG8(DDR_SDRAM_BASE_ADDR + 102) = 0x56;
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REG8(DDR_SDRAM_BASE_ADDR + 102) = 0x56;
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REG8(DDR_SDRAM_BASE_ADDR + 103) = 0x78;
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REG8(DDR_SDRAM_BASE_ADDR + 103) = 0x78;
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int32 = REG32(DDR_SDRAM_BASE_ADDR + 100);
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int32 = REG32(DDR_SDRAM_BASE_ADDR + 100);
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if (REG8(DDR_SDRAM_BASE_ADDR + 100) != 0x12)
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if (REG8(DDR_SDRAM_BASE_ADDR + 100) != 0x12)
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print ("DDR SDRAM accesses char type Error:100!\n\r");
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print ("DDR SDRAM accesses char type Error:100!\n\r");
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if (REG8(DDR_SDRAM_BASE_ADDR + 101) != 0x34)
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if (REG8(DDR_SDRAM_BASE_ADDR + 101) != 0x34)
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print ("DDR SDRAM accesses char type Error:101!\n\r");
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print ("DDR SDRAM accesses char type Error:101!\n\r");
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if (REG8(DDR_SDRAM_BASE_ADDR + 102) != 0x56)
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if (REG8(DDR_SDRAM_BASE_ADDR + 102) != 0x56)
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print ("DDR SDRAM accesses char type Error:102!\n\r");
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print ("DDR SDRAM accesses char type Error:102!\n\r");
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if (REG8(DDR_SDRAM_BASE_ADDR + 103) != 0x78)
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if (REG8(DDR_SDRAM_BASE_ADDR + 103) != 0x78)
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print ("DDR SDRAM accesses char type Error:103!\n\r");
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print ("DDR SDRAM accesses char type Error:103!\n\r");
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for (i=0;i<64;i++) {
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for (i=0;i<64;i++) {
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REG8(DDR_SDRAM_BASE_ADDR + i) = i;
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REG8(DDR_SDRAM_BASE_ADDR + i) = i;
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}
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}
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for (i=0;i<64;i++) {
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for (i=0;i<64;i++) {
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REG8(0x3900+i) = REG8(DDR_SDRAM_BASE_ADDR + i);
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REG8(0x3900+i) = REG8(DDR_SDRAM_BASE_ADDR + i);
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}
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}
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print ("DDR SDRAM sample test done.\n\r");
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print ("DDR SDRAM sample test done.\n\r");
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}
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}
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/*$$EXTERNAL EXEPTIONS*/
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/*$$EXTERNAL EXEPTIONS*/
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/******************************************************************************/
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/******************************************************************************/
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/* E X T E R N A L E X E P T I O N S */
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/* E X T E R N A L E X E P T I O N S */
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/******************************************************************************/
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/******************************************************************************/
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void external_exeption()
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void external_exeption()
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{
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{
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REG uint8 i;
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REG uint8 i;
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REG uint32 PicSr,sr;
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REG uint32 PicSr,sr;
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}
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}
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/*$$MAIN*/
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/*$$MAIN*/
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/******************************************************************************/
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/******************************************************************************/
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/* */
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/* */
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/* M A I N P R O G R A M */
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/* M A I N P R O G R A M */
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/* */
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/* */
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/******************************************************************************/
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/******************************************************************************/
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void Start()
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void Start()
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{
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{
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uint32 i;
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uint32 i;
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uint8 str[9];
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uint8 str[9];
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// Configure GPIO
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// Configure GPIO
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REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs
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REG32(GPIO_BASE + RGPIO_OE) = 0xff; // bit0-7 = outputs, bit8-31 = inputs
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REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO
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REG32(GPIO_BASE + RGPIO_INTE) = 0x0; // Disable interrupts from GPIO
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print("\n\r\n\t");
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print("\n\r\n\t");
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print("==OpenRisc 1200 SOC==\n\r\n");
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print("==OpenRisc 1200 SOC==\n\r\n");
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GPIO_Write(~0x0);
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GPIO_Write(~0x0);
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print("\n\r");
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print("\n\r");
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print("SD Card Bootloader, v0.2\n\r");
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print("SD Card Bootloader, v0.2\n\r");
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print("Xianfeng Zeng, 2009 SA\n\r");
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print("Xianfeng Zeng, 2009 SA\n\r");
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print("Xianfeng@opencores.org\n\r");
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print("Xianfeng@opencores.org\n\r");
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print("http://www.opencores.org/project,or1k_soc_on_altera_embedded_dev_kit\n\r");
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print("http://www.opencores.org/project,or1k_soc_on_altera_embedded_dev_kit\n\r");
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print("\n\r");
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print("\n\r");
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print("System Clock: 30MHz\n\r\n");
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print("System Clock: 30MHz\n\r\n");
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print("DDR SDRAM Base Address: 0x00000000 - 32MB\n\r");
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print("DDR SDRAM Base Address: 0x00000000 - 32MB\n\r");
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print("Ethernet Base Address: 0x20000000 IRQ 4\n\r");
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print("Ethernet Base Address: 0x20000000 IRQ 4\n\r");
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print("UART Base Address: 0x30000000 IRQ 2\n\r");
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print("UART Base Address: 0x30000000 IRQ 2\n\r");
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print("GPIO Base Address: 0x40000000 IRQ 3\n\r");
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print("GPIO Base Address: 0x40000000 IRQ 3\n\r");
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print("SD Card Base Address: 0x50000000\n\r");
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print("SD Card Base Address: 0x50000000\n\r");
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print("SRAM Base Address: 0xF0000000 - 16KB\n\r");
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print("SRAM Base Address: 0xF0000000 - 16KB\n\r");
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print("\r\n\n");
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print("\r\n\n");
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print("Init SD Card:");
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print("Init SD Card:");
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1; /* reset spiMaster */
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x1; /* reset spiMaster */
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do_sleep();
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do_sleep();
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x0;
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REG8(SD_BASE_ADD + SD_TRANS_CTRL_REG) = 0x0;
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if (spiMaster_init() == 0) {
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if (spiMaster_init() == 0) {
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print("Passed!\n\r");
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print("Passed!\n\r");
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} else {
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} else {
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print("Failed!\n\r");
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print("Failed!\n\r");
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}
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}
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ddr_sdram_sample_test();
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ddr_sdram_sample_test();
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copy_sd2ddr();
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copy_sd2ddr();
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|
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GPIO_Write(~0x1);
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GPIO_Write(~0x1);
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print("\n\r");
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print("\n\r");
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print("Jump to DDR SDRAM: 0x100\n\r");
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print("Jump to DDR SDRAM: 0x100\n\r");
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jumpToRAM();
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jumpToRAM();
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|
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print("Should not get here!!:\n\r");
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print("Should not get here!!:\n\r");
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while(TRUE) {
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while(TRUE) {
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do_sleep();
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do_sleep();
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putc('.');
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or1k_putc('.');
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GPIO_Write(~0x0); // Test finished
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GPIO_Write(~0x0); // Test finished
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do_sleep();
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do_sleep();
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GPIO_Write(~0x1);
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GPIO_Write(~0x1);
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do_sleep();
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do_sleep();
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GPIO_Write(~0x2);
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GPIO_Write(~0x2);
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do_sleep();
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do_sleep();
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GPIO_Write(~0x4);
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GPIO_Write(~0x4);
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do_sleep();
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do_sleep();
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GPIO_Write(~0x8);
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GPIO_Write(~0x8);
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|
|
if (i == 39) {
|
if (i == 39) {
|
print("\n\r");
|
print("\n\r");
|
i = 0;
|
i = 0;
|
} else
|
} else
|
i++;
|
i++;
|
}
|
}
|
}
|
}
|
|
|
|
|
