`include "../../../rtl/verilog/gfx/gfx_line.v"
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`include "../../../rtl/verilog/gfx/gfx_line.v"
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module line_bench();
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module line_bench();
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reg clk_i;
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reg clk_i;
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reg rst_i;
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reg rst_i;
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reg [15:0] pixel0_x_i;
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reg [15:0] pixel0_x_i;
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reg [15:0] pixel1_x_i;
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reg [15:0] pixel1_x_i;
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reg [15:0] pixel0_y_i;
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reg [15:0] pixel0_y_i;
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reg [15:0] pixel1_y_i;
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reg [15:0] pixel1_y_i;
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reg [15:0] delta_major_i;
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reg [15:0] delta_major_i;
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reg [15:0] delta_minor_i;
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reg [15:0] delta_minor_i;
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reg draw_line_i;
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reg draw_line_i;
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reg read_pixel_i;
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reg read_pixel_i;
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reg x_major_i;
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reg x_major_i;
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reg minor_slope_positive_i;
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reg minor_slope_positive_i;
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wire busy_o;
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wire busy_o;
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wire [15:0] major_o;
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wire [15:0] major_o;
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wire [15:0] minor_o;
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wire [15:0] minor_o;
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initial begin
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initial begin
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$dumpfile("line.vcd");
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$dumpfile("line.vcd");
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$dumpvars(0,line_bench);
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$dumpvars(0,line_bench);
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draw_line_i = 0;
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draw_line_i = 0;
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clk_i = 0;
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clk_i = 0;
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rst_i = 1;
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rst_i = 1;
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// timing
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// timing
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#2 rst_i = 0;
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#2 rst_i = 0;
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pixel0_x_i = 10;
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pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 2;
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delta_major_i = 2;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#30 rst_i = 1;
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#30 rst_i = 1;
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#2 rst_i = 0;
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#2 rst_i = 0;
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pixel0_x_i = 10;
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pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 4;
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delta_major_i = 4;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#30 pixel0_x_i = 10;
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#30 pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 6;
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delta_major_i = 6;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#30 pixel0_x_i = 10;
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#30 pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 8;
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delta_major_i = 8;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#30 pixel0_x_i = 10;
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#30 pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 16;
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delta_major_i = 16;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#30 pixel0_x_i = 10;
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#30 pixel0_x_i = 10;
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pixel0_y_i = 10;
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pixel0_y_i = 10;
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pixel1_x_i = 20;
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pixel1_x_i = 20;
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delta_major_i = 32;
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delta_major_i = 32;
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delta_minor_i = 2;
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delta_minor_i = 2;
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#2 draw_line_i = 1;
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#2 draw_line_i = 1;
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#2 draw_line_i = 0;
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#2 draw_line_i = 0;
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#1000 $finish;
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#1000 $finish;
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end
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end
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always begin
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always begin
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#1 clk_i = ~clk_i;
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#1 clk_i = ~clk_i;
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end
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end
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bresenham_line bresenham(
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bresenham_line bresenham(
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.clk_i ( clk_i ),
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.clk_i ( clk_i ),
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.rst_i ( rst_i ),
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.rst_i ( rst_i ),
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.pixel0_x_i ( pixel0_x_i ),
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.pixel0_x_i ( pixel0_x_i ),
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.pixel0_y_i ( pixel0_y_i ),
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.pixel0_y_i ( pixel0_y_i ),
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.pixel1_x_i ( pixel1_x_i ),
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.pixel1_x_i ( pixel1_x_i ),
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.pixel1_y_i ( pixel1_y_i ),
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.pixel1_y_i ( pixel1_y_i ),
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.x_major_i ( x_major_i ),
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.x_major_i ( x_major_i ),
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.minor_slope_positive_i ( minor_slope_positive_i ),
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.minor_slope_positive_i ( minor_slope_positive_i ),
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.delta_minor_i ( delta_minor_i ),
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.delta_minor_i ( delta_minor_i ),
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.delta_major_i ( delta_major_i ),
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.delta_major_i ( delta_major_i ),
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.draw_line_i ( draw_line_i ),
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.draw_line_i ( draw_line_i ),
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.read_pixel_i ( read_pixel_i ),
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.read_pixel_i ( read_pixel_i ),
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.busy_o ( busy_o ),
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.busy_o ( busy_o ),
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.major_o ( major_o ),
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.major_o ( major_o ),
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.minor_o ( minor_o )
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.minor_o ( minor_o )
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);
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);
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endmodule
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endmodule
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