`include "../../../rtl/verilog/gfx/gfx_renderer.v"
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`include "../../../rtl/verilog/gfx/gfx_renderer.v"
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`include "../../../rtl/verilog/gfx/gfx_color.v"
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`include "../../../rtl/verilog/gfx/gfx_color.v"
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module render_bench();
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module render_bench();
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reg clk_i;
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reg clk_i;
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reg rst_i;
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reg rst_i;
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// Render target information, used for checking out of bounds and stride when writing pixels
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// Render target information, used for checking out of bounds and stride when writing pixels
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reg [31:2] target_base_i;
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reg [31:2] target_base_i;
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reg [15:0] target_size_x_i;
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reg [15:0] target_size_x_i;
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reg [15:0] target_size_y_i;
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reg [15:0] target_size_y_i;
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reg [1:0] color_depth_i;
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reg [1:0] color_depth_i;
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reg [15:0] pixel_x_i;
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reg [15:0] pixel_x_i;
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reg [15:0] pixel_y_i;
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reg [15:0] pixel_y_i;
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reg [31:0] color_i;
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reg [31:0] color_i;
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reg write_i;
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reg write_i;
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wire write_o;
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wire write_o;
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// wire registers connected to the wbm
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// wire registers connected to the wbm
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wire [31:2] render_addr_o;
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wire [31:2] render_addr_o;
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wire [3:0] render_sel_o;
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wire [3:0] render_sel_o;
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wire [31:0] render_dat_o;
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wire [31:0] render_dat_o;
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// TODO add ack signals
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// TODO add ack signals
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wire ack_o;
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wire ack_o;
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reg ack_i;
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reg ack_i;
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initial begin
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initial begin
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$dumpfile("render.vcd");
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$dumpfile("render.vcd");
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$dumpvars(0,render_bench);
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$dumpvars(0,render_bench);
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// init values
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// init values
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clk_i = 1;
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clk_i = 1;
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rst_i = 1;
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rst_i = 1;
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target_base_i = 0;
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target_base_i = 0;
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target_size_x_i = 640;
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target_size_x_i = 640;
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target_size_y_i = 480;
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target_size_y_i = 480;
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color_depth_i = 2'b01;
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color_depth_i = 2'b01;
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pixel_x_i = 4;
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pixel_x_i = 4;
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pixel_y_i = 2;
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pixel_y_i = 2;
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color_i = 0;
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color_i = 0;
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write_i = 0;
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write_i = 0;
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ack_i = 0;
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ack_i = 0;
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//timing
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//timing
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#4 rst_i =0;
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#4 rst_i =0;
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#16 write_i = 1;
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#16 write_i = 1;
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#2 write_i = 0;
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#2 write_i = 0;
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#2 write_i = 1;
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#2 write_i = 1;
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#2 write_i = 0;
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#2 write_i = 0;
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// end sim
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// end sim
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#100 $finish;
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#100 $finish;
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end
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end
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always begin
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always begin
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#1 clk_i = ~clk_i;
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#1 clk_i = ~clk_i;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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ack_i <= #1 write_o;
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ack_i <= #1 write_o;
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end
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end
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gfx_renderer render(
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gfx_renderer render(
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.clk_i (clk_i),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.rst_i (rst_i),
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.target_base_i (target_base_i),
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.target_base_i (target_base_i),
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.target_size_x_i (target_size_x_i),
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.target_size_x_i (target_size_x_i),
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.target_size_y_i (target_size_y_i),
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.target_size_y_i (target_size_y_i),
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.color_depth_i (color_depth_i),
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.color_depth_i (color_depth_i),
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.pixel_x_i (pixel_x_i),
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.pixel_x_i (pixel_x_i),
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.pixel_y_i (pixel_y_i),
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.pixel_y_i (pixel_y_i),
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.color_i (color_i),
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.color_i (color_i),
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.render_addr_o (render_addr_o),
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.render_addr_o (render_addr_o),
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.render_sel_o (render_sel_o),
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.render_sel_o (render_sel_o),
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.render_dat_o (render_dat_o),
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.render_dat_o (render_dat_o),
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.ack_o (ack_o),
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.ack_o (ack_o),
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.ack_i (ack_i),
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.ack_i (ack_i),
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.write_i (write_i),
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.write_i (write_i),
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.write_o (write_o)
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.write_o (write_o)
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);
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);
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endmodule
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endmodule
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