`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
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`include "../../../rtl/verilog/gfx/gfx_wbm_read_arbiter.v"
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module arbiter_bench();
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module arbiter_bench();
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// Clock
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// Clock
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reg clk_i; // master clock reg
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reg clk_i; // master clock reg
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// Interface against the wbm read module
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// Interface against the wbm read module
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wire master_busy_o;
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wire master_busy_o;
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wire read_request_o;
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wire read_request_o;
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wire [31:2] addr_o;
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wire [31:2] addr_o;
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wire [3:0] sel_o;
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wire [3:0] sel_o;
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reg [31:0] dat_i;
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reg [31:0] dat_i;
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reg ack_i;
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reg ack_i;
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// Interface against masters (fragment processor)
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// Interface against masters (fragment processor)
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reg m0_read_request_i;
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reg m0_read_request_i;
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reg [31:2] m0_addr_i;
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reg [31:2] m0_addr_i;
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reg [3:0] m0_sel_i;
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reg [3:0] m0_sel_i;
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wire [31:0] m0_dat_o;
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wire [31:0] m0_dat_o;
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wire m0_ack_o;
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wire m0_ack_o;
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// Interface against masters (blender)
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// Interface against masters (blender)
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reg m1_read_request_i;
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reg m1_read_request_i;
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reg [31:2] m1_addr_i;
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reg [31:2] m1_addr_i;
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reg [3:0] m1_sel_i;
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reg [3:0] m1_sel_i;
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wire [31:0] m1_dat_o;
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wire [31:0] m1_dat_o;
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wire m1_ack_o;
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wire m1_ack_o;
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initial begin
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initial begin
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$dumpfile("arbiter.vcd");
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$dumpfile("arbiter.vcd");
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$dumpvars(0,arbiter_bench);
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$dumpvars(0,arbiter_bench);
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// init values
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// init values
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clk_i = 0;
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clk_i = 0;
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dat_i = 32'h12345678;
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dat_i = 32'h12345678;
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ack_i = 0;
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ack_i = 0;
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m0_read_request_i = 0;
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m0_read_request_i = 0;
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m0_addr_i = 10;
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m0_addr_i = 10;
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m0_sel_i = 0;
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m0_sel_i = 0;
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m1_read_request_i = 0;
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m1_read_request_i = 0;
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m1_addr_i = 20;
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m1_addr_i = 20;
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m1_sel_i = 8;
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m1_sel_i = 8;
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#10 m0_read_request_i = 1;
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#10 m0_read_request_i = 1;
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#10 m0_read_request_i = 0;
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#10 m0_read_request_i = 0;
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#10 m1_read_request_i = 1;
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#10 m1_read_request_i = 1;
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#10 m1_read_request_i = 0;
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#10 m1_read_request_i = 0;
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#10 m1_read_request_i = 1;
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#10 m1_read_request_i = 1;
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m0_read_request_i = 1;
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m0_read_request_i = 1;
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#10 m1_read_request_i = 0;
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#10 m1_read_request_i = 0;
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#10 m0_read_request_i = 0;
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#10 m0_read_request_i = 0;
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//timing
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//timing
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#100 $finish;
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#100 $finish;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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ack_i <= #1 read_request_o;
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ack_i <= #1 read_request_o;
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end
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end
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always begin
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always begin
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#1 clk_i = ~clk_i;
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#1 clk_i = ~clk_i;
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end
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end
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gfx_wbm_read_arbiter arbiter(
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gfx_wbm_read_arbiter arbiter(
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.master_busy_o (master_busy_o),
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.master_busy_o (master_busy_o),
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// Interface against the wbm read module
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// Interface against the wbm read module
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.read_request_o (read_request_o),
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.read_request_o (read_request_o),
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.addr_o (addr_o),
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.addr_o (addr_o),
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.sel_o (sel_o),
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.sel_o (sel_o),
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.dat_i (dat_i),
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.dat_i (dat_i),
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.ack_i (ack_i),
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.ack_i (ack_i),
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// Interface against masters (fragment processor)
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// Interface against masters (fragment processor)
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.m0_read_request_i (m0_read_request_i),
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.m0_read_request_i (m0_read_request_i),
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.m0_addr_i (m0_addr_i),
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.m0_addr_i (m0_addr_i),
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.m0_sel_i (m0_sel_i),
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.m0_sel_i (m0_sel_i),
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.m0_dat_o (m0_dat_o),
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.m0_dat_o (m0_dat_o),
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.m0_ack_o (m0_ack_o),
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.m0_ack_o (m0_ack_o),
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// Interface against masters (blender)
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// Interface against masters (blender)
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.m1_read_request_i (m1_read_request_i),
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.m1_read_request_i (m1_read_request_i),
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.m1_addr_i (m1_addr_i),
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.m1_addr_i (m1_addr_i),
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.m1_sel_i (m1_sel_i),
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.m1_sel_i (m1_sel_i),
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.m1_dat_o (m1_dat_o),
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.m1_dat_o (m1_dat_o),
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.m1_ack_o (m1_ack_o)
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.m1_ack_o (m1_ack_o)
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);
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);
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endmodule
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endmodule
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