`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
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`include "../../../rtl/verilog/gfx/gfx_wbm_write.v"
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`include "../../../rtl/verilog/gfx/basic_fifo.v"
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`include "../../../rtl/verilog/gfx/basic_fifo.v"
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module wbm_w_bench();
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module wbm_w_bench();
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// wishbone signals
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// wishbone signals
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reg clk_i; // master clock reg
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reg clk_i; // master clock reg
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reg rst_i; // synchronous active high reset
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reg rst_i; // synchronous active high reset
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wire cyc_o; // cycle wire
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wire cyc_o; // cycle wire
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wire stb_o; // strobe output
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wire stb_o; // strobe output
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wire [ 2:0] cti_o; // cycle type id
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wire [ 2:0] cti_o; // cycle type id
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wire [ 1:0] bte_o; // burst type extension
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wire [ 1:0] bte_o; // burst type extension
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wire we_o; // write enable wire
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wire we_o; // write enable wire
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wire [31:0] adr_o; // address wire
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wire [31:0] adr_o; // address wire
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wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
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wire [ 3:0] sel_o; // byte select wires (only 32bits accesses are supported)
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reg ack_i; // wishbone cycle acknowledge
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reg ack_i; // wishbone cycle acknowledge
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reg err_i; // wishbone cycle error
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reg err_i; // wishbone cycle error
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wire [31:0] dat_o; // wishbone data out
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wire [31:0] dat_o; // wishbone data out
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wire sint_o; // non recoverable error, interrupt host
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wire sint_o; // non recoverable error, interrupt host
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// Renderer stuff
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// Renderer stuff
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reg write_i;
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reg write_i;
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wire ack_o;
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wire ack_o;
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reg [31:2] render_addr_i;
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reg [31:2] render_addr_i;
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reg [3:0] render_sel_i;
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reg [3:0] render_sel_i;
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reg [31:0] render_dat_i;
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reg [31:0] render_dat_i;
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initial begin
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initial begin
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$dumpfile("wbm_w.vcd");
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$dumpfile("wbm_w.vcd");
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$dumpvars(0,wbm_w_bench);
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$dumpvars(0,wbm_w_bench);
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// init values
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// init values
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clk_i = 0;
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clk_i = 0;
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rst_i = 1;
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rst_i = 1;
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err_i = 0;
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err_i = 0;
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write_i = 0;
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write_i = 0;
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render_addr_i = 0;
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render_addr_i = 0;
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render_sel_i = 4'b1111;
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render_sel_i = 4'b1111;
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render_dat_i = 32'h12345678;
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render_dat_i = 32'h12345678;
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#2 rst_i = 0;
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#2 rst_i = 0;
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//timing
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//timing
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# 10 write_i = 1;
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# 10 write_i = 1;
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# 2 write_i = 0;
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# 2 write_i = 0;
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# 4 write_i = 1;
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# 4 write_i = 1;
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# 2 write_i = 0;
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# 2 write_i = 0;
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// end sim
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// end sim
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#100 $finish;
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#100 $finish;
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end
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end
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always @(posedge clk_i)
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always @(posedge clk_i)
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begin
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begin
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ack_i <= #1 cyc_o & !ack_i;
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ack_i <= #1 cyc_o & !ack_i;
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end
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end
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always begin
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always begin
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#1 clk_i = ~clk_i;
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#1 clk_i = ~clk_i;
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end
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end
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gfx_wbm_write wbm_w(
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gfx_wbm_write wbm_w(
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// WB signals
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// WB signals
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.clk_i (clk_i),
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.clk_i (clk_i),
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.rst_i (rst_i),
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.rst_i (rst_i),
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.cyc_o (cyc_o),
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.cyc_o (cyc_o),
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.stb_o (stb_o),
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.stb_o (stb_o),
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.cti_o (cti_o),
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.cti_o (cti_o),
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.bte_o (bte_o),
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.bte_o (bte_o),
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.we_o (we_o),
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.we_o (we_o),
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.adr_o (adr_o),
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.adr_o (adr_o),
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.sel_o (sel_o),
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.sel_o (sel_o),
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.ack_i (ack_i),
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.ack_i (ack_i),
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.err_i (err_i),
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.err_i (err_i),
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.dat_o (dat_o),
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.dat_o (dat_o),
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.sint_o (sint_o),
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.sint_o (sint_o),
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// Control signals
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// Control signals
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.write_i (write_i),
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.write_i (write_i),
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.ack_o (ack_o),
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.ack_o (ack_o),
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.render_addr_i (render_addr_i),
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.render_addr_i (render_addr_i),
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.render_sel_i (render_sel_i),
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.render_sel_i (render_sel_i),
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.render_dat_i (render_dat_i)
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.render_dat_i (render_dat_i)
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);
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);
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endmodule
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endmodule
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