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----------------------------------------------------------------------------------
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-- Company:
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-- Engineer: Joao Carlos Nunes Bittencourt
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-- Engineer:
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----------------------------------------------------------------------------------
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--
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-- Create Date: 13:18:18 03/06/2012
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-- Create Date: 15:02:04 04/19/2012
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----------------------------------------------------------------------------------
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-- Design Name: Multiplexer 3 x 1
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-- Design Name: 4x1 Multiplexer
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-- Module Name: mux4x1 - Multiplex
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-- Module Name: mux4x1 - behavioral
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-- Project Name:
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----------------------------------------------------------------------------------
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-- Target Devices:
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-- Project Name: 16-bit uRISC Processor
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-- Tool versions:
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----------------------------------------------------------------------------------
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision:
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-- Revision 0.01 - File Created
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-- 1.0 - File Created
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-- Additional Comments:
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-- 2.0 - Project refactoring
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--
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--
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----------------------------------------------------------------------------------
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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entity mux4x1 is
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entity mux4x1 is
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generic (
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generic (
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WIDTH : integer := 16 );
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WIDTH : integer := 16 );
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port (
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port (
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sink_a : in std_logic_vector (WIDTH-1 downto 0);
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sink_a : in std_logic_vector (WIDTH-1 downto 0);
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sink_b : in std_logic_vector (WIDTH-1 downto 0);
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sink_b : in std_logic_vector (WIDTH-1 downto 0);
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sink_c : in std_logic_vector (WIDTH-1 downto 0);
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sink_c : in std_logic_vector (WIDTH-1 downto 0);
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sink_d : in std_logic_vector (WIDTH-1 downto 0);
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sink_d : in std_logic_vector (WIDTH-1 downto 0);
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sink_sel : in std_logic_vector (1 downto 0);
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sink_sel : in std_logic_vector (1 downto 0);
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src_data : out std_logic_vector (WIDTH-1 downto 0) );
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src_data : out std_logic_vector (WIDTH-1 downto 0) );
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end mux4x1;
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end mux4x1;
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architecture Multiplex of mux4x1 is
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architecture Multiplex of mux4x1 is
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begin
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begin
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process(sink_sel, sink_a, sink_b, sink_c)
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process(sink_sel, sink_a, sink_b, sink_c)
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begin
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begin
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case sink_sel is
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case sink_sel is
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when "00" => src_data <= sink_a;
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when "00" => src_data <= sink_a;
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when "01" => src_data <= sink_b;
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when "01" => src_data <= sink_b;
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when "10" => src_data <= sink_c;
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when "10" => src_data <= sink_c;
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when "11" => src_data <= sink_d;
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when "11" => src_data <= sink_d;
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when others => src_data <= (others => '0');
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when others => src_data <= (others => '0');
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end case;
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end case;
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end process;
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end process;
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end Multiplex;
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end Multiplex;
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