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----------------------------------------------------------------------------------
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-- Engineer: Joao Carlos Nunes Bittencourt
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----------------------------------------------------------------------------------
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-- Create Date: 13:18:18 03/06/2012
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----------------------------------------------------------------------------------
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-- Design Name: Program Counter Adder
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-- Module Name: pc_adder - behavioral
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----------------------------------------------------------------------------------
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-- Project Name: 16-bit uRISC Processor
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----------------------------------------------------------------------------------
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-- Revision:
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-- 1.0 - File Created
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-- 2.0 - Project refactoring
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--
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----------------------------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_arith.all;
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use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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entity pc_adder is
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entity pc_adder is
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generic (
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generic (
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DATA_WIDTH : integer := 16;
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DATA_WIDTH : integer := 16;
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INC_PLUS : integer := 1
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INC_PLUS : integer := 1
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);
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);
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port (
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port (
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sink_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
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sink_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
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src_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
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src_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
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);
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);
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end pc_adder;
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end pc_adder;
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architecture behavioral of pc_adder is
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architecture behavioral of pc_adder is
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begin
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begin
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process(sink_pc)
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process(sink_pc)
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variable counter : std_logic_vector(DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH); -- verify if it is necessary
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variable counter : std_logic_vector(DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH); -- verify if it is necessary
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begin
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begin
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counter := sink_pc + INC_PLUS;
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counter := sink_pc + INC_PLUS;
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src_pc <= counter;
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src_pc <= counter;
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end process;
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end process;
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end behavioral;
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end behavioral;
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