----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Engineer: Joao Carlos Nunes Bittencourt
|
-- Engineer: Joao Carlos Nunes Bittencourt
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Create Date: 13:18:18 03/06/2012
|
-- Create Date: 13:18:18 03/06/2012
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Design Name: Program Counter
|
-- Design Name: Program Counter
|
-- Module Name: fetch_dff - behavioral
|
-- Module Name: program_counter - behavioral
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Project Name: 16-bit uRISC Processor
|
-- Project Name: 16-bit uRISC Processor
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
-- Revision:
|
-- Revision:
|
-- 1.0 - File Created
|
-- 1.0 - File Created
|
-- 2.0 - Project refactoring
|
-- 2.0 - Project refactoring
|
--
|
--
|
----------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_arith.all;
|
use ieee.std_logic_arith.all;
|
|
|
entity program_counter is
|
entity program_counter is
|
generic(
|
generic(
|
DATA_WIDTH : integer := 16
|
DATA_WIDTH : integer := 16
|
);
|
);
|
port (
|
port (
|
sink_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
sink_pc : in std_logic_vector(DATA_WIDTH-1 downto 0);
|
clk : in std_logic;
|
clk : in std_logic;
|
enable : in std_logic;
|
enable : in std_logic;
|
reset : in std_logic;
|
reset : in std_logic;
|
src_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
|
src_pc : out std_logic_vector(DATA_WIDTH-1 downto 0)
|
);
|
);
|
|
|
end program_counter;
|
end program_counter;
|
|
|
architecture behavioral of program_counter is
|
architecture behavioral of program_counter is
|
begin
|
begin
|
process(clk,enable)
|
process(clk,enable)
|
variable counter : std_logic_vector (DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH);
|
variable counter : std_logic_vector (DATA_WIDTH-1 downto 0) := conv_std_logic_vector(0,DATA_WIDTH);
|
begin
|
begin
|
src_pc <= counter;
|
src_pc <= counter;
|
if(clk='1' and clk'event) then
|
if(clk='1' and clk'event) then
|
if(reset = '1') then
|
if(reset = '1') then
|
counter := conv_std_logic_vector(0,DATA_WIDTH);
|
counter := conv_std_logic_vector(0,DATA_WIDTH);
|
else
|
else
|
if(enable = '1') then
|
if(enable = '1') then
|
counter := sink_pc;
|
counter := sink_pc;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
end behavioral;
|
end behavioral;
|
|
|