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[/] [pairing/] [trunk/] [testbench/] [test_f3_add.v] - Diff between revs 4 and 22
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Rev 4 |
Rev 22 |
`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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module test_f3_add;
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module test_f3_add;
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// Inputs
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// Inputs
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reg [1:0] A;
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reg [1:0] A;
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reg [1:0] B;
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reg [1:0] B;
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// Outputs
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// Outputs
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wire [1:0] C;
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wire [1:0] C;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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f3_add uut (
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f3_add uut (
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.A(A),
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.A(A),
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.B(B),
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.B(B),
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.C(C)
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.C(C)
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);
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);
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task check;
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task check;
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begin
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begin
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#10;
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#10;
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if ((A+B) % 3 != C)
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if ((A+B) % 3 != C)
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begin
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begin
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$display("Error"); $finish;
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$display("Error"); $finish;
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end
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end
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end
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end
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endtask
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endtask
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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A = 0;
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A = 0;
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B = 0;
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B = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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A = 0; B = 0; check;
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A = 0; B = 0; check;
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A = 0; B = 1; check;
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A = 0; B = 1; check;
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A = 0; B = 2; check;
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A = 0; B = 2; check;
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A = 1; B = 0; check;
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A = 1; B = 0; check;
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A = 1; B = 1; check;
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A = 1; B = 1; check;
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A = 1; B = 2; check;
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A = 1; B = 2; check;
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A = 2; B = 0; check;
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A = 2; B = 0; check;
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A = 2; B = 1; check;
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A = 2; B = 1; check;
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A = 2; B = 2; check;
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A = 2; B = 2; check;
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$finish;
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$finish;
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end
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end
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endmodule
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endmodule
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