URL
https://opencores.org/ocsvn/pairing/pairing/trunk
[/] [pairing/] [trunk/] [testbench/] [test_f3m_inv.v] - Diff between revs 7 and 22
Go to most recent revision |
Only display areas with differences |
Details |
Blame |
View Log
| Rev 7 |
Rev 22 |
`timescale 1ns / 1ps
|
`timescale 1ns / 1ps
|
`define CLOCK_PERIOD 10
|
`define CLOCK_PERIOD 10
|
module test_f3m_inv;
|
module test_f3m_inv;
|
|
|
// Inputs
|
// Inputs
|
reg [193:0] A;
|
reg [193:0] A;
|
reg clk;
|
reg clk;
|
reg reset;
|
reg reset;
|
|
|
// Outputs
|
// Outputs
|
wire [193:0] C;
|
wire [193:0] C;
|
wire done;
|
wire done;
|
|
|
// Instantiate the Unit Under Test (UUT)
|
// Instantiate the Unit Under Test (UUT)
|
f3m_inv uut (
|
f3m_inv uut (
|
.A(A),
|
.A(A),
|
.clk(clk),
|
.clk(clk),
|
.reset(reset),
|
.reset(reset),
|
.C(C),
|
.C(C),
|
.done(done)
|
.done(done)
|
);
|
);
|
|
|
always #`CLOCK_PERIOD clk = ~clk;
|
always #`CLOCK_PERIOD clk = ~clk;
|
|
|
initial begin
|
initial begin
|
// Initialize Inputs
|
// Initialize Inputs
|
A = 0;
|
A = 0;
|
clk = 0;
|
clk = 0;
|
reset = 0;
|
reset = 0;
|
|
|
// Wait 100 ns for global reset to finish
|
// Wait 100 ns for global reset to finish
|
#100;
|
#100;
|
|
|
// Add stimulus here
|
// Add stimulus here
|
A = 32'b10_01_01_10_01_00; // A = "x";
|
A = 32'b10_01_01_10_01_00; // A = "x";
|
@(negedge clk); reset = 1;
|
@(negedge clk); reset = 1;
|
@(negedge clk); reset = 0;
|
@(negedge clk); reset = 0;
|
#(200*2*`CLOCK_PERIOD);
|
#(200*2*`CLOCK_PERIOD);
|
if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) $display("Error!");
|
if (C != 192'h65450169824811252a919a8a02964184221a1562655252a9) $display("Error!");
|
$display("Good!"); $finish;
|
$display("Good!"); $finish;
|
end
|
end
|
|
|
endmodule
|
endmodule
|
|
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.