`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`include "../rtl/inc.v"
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`include "../rtl/inc.v"
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module test_f3m_mult3;
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module test_f3m_mult3;
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// Inputs
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// Inputs
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reg clk;
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reg clk;
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reg reset;
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reg reset;
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reg [`WIDTH:0] a0,b0,a1,b1,a2,b2,w0,w1,w2;
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reg [`WIDTH:0] a0,b0,a1,b1,a2,b2,w0,w1,w2;
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// Outputs
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// Outputs
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wire [`WIDTH:0] c0,c1,c2;
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wire [`WIDTH:0] c0,c1,c2;
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wire done;
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wire done;
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// Instantiate the Unit Under Test (UUT)
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// Instantiate the Unit Under Test (UUT)
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f3m_mult3 uut (
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f3m_mult3 uut (
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.clk(clk),
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.clk(clk),
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.reset(reset),
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.reset(reset),
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.a0(a0),
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.a0(a0),
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.b0(b0),
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.b0(b0),
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.c0(c0),
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.c0(c0),
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.a1(a1),
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.a1(a1),
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.b1(b1),
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.b1(b1),
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.c1(c1),
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.c1(c1),
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.a2(a2),
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.a2(a2),
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.b2(b2),
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.b2(b2),
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.c2(c2),
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.c2(c2),
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.done(done)
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.done(done)
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);
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);
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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clk = 0;
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clk = 0;
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reset = 0;
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reset = 0;
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a0 = 0;
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a0 = 0;
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b0 = 0;
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b0 = 0;
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a1 = 0;
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a1 = 0;
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b1 = 0;
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b1 = 0;
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a2 = 0;
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a2 = 0;
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b2 = 0;
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b2 = 0;
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// Wait 100 ns for global reset to finish
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// Wait 100 ns for global reset to finish
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#100;
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#100;
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// Add stimulus here
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// Add stimulus here
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a0 = 194'h2581921511a6952a4244918a069446a520480660152916412;
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a0 = 194'h2581921511a6952a4244918a069446a520480660152916412;
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a1 = 194'haa59080a98122082111a110a400642169102154006590a28;
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a1 = 194'haa59080a98122082111a110a400642169102154006590a28;
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a2 = 194'h90026a06416441992252a2820a2860269a094a0a06428285;
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a2 = 194'h90026a06416441992252a2820a2860269a094a0a06428285;
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b0 = 194'h158a5419212805158a941010a495a80966995599a660686a5;
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b0 = 194'h158a5419212805158a941010a495a80966995599a660686a5;
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b1 = 194'h115a25602090915a9086a1165169041652888086051510024;
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b1 = 194'h115a25602090915a9086a1165169041652888086051510024;
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b2 = 194'h191a5669201405a8589951644158119264522a6496809952;
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b2 = 194'h191a5669201405a8589951644158119264522a6496809952;
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w0 = 194'h145a548a114016289482246816a449911942a088540160102;
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w0 = 194'h145a548a114016289482246816a449911942a088540160102;
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w1 = 194'h220652040980466020556941115a5085a5904a60118605858;
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w1 = 194'h220652040980466020556941115a5085a5904a60118605858;
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w2 = 194'h280a8885992001a950615026585a5592096891a9954506155;
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w2 = 194'h280a8885992001a950615026585a5592096891a9954506155;
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 1;
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@ (negedge clk); reset = 0;
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@ (negedge clk); reset = 0;
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@ (posedge done);
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@ (posedge done);
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#5;
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#5;
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if (c0 !== w0) $display("E");
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if (c0 !== w0) $display("E");
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if (c1 !== w1) $display("E");
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if (c1 !== w1) $display("E");
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if (c2 !== w2) $display("E");
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if (c2 !== w2) $display("E");
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$finish;
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$finish;
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end
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end
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always #5 clk = ~clk;
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always #5 clk = ~clk;
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endmodule
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endmodule
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