<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
|
<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
|
<html><head><meta http-equiv="Content-Type" content="text/html;charset=iso-8859-1">
|
<title>DACU</title>
|
<title>DACU</title>
|
<link href="doxygen.css" rel="stylesheet" type="text/css">
|
<link href="doxygen.css" rel="stylesheet" type="text/css">
|
</head><body>
|
</head><body>
|
<!-- Generated by Doxygen 1.2.16 -->
|
<!-- Generated by Doxygen 1.2.16 -->
|
<center>
|
<center>
|
<a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center>
|
<a class="qindex" href="main.html">Main Page</a> <a class="qindex" href="modules.html">Modules</a> <a class="qindex" href="pages.html">Related Pages</a> </center>
|
<hr><h1>DACU<br>
|
<hr><h1>DACU<br>
|
<small>
|
<small>
|
[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
|
[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
|
</h1><table border=0 cellpadding=0 cellspacing=0>
|
</h1><table border=0 cellpadding=0 cellspacing=0>
|
</table>
|
</table>
|
<dl compact><dt><b>
|
<dl compact><dt><b>
|
Overview</b><dd>
|
Overview</b><dd>
|
The Data Address Calculation Unit offers a unified read and write access over the concatenated RF, IOF and DM space, that is, over the Unified Memory (UM) space. <br>
|
The Data Address Calculation Unit offers a unified read and write access over the concatenated RF, IOF and DM space, that is, over the Unified Memory (UM) space. <br>
|
Loads and stores operate in the UM space. They use the DACU in order to translate the Unified Memory address into a RF, IOF or DM address. <br>
|
Loads and stores operate in the UM space. They use the DACU in order to translate the Unified Memory address into a RF, IOF or DM address. <br>
|
The DACU takes requests to read or write into UM space, translates the UM address into RF, IOF or DM address, and transparently places requests to read or write the specific hardware resource (RF, IOF or DM) that corresponds to the given UM address. <br>
|
The DACU takes requests to read or write into UM space, translates the UM address into RF, IOF or DM address, and transparently places requests to read or write the specific hardware resource (RF, IOF or DM) that corresponds to the given UM address. <br>
|
</dl><dl compact><dt><b>
|
</dl><dl compact><dt><b>
|
Reading DACU</b><dd>
|
Reading DACU</b><dd>
|
<br>
|
<br>
|
<div align="center">
|
<div align="center">
|
<img src="pavr_hwres_dacu_01.gif" alt="pavr_hwres_dacu_01.gif">
|
<img src="pavr_hwres_dacu_01.gif" alt="pavr_hwres_dacu_01.gif">
|
</div>
|
</div>
|
<br>
|
<br>
|
DACU read <b>requests</b>: <ul>
|
DACU read <b>requests</b>: <ul>
|
<li> pavr_s5_x_dacurd_rq <br>
|
<li> pavr_s5_x_dacurd_rq <br>
|
Needed by loads from address given by X pointer register. <li> pavr_s5_y_dacurd_rq <br>
|
Needed by loads from address given by X pointer register. <li> pavr_s5_y_dacurd_rq <br>
|
Needed by loads from address given by Y pointer register. <li> pavr_s5_z_dacurd_rq <br>
|
Needed by loads from address given by Y pointer register. <li> pavr_s5_z_dacurd_rq <br>
|
Needed by loads from address given by Z pointer register. <li> pavr_s5_sp_dacurd_rq <br>
|
Needed by loads from address given by Z pointer register. <li> pavr_s5_sp_dacurd_rq <br>
|
Needed by POP instruction. <li> pavr_s5_k16_dacurd_rq <br>
|
Needed by POP instruction. <li> pavr_s5_k16_dacurd_rq <br>
|
Needed by LDS instruction. <br>
|
Needed by LDS instruction. <br>
|
If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pchi8_dacurd_rq <br>
|
If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pchi8_dacurd_rq <br>
|
The higher 8 bits of the PC are loaded from the stack. <br>
|
The higher 8 bits of the PC are loaded from the stack. <br>
|
Needed by RET and RETI instructions. <li> pavr_s51_pcmid8_dacurd_rq <br>
|
Needed by RET and RETI instructions. <li> pavr_s51_pcmid8_dacurd_rq <br>
|
The middle 8 bits of the PC are loaded from the stack. <br>
|
The middle 8 bits of the PC are loaded from the stack. <br>
|
Needed by RET and RETI instructions. <li> pavr_s52_pclo8_dacurd_rq <br>
|
Needed by RET and RETI instructions. <li> pavr_s52_pclo8_dacurd_rq <br>
|
The lower 8 bits of the PC are loaded from the stack. <br>
|
The lower 8 bits of the PC are loaded from the stack. <br>
|
Needed by RET and RETI instructions. </ul>
|
Needed by RET and RETI instructions. </ul>
|
<br>
|
<br>
|
As a response to read requests, the DACU places read <b>requests</b> to RF, IOF or DM: <ul>
|
As a response to read requests, the DACU places read <b>requests</b> to RF, IOF or DM: <ul>
|
<li> pavr_s5_dacu_rfrd1_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmrd_rq </ul>
|
<li> pavr_s5_dacu_rfrd1_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmrd_rq </ul>
|
</dl><dl compact><dt><b>
|
</dl><dl compact><dt><b>
|
Writing DACU</b><dd>
|
Writing DACU</b><dd>
|
<br>
|
<br>
|
<div align="center">
|
<div align="center">
|
<img src="pavr_hwres_dacu_02.gif" alt="pavr_hwres_dacu_02.gif">
|
<img src="pavr_hwres_dacu_02.gif" alt="pavr_hwres_dacu_02.gif">
|
</div>
|
</div>
|
<br>
|
<br>
|
DACU write <b>requests</b>: <ul>
|
DACU write <b>requests</b>: <ul>
|
<li> pavr_s5_x_dacuwr_rq <br>
|
<li> pavr_s5_x_dacuwr_rq <br>
|
Needed by stores to address given by X pointer register. <li> pavr_s5_y_dacuwr_rq <br>
|
Needed by stores to address given by X pointer register. <li> pavr_s5_y_dacuwr_rq <br>
|
Needed by stores to address given by Y pointer register. <li> pavr_s5_z_dacuwr_rq <br>
|
Needed by stores to address given by Y pointer register. <li> pavr_s5_z_dacuwr_rq <br>
|
Needed by stores to address given by Z pointer register. <li> pavr_s5_sp_dacuwr_rq <br>
|
Needed by stores to address given by Z pointer register. <li> pavr_s5_sp_dacuwr_rq <br>
|
Needed by PUSH instruction. <br>
|
Needed by PUSH instruction. <br>
|
<li> pavr_s5_k16_dacuwr_rq <br>
|
<li> pavr_s5_k16_dacuwr_rq <br>
|
Needed by STS instruction. <br>
|
Needed by STS instruction. <br>
|
If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pclo8_dacuwr_rq <br>
|
If the controller has more than 64KB of Data Memory, the Unified Memory address is built by concatenating the RAMPD with the 16 bit constant. <li> pavr_s5_pclo8_dacuwr_rq <br>
|
The lower 8 bits of the PC are stored on the stack. <br>
|
The lower 8 bits of the PC are stored on the stack. <br>
|
Needed by CALL family instructions (CALL, RCALL, ICALL, EICALL, implicit interrupt CALL). <li> pavr_s51_pcmid8_dacuwr_rq <br>
|
Needed by CALL family instructions (CALL, RCALL, ICALL, EICALL, implicit interrupt CALL). <li> pavr_s51_pcmid8_dacuwr_rq <br>
|
The middle 8 bits of the PC are stored on the stack. <br>
|
The middle 8 bits of the PC are stored on the stack. <br>
|
Needed by CALL family instructions. <li> pavr_s52_pchi8_dacuwr_rq <br>
|
Needed by CALL family instructions. <li> pavr_s52_pchi8_dacuwr_rq <br>
|
The higher 8 bits of the PC are stored on the stack. <br>
|
The higher 8 bits of the PC are stored on the stack. <br>
|
Needed by CALL family instructions. </ul>
|
Needed by CALL family instructions. </ul>
|
<br>
|
<br>
|
As a response to write requests, the DACU places write <b>requests</b> to RF, IOF or DM, and BPU: <ul>
|
As a response to write requests, the DACU places write <b>requests</b> to RF, IOF or DM, and BPU: <ul>
|
<li> pavr_s5_dacu_rfwr_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmwr_rq <li> pavr_s5_dacust_bpr0wr_rq </ul>
|
<li> pavr_s5_dacu_rfwr_rq <li> pavr_s5_dacu_iof_rq <li> pavr_s5_dacu_dmwr_rq <li> pavr_s5_dacust_bpr0wr_rq </ul>
|
<br>
|
<br>
|
</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
|
</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
|
<a href="http://www.doxygen.org/index.html">
|
<a href="http://www.doxygen.org/index.html">
|
<img src="doxygen.png" alt="doxygen" align="middle" border=0
|
<img src="doxygen.png" alt="doxygen" align="middle" border=0
|
width=110 height=53></a>1.2.16 </small></address>
|
width=110 height=53></a>1.2.16 </small></address>
|
</body>
|
</body>
|
</html>
|
</html>
|
|
|
