-- <File header>
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-- <File header>
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-- Project
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-- Project
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- pAVR (pipelined AVR) is an 8 bit RISC controller, compatible with Atmel's
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- AVR core, but about 3x faster in terms of both clock frequency and MIPS.
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- The increase in speed comes from a relatively deep pipeline. The original
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- AVR core has only two pipeline stages (fetch and execute), while pAVR has
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-- 6 pipeline stages:
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-- 6 pipeline stages:
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-- 1. PM (read Program Memory)
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-- 1. PM (read Program Memory)
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-- 2. INSTR (load Instruction)
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-- 2. INSTR (load Instruction)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 3. RFRD (decode Instruction and read Register File)
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-- 4. OPS (load Operands)
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-- 4. OPS (load Operands)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 5. ALU (execute ALU opcode or access Unified Memory)
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-- 6. RFWR (write Register File)
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-- 6. RFWR (write Register File)
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-- Version
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-- Version
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-- 0.32
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-- 0.32
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-- Date
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-- Date
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-- 2002 August 07
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-- 2002 August 07
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-- Author
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-- Author
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-- Doru Cuturela, doruu@yahoo.com
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-- Doru Cuturela, doruu@yahoo.com
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-- License
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-- License
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-- This program is free software; you can redistribute it and/or modify
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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-- (at your option) any later version.
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-- This program is distributed in the hope that it will be useful,
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-- </File header>
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-- </File header>
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-- <File info>
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-- <File info>
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-- Test the Data Memory.
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-- Test the Data Memory.
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-- A trivial read-write test.
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-- A trivial read-write test.
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-- </File info>
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-- </File info>
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-- <File body>
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-- <File body>
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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library work;
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library work;
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use work.std_util.all;
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use work.std_util.all;
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use work.pavr_util.all;
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use work.pavr_util.all;
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use work.pavr_constants.all;
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use work.pavr_constants.all;
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entity test_pavr_dm is
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entity test_pavr_dm is
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end;
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end;
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architecture test_pavr_dm_arch of test_pavr_dm is
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architecture test_pavr_dm_arch of test_pavr_dm is
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signal clk, res: std_logic;
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signal clk, res: std_logic;
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-- Clock counter
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-- Clock counter
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signal cnt: std_logic_vector(7 downto 0);
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signal cnt: std_logic_vector(7 downto 0);
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-- DM connectivity
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-- DM connectivity
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signal pavr_dm_do : std_logic_vector(7 downto 0);
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signal pavr_dm_do : std_logic_vector(7 downto 0);
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signal pavr_dm_wr : std_logic;
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signal pavr_dm_wr : std_logic;
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signal pavr_dm_addr : std_logic_vector(pavr_dm_addr_w - 1 downto 0);
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signal pavr_dm_addr : std_logic_vector(pavr_dm_addr_w - 1 downto 0);
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signal pavr_dm_di : std_logic_vector(7 downto 0);
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signal pavr_dm_di : std_logic_vector(7 downto 0);
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-- Declare the Data Memory
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-- Declare the Data Memory
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component pavr_dm
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component pavr_dm
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port(
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port(
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pavr_dm_clk: in std_logic;
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pavr_dm_clk: in std_logic;
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pavr_dm_wr: in std_logic;
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pavr_dm_wr: in std_logic;
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pavr_dm_addr: in std_logic_vector(pavr_dm_addr_w - 1 downto 0);
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pavr_dm_addr: in std_logic_vector(pavr_dm_addr_w - 1 downto 0);
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pavr_dm_di: in std_logic_vector(7 downto 0);
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pavr_dm_di: in std_logic_vector(7 downto 0);
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pavr_dm_do: out std_logic_vector(7 downto 0)
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pavr_dm_do: out std_logic_vector(7 downto 0)
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);
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);
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end component;
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end component;
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for all: pavr_dm use entity work.pavr_dm(pavr_dm_arch);
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for all: pavr_dm use entity work.pavr_dm(pavr_dm_arch);
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begin
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begin
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-- Instantiate the Data Memory
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-- Instantiate the Data Memory
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pavr_dm_instance1: pavr_dm
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pavr_dm_instance1: pavr_dm
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port map(
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port map(
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clk,
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clk,
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pavr_dm_wr,
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pavr_dm_wr,
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pavr_dm_addr,
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pavr_dm_addr,
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pavr_dm_di,
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pavr_dm_di,
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pavr_dm_do
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pavr_dm_do
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);
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);
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generate_clock:
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generate_clock:
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process
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process
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begin
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begin
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clk <= '1';
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clk <= '1';
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wait for 50 ns;
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wait for 50 ns;
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clk <= '0';
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clk <= '0';
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wait for 50 ns;
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wait for 50 ns;
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end process generate_clock;
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end process generate_clock;
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generate_reset:
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generate_reset:
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process
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process
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begin
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begin
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res <= '0';
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res <= '0';
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wait for 100 ns;
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wait for 100 ns;
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res <= '1';
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res <= '1';
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wait for 110 ns;
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wait for 110 ns;
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res <= '0';
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res <= '0';
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wait for 1 ms;
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wait for 1 ms;
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end process generate_reset;
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end process generate_reset;
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test_main:
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test_main:
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process(clk, res,
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process(clk, res,
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cnt,
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cnt,
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pavr_dm_addr, pavr_dm_di
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pavr_dm_addr, pavr_dm_di
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)
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)
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begin
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begin
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if res='1' then
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if res='1' then
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-- Async reset
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-- Async reset
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cnt <= int_to_std_logic_vector(0, cnt'length);
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cnt <= int_to_std_logic_vector(0, cnt'length);
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elsif clk'event and clk='1' then
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elsif clk'event and clk='1' then
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-- Clock counter
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-- Clock counter
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cnt <= cnt+1;
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cnt <= cnt+1;
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-- Initialize inputs.
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-- Initialize inputs.
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pavr_dm_wr <= '0';
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pavr_dm_wr <= '0';
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pavr_dm_addr <= int_to_std_logic_vector(0, pavr_dm_addr'length);
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pavr_dm_addr <= int_to_std_logic_vector(0, pavr_dm_addr'length);
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pavr_dm_di <= int_to_std_logic_vector(0, pavr_dm_di'length);
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pavr_dm_di <= int_to_std_logic_vector(0, pavr_dm_di'length);
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case std_logic_vector_to_nat(cnt) is
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case std_logic_vector_to_nat(cnt) is
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-- TEST 1. Write DM.
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-- TEST 1. Write DM.
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when 3 =>
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when 3 =>
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pavr_dm_wr <= '1';
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pavr_dm_wr <= '1';
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pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
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pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
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pavr_dm_di <= int_to_std_logic_vector(16#A9#, pavr_dm_di'length);
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pavr_dm_di <= int_to_std_logic_vector(16#A9#, pavr_dm_di'length);
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-- TEST 2. Read DM.
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-- TEST 2. Read DM.
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when 4 =>
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when 4 =>
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pavr_dm_wr <= '0';
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pavr_dm_wr <= '0';
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pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
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pavr_dm_addr <= int_to_std_logic_vector(24, pavr_dm_addr'length);
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when others =>
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when others =>
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null;
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null;
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end case;
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end case;
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end if;
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end if;
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end process test_main;
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end process test_main;
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end;
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end;
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-- </File body>
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-- </File body>
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