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<title>SP port</title>
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<hr><h1>SP port<br>
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<hr><h1>SP port<br>
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<small>
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<small>
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[<a class="el" href="group__pavr__hwres__iof.html">IO File</a>]</small>
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[<a class="el" href="group__pavr__hwres__iof.html">IO File</a>]</small>
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<dl compact><dt><b>
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<dl compact><dt><b>
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SP port connectivity</b><dd>
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SP port connectivity</b><dd>
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<br>
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<img src="pavr_hwres_iof_sp_01.gif" alt="pavr_hwres_iof_sp_01.gif">
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<br>
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<br>
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This the stack pointer. <br>
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This the stack pointer. <br>
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It is 16 bits wide, being composed of two 8 bit registers, SPL and SPH. <br>
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It is 16 bits wide, being composed of two 8 bit registers, SPL and SPH. <br>
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The stack can reside anywhere in the Unified Memory space. That is, anywhere in the RF, IOF or DM. It can even begin, for example, in RF and continue in IOF. However, placing the stack pointer in the IOF is likely to be a programming error, as the IOF registers have dedicated functions. Quasi-random values from stack written into IOF could result, for example, in an unpredictably trigerring any interrupt, and in general, in unpredictable behavior of the controller. <br>
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The stack can reside anywhere in the Unified Memory space. That is, anywhere in the RF, IOF or DM. It can even begin, for example, in RF and continue in IOF. However, placing the stack pointer in the IOF is likely to be a programming error, as the IOF registers have dedicated functions. Quasi-random values from stack written into IOF could result, for example, in an unpredictably trigerring any interrupt, and in general, in unpredictable behavior of the controller. <br>
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</dl><dl compact><dt><b>
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</dl><dl compact><dt><b>
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Requests to this port</b><dd>
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Requests to this port</b><dd>
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<ul>
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<ul>
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<li>pavr_s5_inc_spwr_rq <br>
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<li>pavr_s5_inc_spwr_rq <br>
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Increment SP (SPH & SPL) with 1. <br>
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Increment SP (SPH & SPL) with 1. <br>
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Needed by POP.<li>pavr_s5_dec_spwr_rq <br>
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Needed by POP.<li>pavr_s5_dec_spwr_rq <br>
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Increment SP with 1. <br>
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Increment SP with 1. <br>
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Needed by PUSH.<li>pavr_s5_calldec_spwr_rq <br>
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Needed by PUSH.<li>pavr_s5_calldec_spwr_rq <br>
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Decrement SP with 1. <br>
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Decrement SP with 1. <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s51_calldec_spwr_rq <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s51_calldec_spwr_rq <br>
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Decrement SP with 1. <br>
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Decrement SP with 1. <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s52_calldec_spwr_rq <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s52_calldec_spwr_rq <br>
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Decrement SP with 1. <br>
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Decrement SP with 1. <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s5_retinc2_spwr_rq <br>
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Needed by RCALL, ICALL, EICALL, CALL, interrupt implicit CALL.<li>pavr_s5_retinc2_spwr_rq <br>
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Increment SP with 2. <br>
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Increment SP with 2. <br>
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Needed by RET, RETI.<li>pavr_s51_retinc_spwr_rq <br>
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Needed by RET, RETI.<li>pavr_s51_retinc_spwr_rq <br>
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Increment SP with 1. <br>
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Increment SP with 1. <br>
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Needed by RET, RETI. <br>
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Needed by RET, RETI. <br>
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<br>
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<br>
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</ul>
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</ul>
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</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by
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</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:30 2002 for Pipelined AVR microcontroller by
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width=110 height=53></a>1.2.16 </small></address>
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width=110 height=53></a>1.2.16 </small></address>
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