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<title>Program Memory</title>
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<title>Program Memory</title>
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<hr><h1>Program Memory<br>
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<hr><h1>Program Memory<br>
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<small>
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<small>
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[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
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[<a class="el" href="group__pavr__hwres.html">Hardware resources</a>]</small>
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<dl compact><dt><b>
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<dl compact><dt><b>
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PM handling</b><dd>
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PM handling</b><dd>
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<br>
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<br>
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<div align="center">
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<div align="center">
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<img src="pavr_hwres_pm_01.gif" alt="pavr_hwres_pm_01.gif">
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<img src="pavr_hwres_pm_01.gif" alt="pavr_hwres_pm_01.gif">
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</div>
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</div>
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<br>
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<br>
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The Program Memory is a single port RAM. <br>
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The Program Memory is a single port RAM. <br>
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That port provides read-only access. Support for the instruction SPM (Store Program Memory) is currently not provided. <br>
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That port provides read-only access. Support for the instruction SPM (Store Program Memory) is currently not provided. <br>
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The PM is organized on 16 bit words, and has the length set by a constant in the constants definition file (`pavr-constants.vhd'). <br>
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The PM is organized on 16 bit words, and has the length set by a constant in the constants definition file (`pavr-constants.vhd'). <br>
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<br>
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<br>
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Apart from controlling the Program Memory, the PM manager also controls the Program Counter. <br>
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Apart from controlling the Program Memory, the PM manager also controls the Program Counter. <br>
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Some PM access requests need to modify the PC, others don't. The only PM requests that don't modify the PC are the loads from PM (LPM and ELPM instructions). The other requests correspond to instructions that want to modify the instruction flow, thus modify the PC (jumps, branches, calls and returns). <br>
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Some PM access requests need to modify the PC, others don't. The only PM requests that don't modify the PC are the loads from PM (LPM and ELPM instructions). The other requests correspond to instructions that want to modify the instruction flow, thus modify the PC (jumps, branches, calls and returns). <br>
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</dl><dl compact><dt><b>
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</dl><dl compact><dt><b>
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Program Counter handling</b><dd>
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Program Counter handling</b><dd>
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At a given time, the pipeline can process more than one instruction. Up to 6 instructions can be simultaneousely processed. Obviousely, each of these instructions has its own address in the PM. <br>
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At a given time, the pipeline can process more than one instruction. Up to 6 instructions can be simultaneousely processed. Obviousely, each of these instructions has its own address in the PM. <br>
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One may ask: how is defined the Program Counter, as long as two or more instructions are simultaneousely executed? Whose address is considered to be the Program Counter? <br>
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One may ask: how is defined the Program Counter, as long as two or more instructions are simultaneousely executed? Whose address is considered to be the Program Counter? <br>
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The answer is: the Program Counter is in fact composed of a set of registers. Each instruction in the pipeline has an associated Program Counter that follows it while flowing through the pipeline. Implementation details can be found in the description of <a class="el" href="group__pavr__pipeline__jumps.html">jumps</a>, <a class="el" href="group__pavr__pipeline__branches.html">branches</a>, <a class="el" href="group__pavr__pipeline__skips.html">skips</a>, <a class="el" href="group__pavr__pipeline__calls.html">calls</a> and <a class="el" href="group__pavr__pipeline__returns.html">returns</a>. <br>
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The answer is: the Program Counter is in fact composed of a set of registers. Each instruction in the pipeline has an associated Program Counter that follows it while flowing through the pipeline. Implementation details can be found in the description of <a class="el" href="group__pavr__pipeline__jumps.html">jumps</a>, <a class="el" href="group__pavr__pipeline__branches.html">branches</a>, <a class="el" href="group__pavr__pipeline__skips.html">skips</a>, <a class="el" href="group__pavr__pipeline__calls.html">calls</a> and <a class="el" href="group__pavr__pipeline__returns.html">returns</a>. <br>
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As an example, when a relative jump computes the target address, it considers its own Program Counter rather than the address of the instruction fetched that moment from the PM. The instructions that modify the instruction flow (jumps, branches, skips, calls and returns) must be able to manipulate the program counters associated with pipeline stages s1, s2 and s3. However, this is done not directly, but via the Program Memory manager. The PM manager centralizes all instruction flow access requests (jump requests, branch requests, etc) and takes care of the program counters in an organized and manageable manner. <br>
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As an example, when a relative jump computes the target address, it considers its own Program Counter rather than the address of the instruction fetched that moment from the PM. The instructions that modify the instruction flow (jumps, branches, skips, calls and returns) must be able to manipulate the program counters associated with pipeline stages s1, s2 and s3. However, this is done not directly, but via the Program Memory manager. The PM manager centralizes all instruction flow access requests (jump requests, branch requests, etc) and takes care of the program counters in an organized and manageable manner. <br>
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</dl><dl compact><dt><b>
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</dl><dl compact><dt><b>
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Requests to PM</b><dd>
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Requests to PM</b><dd>
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<ul>
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<ul>
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<li>pavr_s5_lpm_pm_rq <br>
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<li>pavr_s5_lpm_pm_rq <br>
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Needed by LPM instruction. <br>
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Needed by LPM instruction. <br>
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This request doesn't modify the instruction flow. <br>
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This request doesn't modify the instruction flow. <br>
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<li>pavr_s5_elpm_pm_rq <br>
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<li>pavr_s5_elpm_pm_rq <br>
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Needed by ELPM instruction. <br>
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Needed by ELPM instruction. <br>
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This request doesn't modify the instruction flow. <br>
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This request doesn't modify the instruction flow. <br>
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<li>pavr_s4_z_pm_rq <br>
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<li>pavr_s4_z_pm_rq <br>
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Needed by ICALL and IJMP. <br>
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Needed by ICALL and IJMP. <br>
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<li>pavr_s4_zeind_pm_rq <br>
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<li>pavr_s4_zeind_pm_rq <br>
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Needed by EICALL and EIJMP. <br>
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Needed by EICALL and EIJMP. <br>
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<li>pavr_s4_k22abs_pm_rq <br>
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<li>pavr_s4_k22abs_pm_rq <br>
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Needed by CALL and JMP. <br>
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Needed by CALL and JMP. <br>
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To get to the jump address, the 16 bit instruction constant is concatenated with a 6 bit constant previousely read also from the instruction opcode.<li>pavr_s4_k12rel_pm_rq <br>
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To get to the jump address, the 16 bit instruction constant is concatenated with a 6 bit constant previousely read also from the instruction opcode.<li>pavr_s4_k12rel_pm_rq <br>
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Needed by RCALL and RJMP. <br>
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Needed by RCALL and RJMP. <br>
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Note that pavr_s4_pc is a pipeline register that holds the Program Memory address of the instruction executing in pipeline stage s4. <br>
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Note that pavr_s4_pc is a pipeline register that holds the Program Memory address of the instruction executing in pipeline stage s4. <br>
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Because the relative jump actually occurs in stage s4, pavr_s4_pc is needed rather than the current Program Counter (pavr_pc).<li>pavr_s6_branch_pm_rq <br>
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Because the relative jump actually occurs in stage s4, pavr_s4_pc is needed rather than the current Program Counter (pavr_pc).<li>pavr_s6_branch_pm_rq <br>
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Needed by branch instructions (BRBC and BRBS). <br>
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Needed by branch instructions (BRBC and BRBS). <br>
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<li>pavr_s6_skip_pm_rq <br>
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<li>pavr_s6_skip_pm_rq <br>
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Needed by some skip instructions (CPSE, SBRC and SBRS). <br>
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Needed by some skip instructions (CPSE, SBRC and SBRS). <br>
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<li>pavr_s61_skip_pm_rq <br>
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<li>pavr_s61_skip_pm_rq <br>
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Needed by some skip instructions (SBIC and SBIS). <br>
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Needed by some skip instructions (SBIC and SBIS). <br>
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<li>pavr_s4_k22int_pm_rq <br>
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<li>pavr_s4_k22int_pm_rq <br>
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Needed by implicit interrupt CALL. <br>
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Needed by implicit interrupt CALL. <br>
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<li>pavr_s54_ret_pm_rq <br>
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<li>pavr_s54_ret_pm_rq <br>
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Needed by RET and RETI. <br>
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Needed by RET and RETI. <br>
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<br>
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<br>
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</ul>
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</ul>
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</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
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</dl><hr><address align="right"><small>Generated on Tue Dec 31 20:26:31 2002 for Pipelined AVR microcontroller by
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