//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "wbr_fifo_control.v" ////
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//// File name "wbr_fifo_control.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2002/02/01 15:25:13 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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module WBR_FIFO_CONTROL
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module WBR_FIFO_CONTROL
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(
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(
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rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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flush_in,
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flush_in,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out
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wallow_out
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) ;
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) ;
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parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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input rclock_in, wclock_in;
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input rclock_in, wclock_in;
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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input renable_in, wenable_in;
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input renable_in, wenable_in;
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// reset input
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// reset input
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input reset_in;
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input reset_in;
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// flush input
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// flush input
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input flush_in ;
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input flush_in ;
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// empty status output
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// empty status output
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output empty_out;
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output empty_out;
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// read and write addresses outputs
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// read and write addresses outputs
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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|
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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// FF for registered empty flag
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// FF for registered empty flag
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reg empty ;
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reg empty ;
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// write allow wire
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// write allow wire
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wire wallow = wenable_in ;
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wire wallow = wenable_in ;
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// write allow output assignment
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// write allow output assignment
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assign wallow_out = wallow ;
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assign wallow_out = wallow ;
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// read allow wire
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// read allow wire
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wire rallow ;
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wire rallow ;
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// clear generation for FFs and registers
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// clear generation for FFs and registers
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wire clear = reset_in || flush_in ;
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wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
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reg wclock_nempty_detect ;
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reg wclock_nempty_detect ;
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always@(posedge reset_in or posedge wclock_in)
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always@(posedge reset_in or posedge wclock_in)
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begin
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begin
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if (reset_in)
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if (reset_in)
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
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else
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else
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
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end
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end
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
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reg stretched_empty ;
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reg stretched_empty ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if(clear)
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if(clear)
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stretched_empty <= #`FF_DELAY 1'b1 ;
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stretched_empty <= #`FF_DELAY 1'b1 ;
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else
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else
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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stretched_empty <= #`FF_DELAY empty && ~wclock_nempty_detect ;
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end
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end
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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// empty output is actual empty + 1 read clock cycle ( stretched empty )
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assign empty_out = empty || stretched_empty ;
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assign empty_out = empty || stretched_empty ;
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//rallow generation
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//rallow generation
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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assign rallow = renable_in && ~empty && ~stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
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// rallow output assignment
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// rallow output assignment
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assign rallow_out = renable_in ;
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assign rallow_out = renable_in ;
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
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// when FIFO is empty, this register provides actual read address, so first location can be read
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// when FIFO is empty, this register provides actual read address, so first location can be read
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
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// done for zero wait state burst
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// done for zero wait state burst
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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assign raddr_out = rallow ? raddr_plus_one : raddr ;
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 3
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// initial value is 3
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raddr_plus_one <= #`FF_DELAY 3 ;
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raddr_plus_one <= #`FF_DELAY 3 ;
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end
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else if (flush_in)
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raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ; // when read fifo is flushed, values from write side are copied to read side
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else if (rallow)
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else if (rallow)
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
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end
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end
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 2
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// initial value is 2
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raddr <= #`FF_DELAY 2 ;
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raddr <= #`FF_DELAY 2 ;
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else if (flush_in)
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raddr <= #`FF_DELAY waddr ; // when flushed, copy value from write side
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else if (rallow)
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else if (rallow)
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raddr <= #`FF_DELAY raddr_plus_one ;
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raddr <= #`FF_DELAY raddr_plus_one ;
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end
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end
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/*-----------------------------------------------------------------------------------------------
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/*-----------------------------------------------------------------------------------------------
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Read address control consists of Read address counter and Grey Address pipeline
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Read address control consists of Read address counter and Grey Address pipeline
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There are 3 Grey addresses:
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There are 3 Grey addresses:
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- rgrey_addr is Grey Code of current read address
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- rgrey_addr is Grey Code of current read address
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- rgrey_next is Grey Code of next read address
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- rgrey_next is Grey Code of next read address
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--------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------*/
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// grey code register for read address - represents current Read Address
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// grey code register for read address - represents current Read Address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 0
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// initial value is 0
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rgrey_addr <= #`FF_DELAY 0 ;
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rgrey_addr <= #`FF_DELAY 0 ;
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end
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else if (flush_in)
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else
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rgrey_addr <= #`FF_DELAY wgrey_addr ; // when flushed, copy value from write side
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if (rallow)
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else if (rallow)
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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rgrey_addr <= #`FF_DELAY rgrey_next ;
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end
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end
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// grey code register for next read address - represents Grey Code of next read address
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// grey code register for next read address - represents Grey Code of next read address
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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// initial value is 1
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// initial value is 1
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rgrey_next <= #`FF_DELAY 1 ;
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rgrey_next <= #`FF_DELAY 1 ;
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end
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else if (flush_in)
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else
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rgrey_next <= #`FF_DELAY wgrey_next ;
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if (rallow)
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else if (rallow)
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
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end
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end
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/*--------------------------------------------------------------------------------------------
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/*--------------------------------------------------------------------------------------------
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Write address control consists of write address counter and two Grey Code Registers:
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Write address control consists of write address counter and two Grey Code Registers:
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- wgrey_addr represents current Grey Coded write address
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- wgrey_addr represents current Grey Coded write address
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- wgrey_next represents Grey Coded next write address
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- wgrey_next represents Grey Coded next write address
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----------------------------------------------------------------------------------------------*/
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----------------------------------------------------------------------------------------------*/
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// grey code register for write address
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// grey code register for write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 0
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// initial value is 0
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wgrey_addr <= #`FF_DELAY 0 ;
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wgrey_addr <= #`FF_DELAY 0 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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wgrey_addr <= #`FF_DELAY wgrey_next ;
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end
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end
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// grey code register for next write address
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// grey code register for next write address
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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begin
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begin
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// initial value is 1
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// initial value is 1
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wgrey_next <= #`FF_DELAY 1 ;
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wgrey_next <= #`FF_DELAY 1 ;
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end
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end
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else
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else
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if (wallow)
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if (wallow)
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
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end
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end
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// write address counter - nothing special except initial value
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// write address counter - nothing special except initial value
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always@(posedge wclock_in or posedge clear)
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always@(posedge wclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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// initial value is 2
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// initial value is 2
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waddr <= #`FF_DELAY 2 ;
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waddr <= #`FF_DELAY 2 ;
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else
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else
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if (wallow)
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if (wallow)
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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waddr <= #`FF_DELAY waddr + 1'b1 ;
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end
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end
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|
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
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/*------------------------------------------------------------------------------------------------------------------------------
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Registered empty control:
|
Registered empty control:
|
registered empty is set on rising edge of rclock_in,
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registered empty is set on rising edge of rclock_in,
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when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on
|
when only one location is used and read in/from fifo. It's kept high until something is written to FIFO, which is registered on
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the next read clock.
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the next read clock.
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--------------------------------------------------------------------------------------------------------------------------------*/
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--------------------------------------------------------------------------------------------------------------------------------*/
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// combinatorial input for registered emty FlipFlop
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// combinatorial input for registered emty FlipFlop
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wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
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wire reg_empty = (rallow && (rgrey_next == wgrey_addr)) || (rgrey_addr == wgrey_addr) ;
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|
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
|
begin
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begin
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if (clear)
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if (clear)
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empty <= #`FF_DELAY 1'b1 ;
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empty <= #`FF_DELAY 1'b1 ;
|
|
else if (flush_in)
|
|
empty <= #1 1'b1 ; // when flushed, set empty to active
|
else
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else
|
empty <= #`FF_DELAY reg_empty ;
|
empty <= #`FF_DELAY reg_empty ;
|
end
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end
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endmodule
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endmodule
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