//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "wbw_fifo_control.v" ////
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//// File name "wbw_fifo_control.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Revision 1.4 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Revision 1.3 2002/02/01 15:25:14 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
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// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Revision 1.2 2001/10/05 08:14:30 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
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// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:47 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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|
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/* FIFO_CONTROL module provides read/write address and status generation for
|
/* FIFO_CONTROL module provides read/write address and status generation for
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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`include "pci_constants.v"
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`include "pci_constants.v"
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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|
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module WBW_FIFO_CONTROL
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module WBW_FIFO_CONTROL
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(
|
(
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rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
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renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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// flush_in, // not used
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// flush_in, // not used
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almost_full_out,
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almost_full_out,
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full_out,
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full_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out
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wallow_out
|
);
|
);
|
|
|
parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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|
|
// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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input rclock_in, wclock_in;
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input rclock_in, wclock_in;
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|
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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input renable_in, wenable_in ;
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input renable_in, wenable_in ;
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|
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// reset input
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// reset input
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input reset_in;
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input reset_in;
|
|
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// flush input
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// flush input
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// input flush_in ; // not used
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// input flush_in ; // not used
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|
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// almost full and empy status outputs
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// almost full and empy status outputs
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output almost_full_out ;
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output almost_full_out ;
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|
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// full and empty status outputs
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// full and empty status outputs
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output full_out, empty_out;
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output full_out, empty_out;
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|
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// read and write addresses outputs
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// read and write addresses outputs
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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|
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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|
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// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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|
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// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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|
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// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
|
|
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// next write gray address calculation - bitwise xor between address and shifted address
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// next write gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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|
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// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus2 ; // two before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
|
|
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// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
|
|
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// FFs for registered empty and full flags
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// FFs for registered empty and full flags
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wire empty ;
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wire empty ;
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wire full ;
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wire full ;
|
|
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// almost_full tag
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// almost_full tag
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wire almost_full ;
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wire almost_full ;
|
|
|
// write allow wire - writes are allowed when fifo is not full
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// write allow wire - writes are allowed when fifo is not full
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wire wallow = wenable_in && !full ;
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wire wallow = wenable_in && !full ;
|
|
|
// write allow output assignment
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// write allow output assignment
|
assign wallow_out = wallow && !full ;
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assign wallow_out = wallow && !full ;
|
|
|
// read allow wire
|
// read allow wire
|
wire rallow ;
|
wire rallow ;
|
|
|
// full output assignment
|
// full output assignment
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assign full_out = full ;
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assign full_out = full ;
|
|
|
// almost full output assignment
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// almost full output assignment
|
assign almost_full_out = almost_full && !full ;
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assign almost_full_out = almost_full && !full ;
|
|
|
// clear generation for FFs and registers
|
// clear generation for FFs and registers
|
wire clear = reset_in /*|| flush_in*/ ; // flush not used
|
wire clear = reset_in /*|| flush_in*/ ; // flush not used
|
|
|
reg wclock_nempty_detect ;
|
reg wclock_nempty_detect ;
|
always@(posedge clear or posedge wclock_in)
|
always@(posedge clear or posedge wclock_in)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
|
wclock_nempty_detect <= #`FF_DELAY 1'b0 ;
|
else
|
else
|
wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
|
wclock_nempty_detect <= #`FF_DELAY (rgrey_addr != wgrey_addr) ;
|
end
|
end
|
|
|
// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
|
// special synchronizing mechanism for different implementations - in synchronous imp., empty is prolonged for 1 clock edge if no write clock comes after initial write
|
wire stretched_empty ;
|
wire stretched_empty ;
|
|
|
wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
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wire stretched_empty_flop_i = empty && !wclock_nempty_detect ;
|
|
|
meta_flop #(1) i_meta_flop_stretched_empty
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meta_flop #(1) i_meta_flop_stretched_empty
|
(
|
(
|
.rst_i (clear),
|
.rst_i (clear),
|
.clk_i (rclock_in),
|
.clk_i (rclock_in),
|
.ld_i (1'b0),
|
.ld_i (1'b0),
|
.ld_val_i (1'b0),
|
.ld_val_i (1'b0),
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.en_i (1'b1),
|
.en_i (1'b1),
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.d_i (stretched_empty_flop_i),
|
.d_i (stretched_empty_flop_i),
|
.meta_q_o (stretched_empty)
|
.meta_q_o (stretched_empty)
|
) ;
|
) ;
|
|
|
// empty output is actual empty + 1 read clock cycle ( stretched empty )
|
// empty output is actual empty + 1 read clock cycle ( stretched empty )
|
assign empty_out = empty || stretched_empty ;
|
assign empty_out = empty || stretched_empty ;
|
|
|
//rallow generation
|
//rallow generation
|
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
|
assign rallow = renable_in && !empty && !stretched_empty ; // reads allowed if read enable is high and FIFO is not empty
|
|
|
// rallow output assignment
|
// rallow output assignment
|
assign rallow_out = rallow ;
|
assign rallow_out = rallow ;
|
|
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
|
// when FIFO is empty, this register provides actual read address, so first location can be read
|
// when FIFO is empty, this register provides actual read address, so first location can be read
|
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
|
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
|
|
|
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
|
// address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
|
// done for zero wait state burst
|
// done for zero wait state burst
|
assign raddr_out = rallow ? raddr_plus_one : raddr ;
|
assign raddr_out = rallow ? raddr_plus_one : raddr ;
|
|
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is important - raddr initial value is 4, so this one is 5
|
// initial value is important - raddr initial value is 4, so this one is 5
|
raddr_plus_one <= #`FF_DELAY 5 ;
|
raddr_plus_one <= #`FF_DELAY 5 ;
|
end
|
end
|
else if (rallow)
|
else if (rallow)
|
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
|
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
|
end
|
end
|
|
|
// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
|
// raddr is filled with raddr_plus_one on rising read clock edge when rallow is high
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
// initial value is 4
|
// initial value is 4
|
raddr <= #`FF_DELAY 4 ;
|
raddr <= #`FF_DELAY 4 ;
|
else if (rallow)
|
else if (rallow)
|
raddr <= #`FF_DELAY raddr_plus_one ;
|
raddr <= #`FF_DELAY raddr_plus_one ;
|
end
|
end
|
|
|
/*-----------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------
|
Read address control consists of Read address counter and Grey Address pipeline
|
Read address control consists of Read address counter and Grey Address pipeline
|
There are 4 Grey addresses:
|
There are 4 Grey addresses:
|
- rgrey_minus2 is Grey Code of address two before current address
|
- rgrey_minus2 is Grey Code of address two before current address
|
- rgrey_minus1 is Grey Code of address one before current address
|
- rgrey_minus1 is Grey Code of address one before current address
|
- rgrey_addr is Grey Code of current read address
|
- rgrey_addr is Grey Code of current read address
|
- rgrey_next is Grey Code of next read address
|
- rgrey_next is Grey Code of next read address
|
--------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------*/
|
|
|
// grey code register for two before read address
|
// grey code register for two before read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 0
|
// initial value is 0
|
rgrey_minus2 <= #`FF_DELAY 0 ;
|
rgrey_minus2 <= #`FF_DELAY 0 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
|
rgrey_minus2 <= #`FF_DELAY rgrey_minus1 ;
|
end
|
end
|
|
|
// grey code register for one before read address
|
// grey code register for one before read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 1
|
// initial value is 1
|
rgrey_minus1 <= #`FF_DELAY 1 ;
|
rgrey_minus1 <= #`FF_DELAY 1 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
|
rgrey_minus1 <= #`FF_DELAY rgrey_addr ;
|
end
|
end
|
|
|
// grey code register for read address - represents current Read Address
|
// grey code register for read address - represents current Read Address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 3 = ...00011
|
// initial value is 3 = ...00011
|
rgrey_addr <= #`FF_DELAY 3 ;
|
rgrey_addr <= #`FF_DELAY 3 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_addr <= #`FF_DELAY rgrey_next ;
|
rgrey_addr <= #`FF_DELAY rgrey_next ;
|
end
|
end
|
|
|
// grey code register for next read address - represents Grey Code of next read address
|
// grey code register for next read address - represents Grey Code of next read address
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 2 = ...00010
|
// initial value is 2 = ...00010
|
rgrey_next <= #`FF_DELAY 2 ;
|
rgrey_next <= #`FF_DELAY 2 ;
|
end
|
end
|
else
|
else
|
if (rallow)
|
if (rallow)
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
end
|
end
|
|
|
/*--------------------------------------------------------------------------------------------
|
/*--------------------------------------------------------------------------------------------
|
Write address control consists of write address counter and two Grey Code Registers:
|
Write address control consists of write address counter and two Grey Code Registers:
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_next represents Grey Coded next write address
|
- wgrey_next represents Grey Coded next write address
|
----------------------------------------------------------------------------------------------*/
|
----------------------------------------------------------------------------------------------*/
|
// grey code register for write address
|
// grey code register for write address
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 3 = ....011
|
// initial value is 3 = ....011
|
wgrey_addr <= #`FF_DELAY 3 ;
|
wgrey_addr <= #`FF_DELAY 3 ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
wgrey_addr <= #`FF_DELAY wgrey_next ;
|
wgrey_addr <= #`FF_DELAY wgrey_next ;
|
end
|
end
|
|
|
// grey code register for next write address
|
// grey code register for next write address
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial value is 2 = ...010
|
// initial value is 2 = ...010
|
wgrey_next <= #`FF_DELAY 2 ;
|
wgrey_next <= #`FF_DELAY 2 ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
end
|
end
|
|
|
// write address counter - nothing special - initial value is important though
|
// write address counter - nothing special - initial value is important though
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
// initial value 4
|
// initial value 4
|
waddr <= #`FF_DELAY 4 ;
|
waddr <= #`FF_DELAY 4 ;
|
else
|
else
|
if (wallow)
|
if (wallow)
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
end
|
end
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Registered full control:
|
Registered full control:
|
registered full is set on rising edge of wclock_in when there is one free location in and another written to fifo
|
registered full is set on rising edge of wclock_in when there is one free location in and another written to fifo
|
It's kept high until something is read from FIFO, which is registered on
|
It's kept high until something is read from FIFO, which is registered on
|
next rising write clock edge.
|
next rising write clock edge.
|
|
|
Registered almost full control:
|
Registered almost full control:
|
Almost full flag is set on rising wclock_in edge when there are two unused locations left in and another written to fifo.
|
Almost full flag is set on rising wclock_in edge when there are two unused locations left in and another written to fifo.
|
It is set until something is read/written from/to fifo
|
It is set until something is read/written from/to fifo
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
//combinatorial input to Registered full FlipFlop
|
//combinatorial input to Registered full FlipFlop
|
wire reg_full = wallow && (wgrey_next == rgrey_minus1) || (wgrey_next == rgrey_addr) ;
|
wire reg_full = wallow && (wgrey_next == rgrey_minus1) || (wgrey_next == rgrey_addr) ;
|
|
|
meta_flop #(0) i_meta_flop_full
|
meta_flop #(0) i_meta_flop_full
|
(
|
(
|
.rst_i (clear),
|
.rst_i (clear),
|
.clk_i (wclock_in),
|
.clk_i (wclock_in),
|
.ld_i (1'b0),
|
.ld_i (1'b0),
|
.ld_val_i (1'b0),
|
.ld_val_i (1'b0),
|
.en_i (1'b1),
|
.en_i (1'b1),
|
.d_i (reg_full),
|
.d_i (reg_full),
|
.meta_q_o (full)
|
.meta_q_o (full)
|
) ;
|
) ;
|
|
|
// input for almost full latch
|
// input for almost full latch
|
wire reg_almost_full_in = wallow && (wgrey_next == rgrey_minus2) || (wgrey_next == rgrey_minus1) ;
|
wire reg_almost_full_in = wallow && (wgrey_next == rgrey_minus2) || (wgrey_next == rgrey_minus1) ;
|
|
|
meta_flop #(0) i_meta_flop_almost_full
|
meta_flop #(0) i_meta_flop_almost_full
|
(
|
(
|
.rst_i (clear),
|
.rst_i (clear),
|
.clk_i (wclock_in),
|
.clk_i (wclock_in),
|
.ld_i (1'b0),
|
.ld_i (1'b0),
|
.ld_val_i (1'b0),
|
.ld_val_i (1'b0),
|
.en_i (1'b1),
|
.en_i (1'b1),
|
.d_i (reg_almost_full_in),
|
.d_i (reg_almost_full_in),
|
.meta_q_o (almost_full)
|
.meta_q_o (almost_full)
|
) ;
|
) ;
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Registered empty control:
|
Registered empty control:
|
registered empty is set on rising edge of rclock_in when one location is used and read from fifo. It's kept high
|
registered empty is set on rising edge of rclock_in when one location is used and read from fifo. It's kept high
|
until something is written to the fifo, which is registered on the next clock edge.
|
until something is written to the fifo, which is registered on the next clock edge.
|
|
|
Registered almost empty control:
|
Registered almost empty control:
|
Almost empty is set on rising edge of rclock_in when two locations are used and one read. It's kept set until something
|
Almost empty is set on rising edge of rclock_in when two locations are used and one read. It's kept set until something
|
is read/written from/to fifo.
|
is read/written from/to fifo.
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
// combinatorial input for registered emty FlipFlop
|
// combinatorial input for registered emty FlipFlop
|
wire comb_almost_empty = (rgrey_next == wgrey_addr) ;
|
wire comb_almost_empty = (rgrey_next == wgrey_addr) ;
|
wire comb_empty = (rgrey_addr == wgrey_addr) ;
|
wire comb_empty = (rgrey_addr == wgrey_addr) ;
|
wire reg_empty = renable_in && comb_almost_empty || comb_empty ;
|
wire reg_empty = renable_in && comb_almost_empty || comb_empty ;
|
|
|
meta_flop #(1) i_meta_flop_empty
|
meta_flop #(1) i_meta_flop_empty
|
(
|
(
|
.rst_i (clear),
|
.rst_i (clear),
|
.clk_i (rclock_in),
|
.clk_i (rclock_in),
|
.ld_i (1'b0),
|
.ld_i (1'b0),
|
.ld_val_i (1'b0),
|
.ld_val_i (1'b0),
|
.en_i (1'b1),
|
.en_i (1'b1),
|
.d_i (reg_empty),
|
.d_i (reg_empty),
|
.meta_q_o (empty)
|
.meta_q_o (empty)
|
) ;
|
) ;
|
|
|
endmodule
|
endmodule
|
|
|
