//////////////////////////////////////////////////////////////////////
|
//////////////////////////////////////////////////////////////////////
|
//// ////
|
//// ////
|
//// File name "fifo_control.v" ////
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//// File name "fifo_control.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
|
//// http://www.opencores.org/cores/pci/ ////
|
//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// All additional information is avaliable in the README ////
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//// All additional information is avaliable in the README ////
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//// file. ////
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//// file. ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
|
//// This source file may be used and distributed without ////
|
//// restriction provided that this copyright statement is not ////
|
//// restriction provided that this copyright statement is not ////
|
//// removed from the file and that any derivative work contains ////
|
//// removed from the file and that any derivative work contains ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// the original copyright notice and the associated disclaimer. ////
|
//// ////
|
//// ////
|
//// This source file is free software; you can redistribute it ////
|
//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
|
//// and/or modify it under the terms of the GNU Lesser General ////
|
//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
|
//// either version 2.1 of the License, or (at your option) any ////
|
//// later version. ////
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//// later version. ////
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//// ////
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//// ////
|
//// This source is distributed in the hope that it will be ////
|
//// This source is distributed in the hope that it will be ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
|
//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
|
//// details. ////
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//// ////
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//// ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// You should have received a copy of the GNU Lesser General ////
|
//// Public License along with this source; if not, download it ////
|
//// Public License along with this source; if not, download it ////
|
//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
|
//
|
// CVS Revision History
|
// CVS Revision History
|
//
|
//
|
// $Log: not supported by cvs2svn $
|
// $Log: not supported by cvs2svn $
|
// Revision 1.3 2003/07/29 08:20:11 mihad
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// Revision 1.3 2003/07/29 08:20:11 mihad
|
// Found and simulated the problem in the synchronization logic.
|
// Found and simulated the problem in the synchronization logic.
|
// Repaired the synchronization logic in the FIFOs.
|
// Repaired the synchronization logic in the FIFOs.
|
//
|
//
|
// Revision 1.2 2003/03/26 13:16:18 mihad
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// Revision 1.2 2003/03/26 13:16:18 mihad
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// Added the reset value parameter to the synchronizer flop module.
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// Added the reset value parameter to the synchronizer flop module.
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// Added resets to all synchronizer flop instances.
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// Added resets to all synchronizer flop instances.
|
// Repaired initial sync value in fifos.
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// Repaired initial sync value in fifos.
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//
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//
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Revision 1.1 2003/01/27 16:49:31 mihad
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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// Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
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//
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//
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// Revision 1.7 2002/11/27 20:36:10 mihad
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// Revision 1.7 2002/11/27 20:36:10 mihad
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// Changed the code a bit to make it more readable.
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// Changed the code a bit to make it more readable.
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// Functionality not changed in any way.
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// Functionality not changed in any way.
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// More robust synchronization in fifos is still pending.
|
// More robust synchronization in fifos is still pending.
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//
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//
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// Revision 1.6 2002/09/30 16:03:04 mihad
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// Revision 1.6 2002/09/30 16:03:04 mihad
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// Added meta flop module for easier meta stable FF identification during synthesis
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// Added meta flop module for easier meta stable FF identification during synthesis
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//
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//
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// Revision 1.5 2002/09/25 15:53:52 mihad
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// Revision 1.5 2002/09/25 15:53:52 mihad
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// Removed all logic from asynchronous reset network
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// Removed all logic from asynchronous reset network
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//
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//
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// Revision 1.4 2002/03/05 11:53:47 mihad
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// Revision 1.4 2002/03/05 11:53:47 mihad
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// Added some testcases, removed un-needed fifo signals
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// Added some testcases, removed un-needed fifo signals
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//
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//
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Revision 1.3 2002/02/01 15:25:12 mihad
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// Repaired a few bugs, updated specification, added test bench files and design document
|
// Repaired a few bugs, updated specification, added test bench files and design document
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//
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//
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Revision 1.2 2001/10/05 08:14:28 mihad
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// Updated all files with inclusion of timescale file for simulation purposes.
|
// Updated all files with inclusion of timescale file for simulation purposes.
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//
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//
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// Revision 1.1.1.1 2001/10/02 15:33:46 mihad
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// New project directory structure
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// New project directory structure
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//
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//
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//
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//
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|
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/* FIFO_CONTROL module provides read/write address and status generation for
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/* FIFO_CONTROL module provides read/write address and status generation for
|
FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
|
FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
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|
|
`include "pci_constants.v"
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`include "pci_constants.v"
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|
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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|
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module pci_pcir_fifo_control
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module pci_pcir_fifo_control
|
(
|
(
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rclock_in,
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rclock_in,
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wclock_in,
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wclock_in,
|
renable_in,
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renable_in,
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wenable_in,
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wenable_in,
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reset_in,
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reset_in,
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flush_in,
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flush_in,
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full_out,
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full_out,
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almost_empty_out,
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almost_empty_out,
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empty_out,
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empty_out,
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waddr_out,
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waddr_out,
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raddr_out,
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raddr_out,
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rallow_out,
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rallow_out,
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wallow_out
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wallow_out
|
);
|
);
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|
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// address length parameter - depends on fifo depth
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// address length parameter - depends on fifo depth
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parameter ADDR_LENGTH = 7 ;
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parameter ADDR_LENGTH = 7 ;
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|
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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// independent clock inputs - rclock_in = read clock, wclock_in = write clock
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input rclock_in, wclock_in;
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input rclock_in, wclock_in;
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|
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// enable inputs - read address changes on rising edge of rclock_in when reads are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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// write address changes on rising edge of wclock_in when writes are allowed
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input renable_in, wenable_in;
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input renable_in, wenable_in;
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|
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// reset input
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// reset input
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input reset_in;
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input reset_in;
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|
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// flush input
|
// flush input
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input flush_in ;
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input flush_in ;
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|
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// almost empy status output
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// almost empy status output
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output almost_empty_out;
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output almost_empty_out;
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|
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// full and empty status outputs
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// full and empty status outputs
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output full_out, empty_out;
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output full_out, empty_out;
|
|
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// read and write addresses outputs
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// read and write addresses outputs
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
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|
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// read and write allow outputs
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// read and write allow outputs
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output rallow_out, wallow_out ;
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output rallow_out, wallow_out ;
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|
|
// read address register
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// read address register
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reg [(ADDR_LENGTH - 1):0] raddr ;
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reg [(ADDR_LENGTH - 1):0] raddr ;
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|
|
// write address register
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// write address register
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reg [(ADDR_LENGTH - 1):0] waddr;
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reg [(ADDR_LENGTH - 1):0] waddr;
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assign waddr_out = waddr ;
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assign waddr_out = waddr ;
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|
|
// grey code registers
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// grey code registers
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// grey code pipeline for write address
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// grey code pipeline for write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
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reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next grey coded write address
|
|
|
// next write gray address calculation - bitwise xor between address and shifted address
|
// next write gray address calculation - bitwise xor between address and shifted address
|
wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_wgrey_next = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
|
|
|
// grey code pipeline for read address
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// grey code pipeline for read address
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reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
|
reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
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reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
|
|
|
// next read gray address calculation - bitwise xor between address and shifted address
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// next read gray address calculation - bitwise xor between address and shifted address
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
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wire [(ADDR_LENGTH - 2):0] calc_rgrey_next = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
|
|
|
// FFs for registered empty and full flags
|
// FFs for registered empty and full flags
|
wire empty ;
|
wire empty ;
|
wire full ;
|
wire full ;
|
|
|
// almost_empty tag
|
// almost_empty tag
|
wire almost_empty ;
|
wire almost_empty ;
|
|
|
// write allow wire - writes are allowed when fifo is not full
|
// write allow wire - writes are allowed when fifo is not full
|
wire wallow = wenable_in && !full ;
|
wire wallow = wenable_in && !full ;
|
|
|
// write allow output assignment
|
// write allow output assignment
|
assign wallow_out = wallow ;
|
assign wallow_out = wallow ;
|
|
|
// read allow wire
|
// read allow wire
|
wire rallow ;
|
wire rallow ;
|
|
|
// full output assignment
|
// full output assignment
|
assign full_out = full ;
|
assign full_out = full ;
|
|
|
// clear generation for FFs and registers
|
// clear generation for FFs and registers
|
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
|
wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
|
|
|
assign empty_out = empty ;
|
assign empty_out = empty ;
|
|
|
//rallow generation
|
//rallow generation
|
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
|
assign rallow = renable_in && !empty ; // reads allowed if read enable is high and FIFO is not empty
|
|
|
// rallow output assignment
|
// rallow output assignment
|
assign rallow_out = rallow ;
|
assign rallow_out = rallow ;
|
|
|
// almost empty output assignment
|
// almost empty output assignment
|
assign almost_empty_out = almost_empty ;
|
assign almost_empty_out = almost_empty ;
|
|
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
|
// at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
|
// when FIFO is empty, this register provides actual read address, so first location can be read
|
// when FIFO is empty, this register provides actual read address, so first location can be read
|
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
|
reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
|
|
|
// address output mux - when FIFO is not read, current actual address is driven out, when it is read, next address is driven out to provide
|
// address output mux - when FIFO is not read, current actual address is driven out, when it is read, next address is driven out to provide
|
// next data immediately
|
// next data immediately
|
// done for zero wait state burst operation
|
// done for zero wait state burst operation
|
assign raddr_out = rallow ? raddr_plus_one : raddr ;
|
assign raddr_out = rallow ? raddr_plus_one : raddr ;
|
|
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
|
// initial values seem a bit odd - they are this way to allow easier grey pipeline implementation and to allow min fifo size of 8
|
raddr_plus_one <= #`FF_DELAY 3 ;
|
raddr_plus_one <= #`FF_DELAY 3 ;
|
raddr <= #`FF_DELAY 2 ;
|
raddr <= #`FF_DELAY 2 ;
|
end
|
end
|
else if (flush_in)
|
else if (flush_in)
|
begin
|
begin
|
raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ;
|
raddr_plus_one <= #`FF_DELAY waddr + 1'b1 ;
|
raddr <= #`FF_DELAY waddr ;
|
raddr <= #`FF_DELAY waddr ;
|
end
|
end
|
else if (rallow)
|
else if (rallow)
|
begin
|
begin
|
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
|
raddr_plus_one <= #`FF_DELAY raddr_plus_one + 1'b1 ;
|
raddr <= #`FF_DELAY raddr_plus_one ;
|
raddr <= #`FF_DELAY raddr_plus_one ;
|
end
|
end
|
end
|
end
|
|
|
/*-----------------------------------------------------------------------------------------------
|
/*-----------------------------------------------------------------------------------------------
|
Read address control consists of Read address counter and Grey Address pipeline
|
Read address control consists of Read address counter and Grey Address pipeline
|
There are 2 Grey addresses:
|
There are 2 Grey addresses:
|
- rgrey_addr is Grey Code of current read address
|
- rgrey_addr is Grey Code of current read address
|
- rgrey_next is Grey Code of next read address
|
- rgrey_next is Grey Code of next read address
|
--------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------*/
|
// grey coded address pipeline for status generation in read clock domain
|
// grey coded address pipeline for status generation in read clock domain
|
always@(posedge rclock_in or posedge clear)
|
always@(posedge rclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
rgrey_addr <= #1 0 ;
|
rgrey_addr <= #1 0 ;
|
rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
|
rgrey_next <= #`FF_DELAY 1 ; // this grey code is calculated from the current binary address and loaded any time data is read from fifo
|
end
|
end
|
else if (flush_in)
|
else if (flush_in)
|
begin
|
begin
|
// when fifo is flushed, load the register values from the write clock domain.
|
// when fifo is flushed, load the register values from the write clock domain.
|
// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
|
// must be no problem, because write pointers are stable for at least 3 clock cycles before flush can occur.
|
rgrey_addr <= #1 wgrey_addr ;
|
rgrey_addr <= #1 wgrey_addr ;
|
rgrey_next <= #`FF_DELAY wgrey_next ;
|
rgrey_next <= #`FF_DELAY wgrey_next ;
|
end
|
end
|
else if (rallow)
|
else if (rallow)
|
begin
|
begin
|
// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
|
// move the pipeline when data is read from fifo and calculate new value for first stage of pipeline from current binary fifo address
|
rgrey_addr <= #1 rgrey_next ;
|
rgrey_addr <= #1 rgrey_next ;
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
rgrey_next <= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
|
end
|
end
|
end
|
end
|
|
|
/*--------------------------------------------------------------------------------------------
|
/*--------------------------------------------------------------------------------------------
|
Write address control consists of write address counter and 2 Grey Code Registers:
|
Write address control consists of write address counter and 2 Grey Code Registers:
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_addr represents current Grey Coded write address
|
- wgrey_next represents Grey Coded next write address
|
- wgrey_next represents Grey Coded next write address
|
----------------------------------------------------------------------------------------------*/
|
----------------------------------------------------------------------------------------------*/
|
// grey coded address pipeline for status generation in write clock domain
|
// grey coded address pipeline for status generation in write clock domain
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
begin
|
begin
|
wgrey_addr <= #1 0 ;
|
wgrey_addr <= #1 0 ;
|
wgrey_next <= #`FF_DELAY 1 ;
|
wgrey_next <= #`FF_DELAY 1 ;
|
end
|
end
|
else
|
else
|
if (wallow)
|
if (wallow)
|
begin
|
begin
|
wgrey_addr <= #1 wgrey_next ;
|
wgrey_addr <= #1 wgrey_next ;
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
wgrey_next <= #`FF_DELAY {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
|
end
|
end
|
end
|
end
|
|
|
// write address binary counter - nothing special except initial value
|
// write address binary counter - nothing special except initial value
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
// initial value 2
|
// initial value 2
|
waddr <= #`FF_DELAY 2 ;
|
waddr <= #`FF_DELAY 2 ;
|
else
|
else
|
if (wallow)
|
if (wallow)
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
waddr <= #`FF_DELAY waddr + 1'b1 ;
|
end
|
end
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Full control:
|
Full control:
|
Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.
|
Gray coded read address pointer is synchronized to write clock domain and compared to Gray coded next write address.
|
If they are equal, fifo is full.
|
If they are equal, fifo is full.
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;
|
wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_addr ;
|
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;
|
reg [(ADDR_LENGTH - 1):0] wclk_rgrey_addr ;
|
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr
|
pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_addr
|
(
|
(
|
.data_in (rgrey_addr),
|
.data_in (rgrey_addr),
|
.clk_out (wclock_in),
|
.clk_out (wclock_in),
|
.sync_data_out (wclk_sync_rgrey_addr),
|
.sync_data_out (wclk_sync_rgrey_addr),
|
.async_reset (clear)
|
.async_reset (clear)
|
) ;
|
) ;
|
|
|
always@(posedge wclock_in or posedge clear)
|
always@(posedge wclock_in or posedge clear)
|
begin
|
begin
|
if (clear)
|
if (clear)
|
wclk_rgrey_addr <= #`FF_DELAY 0 ;
|
wclk_rgrey_addr <= #`FF_DELAY 0 ;
|
else
|
else
|
wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ;
|
wclk_rgrey_addr <= #`FF_DELAY wclk_sync_rgrey_addr ;
|
end
|
end
|
|
|
assign full = (wgrey_next == wclk_rgrey_addr) ;
|
assign full = (wgrey_next == wclk_rgrey_addr) ;
|
|
|
/*------------------------------------------------------------------------------------------------------------------------------
|
/*------------------------------------------------------------------------------------------------------------------------------
|
Empty control:
|
Empty control:
|
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
|
Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
|
If they are equal, fifo is empty. Synchronized write pointer is also compared to Gray coded next read address. If these two are
|
If they are equal, fifo is empty. Synchronized write pointer is also compared to Gray coded next read address. If these two are
|
equal, fifo is almost empty.
|
equal, fifo is almost empty.
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
--------------------------------------------------------------------------------------------------------------------------------*/
|
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
|
wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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reg [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
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pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
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pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
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(
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(
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.data_in (wgrey_addr),
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.data_in (wgrey_addr),
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.clk_out (rclock_in),
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.clk_out (rclock_in),
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.sync_data_out (rclk_sync_wgrey_addr),
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.sync_data_out (rclk_sync_wgrey_addr),
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.async_reset (clear)
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.async_reset (clear)
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) ;
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) ;
|
|
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always@(posedge rclock_in or posedge clear)
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always@(posedge rclock_in or posedge clear)
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begin
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begin
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if (clear)
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if (clear)
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rclk_wgrey_addr <= #`FF_DELAY 0 ;
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rclk_wgrey_addr <= #`FF_DELAY 0 ;
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else
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else
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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rclk_wgrey_addr <= #`FF_DELAY rclk_sync_wgrey_addr ;
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end
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end
|
|
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assign almost_empty = (rgrey_next == rclk_wgrey_addr) ;
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assign almost_empty = (rgrey_next == rclk_wgrey_addr) ;
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assign empty = (rgrey_addr == rclk_wgrey_addr) ;
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assign empty = (rgrey_addr == rclk_wgrey_addr) ;
|
|
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endmodule
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endmodule
|
|
|
