//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// File name "pci_wbs_wbb3_2_wbb2.v" ////
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//// File name "pci_wbs_wbb3_2_wbb2.v" ////
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//// ////
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//// ////
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//// This file is part of the "PCI bridge" project ////
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//// This file is part of the "PCI bridge" project ////
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//// http://www.opencores.org/cores/pci/ ////
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//// http://www.opencores.org/cores/pci/ ////
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//// ////
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//// ////
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//// Author(s): ////
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//// Author(s): ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// - Miha Dolenc (mihad@opencores.org) ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//// ////
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//// ////
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//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////
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//// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org ////
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//// ////
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//// ////
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//// This source file may be used and distributed without ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer. ////
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//// the original copyright notice and the associated disclaimer. ////
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//// ////
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//// ////
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//// This source file is free software; you can redistribute it ////
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//// This source file is free software; you can redistribute it ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// and/or modify it under the terms of the GNU Lesser General ////
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//// Public License as published by the Free Software Foundation; ////
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//// Public License as published by the Free Software Foundation; ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// either version 2.1 of the License, or (at your option) any ////
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//// later version. ////
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//// later version. ////
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//// ////
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//// ////
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//// This source is distributed in the hope that it will be ////
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//// This source is distributed in the hope that it will be ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// PURPOSE. See the GNU Lesser General Public License for more ////
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//// details. ////
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//// details. ////
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//// ////
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//// ////
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//// You should have received a copy of the GNU Lesser General ////
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//// You should have received a copy of the GNU Lesser General ////
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//// Public License along with this source; if not, download it ////
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//// Public License along with this source; if not, download it ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// from http://www.opencores.org/lgpl.shtml ////
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//// ////
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//// ////
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//////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////
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//
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//
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// CVS Revision History
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// CVS Revision History
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//
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//
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// $Log: not supported by cvs2svn $
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// $Log: not supported by cvs2svn $
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//
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//
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module pci_wbs_wbb3_2_wbb2
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module pci_wbs_wbb3_2_wbb2
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(
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(
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wb_clk_i,
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wb_clk_i,
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wb_rst_i,
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wb_rst_i,
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wbs_cyc_i,
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wbs_cyc_i,
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wbs_cyc_o,
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wbs_cyc_o,
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wbs_stb_i,
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wbs_stb_i,
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wbs_stb_o,
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wbs_stb_o,
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wbs_adr_i,
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wbs_adr_i,
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wbs_adr_o,
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wbs_adr_o,
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wbs_dat_i_i,
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wbs_dat_i_i,
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wbs_dat_i_o,
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wbs_dat_i_o,
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wbs_dat_o_i,
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wbs_dat_o_i,
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wbs_dat_o_o,
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wbs_dat_o_o,
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wbs_we_i,
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wbs_we_i,
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wbs_we_o,
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wbs_we_o,
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wbs_sel_i,
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wbs_sel_i,
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wbs_sel_o,
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wbs_sel_o,
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wbs_ack_i,
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wbs_ack_i,
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wbs_ack_o,
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wbs_ack_o,
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wbs_err_i,
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wbs_err_i,
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wbs_err_o,
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wbs_err_o,
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wbs_rty_i,
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wbs_rty_i,
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wbs_rty_o,
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wbs_rty_o,
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wbs_cti_i,
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wbs_cti_i,
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wbs_bte_i,
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wbs_bte_i,
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wbs_cab_o
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wbs_cab_o
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) ;
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) ;
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input wb_clk_i ;
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input wb_clk_i ;
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input wb_rst_i ;
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input wb_rst_i ;
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input wbs_cyc_i ;
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input wbs_cyc_i ;
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output wbs_cyc_o ;
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output wbs_cyc_o ;
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input wbs_stb_i ;
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input wbs_stb_i ;
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output wbs_stb_o ;
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output wbs_stb_o ;
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input [31:0] wbs_adr_i ;
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input [31:0] wbs_adr_i ;
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output [31:0] wbs_adr_o ;
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output [31:0] wbs_adr_o ;
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input [31:0] wbs_dat_i_i ;
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input [31:0] wbs_dat_i_i ;
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output [31:0] wbs_dat_i_o ;
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output [31:0] wbs_dat_i_o ;
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input [31:0] wbs_dat_o_i ;
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input [31:0] wbs_dat_o_i ;
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output [31:0] wbs_dat_o_o ;
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output [31:0] wbs_dat_o_o ;
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input wbs_we_i ;
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input wbs_we_i ;
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output wbs_we_o ;
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output wbs_we_o ;
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input [ 3:0] wbs_sel_i ;
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input [ 3:0] wbs_sel_i ;
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output [ 3:0] wbs_sel_o ;
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output [ 3:0] wbs_sel_o ;
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input wbs_ack_i ;
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input wbs_ack_i ;
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output wbs_ack_o ;
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output wbs_ack_o ;
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input wbs_err_i ;
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input wbs_err_i ;
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output wbs_err_o ;
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output wbs_err_o ;
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input wbs_rty_i ;
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input wbs_rty_i ;
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output wbs_rty_o ;
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output wbs_rty_o ;
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input [ 2:0] wbs_cti_i ;
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input [ 2:0] wbs_cti_i ;
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input [ 1:0] wbs_bte_i ;
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input [ 1:0] wbs_bte_i ;
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output wbs_cab_o ;
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output wbs_cab_o ;
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reg wbs_cyc_o ;
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reg wbs_cyc_o ;
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reg [31:0] wbs_adr_o ;
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reg [31:0] wbs_adr_o ;
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reg [31:0] wbs_dat_i_o ;
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reg [31:0] wbs_dat_i_o ;
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reg wbs_dat_i_o_valid ;
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reg wbs_dat_i_o_valid ;
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reg [31:0] wbs_dat_o_o ;
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reg [31:0] wbs_dat_o_o ;
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reg wbs_we_o ;
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reg wbs_we_o ;
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reg [ 3:0] wbs_sel_o ;
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reg [ 3:0] wbs_sel_o ;
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reg wbs_ack_o ;
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reg wbs_ack_o ;
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reg wbs_err_o ;
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reg wbs_err_o ;
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reg wbs_rty_o ;
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reg wbs_rty_o ;
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reg wbs_cab_o ;
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reg wbs_cab_o ;
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always@(posedge wb_rst_i or posedge wb_clk_i)
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always@(posedge wb_rst_i or posedge wb_clk_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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begin
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wbs_cyc_o <= 1'b0 ;
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wbs_cyc_o <= 1'b0 ;
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wbs_adr_o <= 32'h0 ;
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wbs_adr_o <= 32'h0 ;
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wbs_dat_i_o <= 32'h0 ;
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wbs_dat_i_o <= 32'h0 ;
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wbs_dat_o_o <= 32'h0 ;
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wbs_dat_o_o <= 32'h0 ;
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wbs_sel_o <= 4'h0 ;
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wbs_sel_o <= 4'h0 ;
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wbs_we_o <= 1'b0 ;
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wbs_we_o <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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end
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end
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else
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else
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begin:transfer_and_transfer_adr_ctrl_blk
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begin:transfer_and_transfer_adr_ctrl_blk
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reg start_cycle ;
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reg start_cycle ;
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reg [3:0] end_cycle ;
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reg [3:0] end_cycle ;
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reg generate_int_adr ;
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reg generate_int_adr ;
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start_cycle = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o ;
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start_cycle = ~wbs_cyc_o & wbs_cyc_i & wbs_stb_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o ;
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// there is a few conditions when cycle must be terminated
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// there is a few conditions when cycle must be terminated
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// I've put them into bit array for better readability of the code
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// I've put them into bit array for better readability of the code
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// 1st condition - pci bridge is signaling an error
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// 1st condition - pci bridge is signaling an error
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end_cycle[0] = wbs_err_i ;
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end_cycle[0] = wbs_err_i ;
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// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
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// 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
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end_cycle[1] = wbs_rty_i `ifdef PCI_WBS_B3_RTY_DISABLE & 1'b0 `endif ;
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end_cycle[1] = wbs_rty_i `ifdef PCI_WBS_B3_RTY_DISABLE & 1'b0 `endif ;
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// 3rd condition - end non burst cycles as soon as pci bridge response is received
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// 3rd condition - end non burst cycles as soon as pci bridge response is received
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end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
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end_cycle[2] = wbs_cyc_i & wbs_stb_i & wbs_ack_i & ~wbs_cab_o ;
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// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
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// 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
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end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
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end_cycle[3] = wbs_cyc_i & wbs_stb_i & wbs_ack_o & wbs_cab_o & (wbs_cti_i == 3'b111) ;
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if (wbs_dat_i_o_valid)
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if (wbs_dat_i_o_valid)
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begin
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begin
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if (wbs_ack_i | wbs_err_i `ifdef PCI_WBS_B3_RTY_DISABLE `else | wbs_rty_i `endif)
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if (wbs_ack_i | wbs_err_i `ifdef PCI_WBS_B3_RTY_DISABLE `else | wbs_rty_i `endif)
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wbs_dat_i_o_valid <= 1'b0 ;
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wbs_dat_i_o_valid <= 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)
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if (wbs_cyc_i & wbs_stb_i & wbs_we_i & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o)
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begin
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begin
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wbs_dat_i_o <= wbs_dat_i_i ;
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wbs_dat_i_o <= wbs_dat_i_i ;
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wbs_dat_i_o_valid <= 1'b1 ;
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wbs_dat_i_o_valid <= 1'b1 ;
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end
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end
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end
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end
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if (start_cycle)
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if (start_cycle)
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begin
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begin
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wbs_cyc_o <= 1'b1 ;
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wbs_cyc_o <= 1'b1 ;
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wbs_sel_o <= wbs_sel_i ;
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wbs_sel_o <= wbs_sel_i ;
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wbs_we_o <= wbs_we_i ;
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wbs_we_o <= wbs_we_i ;
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if (wbs_cti_i == 3'b010)
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if (wbs_cti_i == 3'b010)
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begin
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begin
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case (wbs_bte_i)
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case (wbs_bte_i)
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2'b00: begin
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2'b00: begin
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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end
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end
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2'b01: begin
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2'b01: begin
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if (wbs_adr_i[3:0] == 4'b0000)
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if (wbs_adr_i[3:0] == 4'b0000)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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2'b10: begin
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2'b10: begin
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if (wbs_adr_i[4:0] == 5'b00000)
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if (wbs_adr_i[4:0] == 5'b00000)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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2'b11: begin
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2'b11: begin
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if (wbs_adr_i[5:0] == 6'b000000)
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if (wbs_adr_i[5:0] == 6'b000000)
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wbs_cab_o <= 1'b1 ;
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wbs_cab_o <= 1'b1 ;
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else
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else
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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endcase
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endcase
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end
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end
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else
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else
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begin
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begin
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wbs_cab_o <= 1'b0 ;
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wbs_cab_o <= 1'b0 ;
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end
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end
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end
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end
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else if ( wbs_cyc_o & (|end_cycle) )
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else if ( wbs_cyc_o & (|end_cycle) )
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begin
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begin
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wbs_cyc_o <= 1'b0 ;
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wbs_cyc_o <= 1'b0 ;
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end
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end
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if (start_cycle)
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if (start_cycle)
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wbs_adr_o <= wbs_adr_i ;
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wbs_adr_o <= wbs_adr_i ;
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else if (wbs_ack_i)
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else if (wbs_ack_i)
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wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;
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wbs_adr_o[31:2] <= wbs_adr_o[31:2] + 1'b1 ;
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if (~wbs_we_o & wbs_ack_i)
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if (~wbs_we_o & wbs_ack_i)
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wbs_dat_o_o <= wbs_dat_o_i ;
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wbs_dat_o_o <= wbs_dat_o_i ;
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end
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end
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end
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end
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always@(posedge wb_rst_i or posedge wb_clk_i)
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always@(posedge wb_rst_i or posedge wb_clk_i)
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begin
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begin
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if (wb_rst_i)
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if (wb_rst_i)
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begin
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begin
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wbs_ack_o <= 1'b0 ;
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wbs_ack_o <= 1'b0 ;
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wbs_err_o <= 1'b0 ;
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wbs_err_o <= 1'b0 ;
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wbs_rty_o <= 1'b0 ;
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wbs_rty_o <= 1'b0 ;
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end
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end
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else
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else
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begin
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begin
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if (wbs_ack_o)
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if (wbs_ack_o)
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wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ;
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wbs_ack_o <= wbs_ack_i | ~wbs_stb_i ;
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else
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else
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wbs_ack_o <= wbs_ack_i ;
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wbs_ack_o <= wbs_ack_i ;
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if (wbs_err_o)
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if (wbs_err_o)
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wbs_err_o <= ~wbs_stb_i ;
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wbs_err_o <= ~wbs_stb_i ;
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else
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else
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wbs_err_o <= wbs_err_i ;
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wbs_err_o <= wbs_err_i ;
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`ifdef PCI_WBS_B3_RTY_DISABLE
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`ifdef PCI_WBS_B3_RTY_DISABLE
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wbs_rty_o <= 1'b0 ;
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wbs_rty_o <= 1'b0 ;
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`else
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`else
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if (wbs_rty_o)
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if (wbs_rty_o)
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wbs_rty_o <= ~wbs_stb_i ;
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wbs_rty_o <= ~wbs_stb_i ;
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else
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else
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wbs_rty_o <= wbs_rty_i ;
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wbs_rty_o <= wbs_rty_i ;
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`endif
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`endif
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end
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end
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end
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end
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assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
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assign wbs_stb_o = (wbs_cyc_o & ~wbs_we_o & ~wbs_ack_o & ~wbs_err_o & ~wbs_rty_o) |
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(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) |
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(wbs_cyc_o & wbs_stb_i & wbs_cab_o & ~wbs_we_o & wbs_cti_i !== 3'b111) |
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(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
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(wbs_cyc_o & wbs_we_o & wbs_dat_i_o_valid) ;
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