//===========================================================================
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//===========================================================================
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// $Id: pci_bus_monitor.v,v 1.3 2002-08-13 11:03:51 mihad Exp $
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// $Id: pci_bus_monitor.v,v 1.4 2003-08-03 18:04:44 mihad Exp $
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//
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//
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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// Copyright 2001 Blue Beaver. All Rights Reserved.
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//
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//
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// Summary: Watch the PCI Bus Wires to try to see Protocol Errors.
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// This module also has access to the individual PCI Bus OE
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// This module also has access to the individual PCI Bus OE
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// signals for each interface (either through extra output
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// signals for each interface (either through extra output
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// ports or through "." notation), and it can see when more
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// ports or through "." notation), and it can see when more
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// than one interface is driving the bus, even if the values
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// than one interface is driving the bus, even if the values
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// are the same.
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// are the same.
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// A future version of this module should write out a transcript
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// A future version of this module should write out a transcript
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// of the activity seen on the PCI Bus.
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// of the activity seen on the PCI Bus.
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//
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//
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// This library is free software; you can distribute it and/or modify it
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// This library is free software; you can distribute it and/or modify it
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// under the terms of the GNU Lesser General Public License as published
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// under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation; either version 2.1 of the License, or
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// by the Free Software Foundation; either version 2.1 of the License, or
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// (at your option) any later version.
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// (at your option) any later version.
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//
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//
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// This library is distributed in the hope that it will be useful, but
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// This library is distributed in the hope that it will be useful, but
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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// See the GNU Lesser General Public License for more details.
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// See the GNU Lesser General Public License for more details.
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//
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//
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// You should have received a copy of the GNU Lesser General Public License
|
// You should have received a copy of the GNU Lesser General Public License
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// along with this library. If not, write to
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// along with this library. If not, write to
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// Free Software Foundation, Inc.
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// Free Software Foundation, Inc.
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// 59 Temple Place, Suite 330
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// 59 Temple Place, Suite 330
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// Boston, MA 02111-1307 USA
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// Boston, MA 02111-1307 USA
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//
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//
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// Author's note about this license: The intention of the Author and of
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// Author's note about this license: The intention of the Author and of
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// the Gnu Lesser General Public License is that users should be able to
|
// the Gnu Lesser General Public License is that users should be able to
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// use this code for any purpose, including combining it with other source
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// use this code for any purpose, including combining it with other source
|
// code, combining it with other logic, translated it into a gate-level
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// code, combining it with other logic, translated it into a gate-level
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// representation, or projected it into gates in a programmable or
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// representation, or projected it into gates in a programmable or
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// hardwired chip, as long as the users of the resulting source, compiled
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// hardwired chip, as long as the users of the resulting source, compiled
|
// source, or chip are given the means to get a copy of this source code
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// source, or chip are given the means to get a copy of this source code
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// with no new restrictions on redistribution of this source.
|
// with no new restrictions on redistribution of this source.
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//
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//
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// If you make changes, even substantial changes, to this code, or use
|
// If you make changes, even substantial changes, to this code, or use
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// substantial parts of this code as an inseparable part of another work
|
// substantial parts of this code as an inseparable part of another work
|
// of authorship, the users of the resulting IP must be given the means
|
// of authorship, the users of the resulting IP must be given the means
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// to get a copy of the modified or combined source code, with no new
|
// to get a copy of the modified or combined source code, with no new
|
// restrictions on redistribution of the resulting source.
|
// restrictions on redistribution of the resulting source.
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//
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//
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// Separate parts of the combined source code, compiled code, or chip,
|
// Separate parts of the combined source code, compiled code, or chip,
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// which are NOT derived from this source code do NOT need to be offered
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// which are NOT derived from this source code do NOT need to be offered
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// to the final user of the chip merely because they are used in
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// to the final user of the chip merely because they are used in
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// combination with this code. Other code is not forced to fall under
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// combination with this code. Other code is not forced to fall under
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// the GNU Lesser General Public License when it is linked to this code.
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// the GNU Lesser General Public License when it is linked to this code.
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// The license terms of other source code linked to this code might require
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// The license terms of other source code linked to this code might require
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// that it NOT be made available to users. The GNU Lesser General Public
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// that it NOT be made available to users. The GNU Lesser General Public
|
// License does not prevent this code from being used in such a situation,
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// License does not prevent this code from being used in such a situation,
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// as long as the user of the resulting IP is given the means to get a
|
// as long as the user of the resulting IP is given the means to get a
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// copy of this component of the IP with no new restrictions on
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// copy of this component of the IP with no new restrictions on
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// redistribution of this source.
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// redistribution of this source.
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//
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//
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// This code was developed using VeriLogger Pro, by Synapticad.
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// This code was developed using VeriLogger Pro, by Synapticad.
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// Their support is greatly appreciated.
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// Their support is greatly appreciated.
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//
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//
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// NOTE: This module watches the PCI bus and gives commentary about what
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// NOTE: This module watches the PCI bus and gives commentary about what
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// it sees.
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// it sees.
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// I hope that this can get a parameter which says whether to put
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// I hope that this can get a parameter which says whether to put
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// its log in a file, on the terminal, or both.
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// its log in a file, on the terminal, or both.
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//
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//
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// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
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// TO DO: create code to act on MONITOR_CREATE_BUS_ACTIVITY_TRANSCRIPT
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//
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//
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//===========================================================================
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//===========================================================================
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|
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// Note that master aborts are the norm on Special Cycles!
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// Note that master aborts are the norm on Special Cycles!
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// synopsys translate_off
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// synopsys translate_off
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`include "timescale.v"
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`include "timescale.v"
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// synopsys translate_on
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// synopsys translate_on
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//`timescale 1ns/10ps
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//`timescale 1ns/10ps
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|
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module pci_bus_monitor (
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module pci_bus_monitor (
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pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
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pci_ext_ad, pci_ext_cbe_l, pci_ext_par,
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pci_ext_frame_l, pci_ext_irdy_l,
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pci_ext_frame_l, pci_ext_irdy_l,
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pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
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pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l,
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pci_ext_perr_l, pci_ext_serr_l,
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pci_ext_perr_l, pci_ext_serr_l,
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pci_real_req_l, pci_real_gnt_l,
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pci_real_req_l, pci_real_gnt_l,
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pci_ext_req_l, pci_ext_gnt_l,
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pci_ext_req_l, pci_ext_gnt_l,
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test_error_event, test_observe_r_oe_sigs,
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test_error_event, test_observe_r_oe_sigs,
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test_observe_0_oe_sigs, test_observe_1_oe_sigs,
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test_observe_0_oe_sigs, test_observe_1_oe_sigs,
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test_observe_2_oe_sigs, test_observe_3_oe_sigs,
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test_observe_2_oe_sigs, test_observe_3_oe_sigs,
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pci_ext_reset_l, pci_ext_clk,
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pci_ext_reset_l, pci_ext_clk,
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log_file_desc
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log_file_desc
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);
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);
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`include "pci_blue_options.vh"
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`include "pci_blue_options.vh"
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`include "pci_blue_constants.vh"
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`include "pci_blue_constants.vh"
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|
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input [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
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input [PCI_BUS_DATA_RANGE:0] pci_ext_ad;
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input [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
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input [PCI_BUS_CBE_RANGE:0] pci_ext_cbe_l;
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input pci_ext_par;
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input pci_ext_par;
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input pci_ext_frame_l, pci_ext_irdy_l;
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input pci_ext_frame_l, pci_ext_irdy_l;
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input pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
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input pci_ext_devsel_l, pci_ext_trdy_l, pci_ext_stop_l;
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input pci_ext_perr_l, pci_ext_serr_l;
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input pci_ext_perr_l, pci_ext_serr_l;
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input pci_real_req_l, pci_real_gnt_l;
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input pci_real_req_l, pci_real_gnt_l;
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input [3:0] pci_ext_req_l;
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input [3:0] pci_ext_req_l;
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input [3:0] pci_ext_gnt_l;
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input [3:0] pci_ext_gnt_l;
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output test_error_event;
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output test_error_event;
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input [5:0] test_observe_r_oe_sigs;
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input [5:0] test_observe_r_oe_sigs;
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input [5:0] test_observe_0_oe_sigs;
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input [5:0] test_observe_0_oe_sigs;
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input [5:0] test_observe_1_oe_sigs;
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input [5:0] test_observe_1_oe_sigs;
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input [5:0] test_observe_2_oe_sigs;
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input [5:0] test_observe_2_oe_sigs;
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input [5:0] test_observe_3_oe_sigs;
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input [5:0] test_observe_3_oe_sigs;
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|
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input pci_ext_reset_l, pci_ext_clk;
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input pci_ext_reset_l, pci_ext_clk;
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|
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input [31:0] log_file_desc ;
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input [31:0] log_file_desc ;
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// Make temporary Bip every time an error is detected
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// Make temporary Bip every time an error is detected
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reg test_error_event;
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reg test_error_event;
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initial test_error_event <= 1'bZ;
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initial test_error_event <= 1'bZ;
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reg error_detected;
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reg error_detected;
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initial error_detected <= 1'b0;
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initial error_detected <= 1'b0;
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always @(error_detected)
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always @(error_detected)
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begin
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begin
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test_error_event <= 1'b0;
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test_error_event <= 1'b0;
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#2;
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#2;
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test_error_event <= 1'bZ;
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test_error_event <= 1'bZ;
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end
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end
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// watch for the PCI Clock going X
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// watch for the PCI Clock going X
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always @(pci_ext_clk)
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always @(pci_ext_clk)
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begin
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begin
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if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
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if (($time > 0) && ((pci_ext_clk ^ pci_ext_clk) === 1'bx))
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begin
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begin
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$display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
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$display ("*** monitor - PCI External Clock invalid 'h%x, at %t",
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pci_ext_clk, $time);
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pci_ext_clk, $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
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$fdisplay (log_file_desc, "*** monitor - PCI External Clock invalid 'h%x, at %t",
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pci_ext_clk, $time);
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pci_ext_clk, $time);
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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end
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end
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// watch for the Reset signal going X
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// watch for the Reset signal going X
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always @(pci_ext_reset_l)
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always @(pci_ext_reset_l)
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begin
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begin
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if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
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if (($time > 0) & ((pci_ext_reset_l ^ pci_ext_reset_l) === 1'bx))
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begin
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begin
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$display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
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$display ("*** monitor - PCI External RESET_L invalid 'h%x, at %t",
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pci_ext_reset_l, $time);
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pci_ext_reset_l, $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
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$fdisplay (log_file_desc, "*** monitor - PCI External RESET_L invalid 'h%x, at %t",
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pci_ext_reset_l, $time);
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pci_ext_reset_l, $time);
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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end
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end
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|
|
// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
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// Make sure all PCI signals are HIGH-Z or Deasserted HIGH as needed
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// when the external PCI bus leaves reset.
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// when the external PCI bus leaves reset.
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// The values of some signals are set by pullups on the PC board
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// The values of some signals are set by pullups on the PC board
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always @(posedge pci_ext_reset_l)
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always @(posedge pci_ext_reset_l)
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begin
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begin
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if ($time > 0)
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if ($time > 0)
|
begin
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begin
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if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
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if (pci_ext_ad[PCI_BUS_DATA_RANGE:0] !== `PCI_BUS_DATA_Z)
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begin
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begin
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$display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
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$display ("*** monitor - PCI External AD not high-Z 'h%x, at %t",
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pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
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pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
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$fdisplay (log_file_desc, "*** monitor - PCI External AD not high-Z 'h%x, at %t",
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pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
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pci_ext_ad[PCI_BUS_DATA_RANGE:0], $time);
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
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if (pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0] !== `PCI_BUS_CBE_Z)
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begin
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begin
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$display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
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$display ("*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
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pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
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pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
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$fdisplay (log_file_desc, "*** monitor - PCI External CBE_L not high-Z 'h%x, at %t",
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pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
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pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0], $time);
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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`NO_ELSE;
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`NO_ELSE;
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if (pci_ext_par !== 1'bz)
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if (pci_ext_par !== 1'bz)
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begin
|
begin
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$display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
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$display ("*** monitor - PCI External PAR not high-Z 'h%x, at %t",
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pci_ext_par, $time);
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pci_ext_par, $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
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$fdisplay (log_file_desc, "*** monitor - PCI External PAR not high-Z 'h%x, at %t",
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pci_ext_par, $time);
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pci_ext_par, $time);
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error_detected <= ~error_detected;
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error_detected <= ~error_detected;
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end
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end
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`NO_ELSE;
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`NO_ELSE;
|
if (pci_ext_frame_l !== 1'b1)
|
if (pci_ext_frame_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
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$display ("*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
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pci_ext_frame_l, $time);
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pci_ext_frame_l, $time);
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$fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External FRAME_L invalid 'h%x, at %t",
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pci_ext_frame_l, $time);
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pci_ext_frame_l, $time);
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error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
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end
|
end
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`NO_ELSE;
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`NO_ELSE;
|
if (pci_ext_irdy_l !== 1'b1)
|
if (pci_ext_irdy_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
pci_ext_irdy_l, $time);
|
pci_ext_irdy_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External IRDY_L invalid 'h%x, at %t",
|
pci_ext_irdy_l, $time);
|
pci_ext_irdy_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_devsel_l !== 1'b1)
|
if (pci_ext_devsel_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
pci_ext_devsel_l, $time);
|
pci_ext_devsel_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External DEVSEL_L invalid 'h%x, at %t",
|
pci_ext_devsel_l, $time);
|
pci_ext_devsel_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_trdy_l !== 1'b1)
|
if (pci_ext_trdy_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
pci_ext_trdy_l, $time);
|
pci_ext_trdy_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External TRDY_L invalid 'h%x, at %t",
|
pci_ext_trdy_l, $time);
|
pci_ext_trdy_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_stop_l !== 1'b1)
|
if (pci_ext_stop_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
pci_ext_stop_l, $time);
|
pci_ext_stop_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External STOP_L invalid 'h%x, at %t",
|
pci_ext_stop_l, $time);
|
pci_ext_stop_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_perr_l !== 1'b1)
|
if (pci_ext_perr_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
pci_ext_perr_l, $time);
|
pci_ext_perr_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External PERR_L invalid 'h%x, at %t",
|
pci_ext_perr_l, $time);
|
pci_ext_perr_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_serr_l !== 1'b1)
|
if (pci_ext_serr_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
pci_ext_serr_l, $time);
|
pci_ext_serr_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External SERR_L invalid 'h%x, at %t",
|
pci_ext_serr_l, $time);
|
pci_ext_serr_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_real_req_l !== 1'b1)
|
if (pci_real_req_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
pci_real_req_l, $time);
|
pci_real_req_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal REQ_L invalid 'h%x, at %t",
|
pci_real_req_l, $time);
|
pci_real_req_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_real_gnt_l !== 1'b1)
|
if (pci_real_gnt_l !== 1'b1)
|
begin
|
begin
|
$display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
pci_real_gnt_l, $time);
|
pci_real_gnt_l, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Internal GNT_L invalid 'h%x, at %t",
|
pci_real_gnt_l, $time);
|
pci_real_gnt_l, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_req_l[3:0] !== 4'hF)
|
if (pci_ext_req_l[3:0] !== 4'hF)
|
begin
|
begin
|
$display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
pci_ext_req_l[3:0], $time);
|
pci_ext_req_l[3:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External REQ_L invalid 'h%x, at %t",
|
pci_ext_req_l[3:0], $time);
|
pci_ext_req_l[3:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (pci_ext_gnt_l[3:0] !== 4'hF)
|
if (pci_ext_gnt_l[3:0] !== 4'hF)
|
begin
|
begin
|
$display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
$display ("*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
pci_ext_gnt_l[3:0], $time);
|
pci_ext_gnt_l[3:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI External GNT_L invalid 'h%x, at %t",
|
pci_ext_gnt_l[3:0], $time);
|
pci_ext_gnt_l[3:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
|
|
task Watch_For_X_On_OE_Sigs;
|
task Watch_For_X_On_OE_Sigs;
|
input [2:0] signal_source;
|
input [2:0] signal_source;
|
input [5:0] oe_signals;
|
input [5:0] oe_signals;
|
begin
|
begin
|
if ((^oe_signals[5:0]) === 1'bX)
|
if ((^oe_signals[5:0]) === 1'bX)
|
begin
|
begin
|
if (signal_source[2:0] == `Test_Master_Real)
|
if (signal_source[2:0] == `Test_Master_Real)
|
begin
|
begin
|
$display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
$display ("*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
oe_signals[5:0], $time);
|
oe_signals[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Real OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
oe_signals[5:0], $time);
|
oe_signals[5:0], $time);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
$display ("*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
signal_source[2:0], oe_signals[5:0], $time);
|
signal_source[2:0], oe_signals[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %h OE signals have X's {F, I, D_T_S, AD, CBE, PERR} 'b%b, at %t",
|
signal_source[2:0], oe_signals[5:0], $time);
|
signal_source[2:0], oe_signals[5:0], $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
|
task Watch_For_Simultaneous_Drive_Of_OE_Sigs;
|
input [2:0] signal_source_0;
|
input [2:0] signal_source_0;
|
input [2:0] signal_source_1;
|
input [2:0] signal_source_1;
|
input [5:0] oe_signals_0;
|
input [5:0] oe_signals_0;
|
input [5:0] oe_signals_1;
|
input [5:0] oe_signals_1;
|
begin
|
begin
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
begin
|
begin
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
begin
|
begin
|
$display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_1[2:0], oe_signals_0[5:0],
|
signal_source_1[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Real and Test %x drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_1[2:0], oe_signals_0[5:0],
|
signal_source_1[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
end
|
end
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
begin
|
begin
|
$display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], oe_signals_0[5:0],
|
signal_source_0[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Real drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], oe_signals_0[5:0],
|
signal_source_0[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], signal_source_1[1:0],
|
signal_source_0[2:0], signal_source_1[1:0],
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x and Test %h drive bus simultaneously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], signal_source_1[1:0],
|
signal_source_0[2:0], signal_source_1[1:0],
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
end
|
end
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Watch_For_Deassert_Before_Tristate ;
|
task Watch_For_Deassert_Before_Tristate ;
|
input [2:0] signal_source ;
|
input [2:0] signal_source ;
|
input [5:0] prev_oe_sigs ;
|
input [5:0] prev_oe_sigs ;
|
input [5:0] current_oe_sigs ;
|
input [5:0] current_oe_sigs ;
|
input prev_perr ;
|
input prev_perr ;
|
input prev_frame ;
|
input prev_frame ;
|
input prev_irdy ;
|
input prev_irdy ;
|
input prev_trdy ;
|
input prev_trdy ;
|
input prev_stop ;
|
input prev_stop ;
|
input prev_devsel ;
|
input prev_devsel ;
|
reg do_error ;
|
reg do_error ;
|
begin
|
begin
|
do_error = 0 ;
|
do_error = 0 ;
|
if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
|
if ( prev_oe_sigs[0] && !current_oe_sigs[0] && prev_perr )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving PERR before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving PERR before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_stop )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving STOP before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving STOP before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_trdy )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving TRDY before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving TRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
|
if ( prev_oe_sigs[3] && !current_oe_sigs[3] && prev_devsel )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving DEVSEL before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving DEVSEL before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
|
if ( prev_oe_sigs[4] && !current_oe_sigs[4] && prev_irdy )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving IRDY before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving IRDY before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
|
if ( prev_oe_sigs[5] && !current_oe_sigs[5] && prev_frame )
|
begin
|
begin
|
do_error = 1 ;
|
do_error = 1 ;
|
if ( signal_source == `Test_Master_Real )
|
if ( signal_source == `Test_Master_Real )
|
begin
|
begin
|
$display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
$display("*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Real Stopped driving FRAME before Deasserting it for one cycle, at %t", $time) ;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$display("*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
$fdisplay(log_file_desc, "*** monitor - PCI Test %x Stopped driving FRAME before Deasserting it for one cycle, at %t", signal_source, $time) ;
|
end
|
end
|
end
|
end
|
|
|
if ( do_error )
|
if ( do_error )
|
error_detected <= ~error_detected ;
|
error_detected <= ~error_detected ;
|
end
|
end
|
endtask
|
endtask
|
|
|
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
|
task Watch_For_Back_To_Back_Drive_Of_OE_Sigs;
|
input [2:0] signal_source_0;
|
input [2:0] signal_source_0;
|
input [2:0] signal_source_1;
|
input [2:0] signal_source_1;
|
input [5:0] oe_signals_0;
|
input [5:0] oe_signals_0;
|
input [5:0] oe_signals_1;
|
input [5:0] oe_signals_1;
|
begin
|
begin
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
if ((oe_signals_0 & oe_signals_1) !== 6'h00)
|
begin
|
begin
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
if (signal_source_0[2:0] == `Test_Master_Real)
|
begin
|
begin
|
$display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_1[2:0], oe_signals_0[5:0],
|
signal_source_1[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Real drives when Test %x drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_1[2:0], oe_signals_0[5:0],
|
signal_source_1[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
end
|
end
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
else if (signal_source_1[2:0] == `Test_Master_Real)
|
begin
|
begin
|
$display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], oe_signals_0[5:0],
|
signal_source_0[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Real drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], oe_signals_0[5:0],
|
signal_source_0[2:0], oe_signals_0[5:0],
|
oe_signals_1[5:0], $time);
|
oe_signals_1[5:0], $time);
|
end
|
end
|
else
|
else
|
begin
|
begin
|
$display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$display ("*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], signal_source_1[1:0],
|
signal_source_0[2:0], signal_source_1[1:0],
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI Test %x drives when Test %h drove previously {F, I, D_T_S, AD, CBE, PERR} 'b%b, 'b%b, at %t",
|
signal_source_0[2:0], signal_source_1[1:0],
|
signal_source_0[2:0], signal_source_1[1:0],
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
oe_signals_0[5:0], oe_signals_1[5:0], $time);
|
end
|
end
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
endtask
|
endtask
|
|
|
// watch for PCI devices simultaneously driving PCI wires
|
// watch for PCI devices simultaneously driving PCI wires
|
// OE Observation signals are
|
// OE Observation signals are
|
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
|
// {frame_oe, irdy_oe, devsel_t_s_oe, ad_oe, cbe_oe, perr_oe}
|
// Unused ports should be wired to 0
|
// Unused ports should be wired to 0
|
reg [5:0] prev_real_oe_sigs;
|
reg [5:0] prev_real_oe_sigs;
|
reg [5:0] prev_test_0_oe_sigs;
|
reg [5:0] prev_test_0_oe_sigs;
|
reg [5:0] prev_test_1_oe_sigs;
|
reg [5:0] prev_test_1_oe_sigs;
|
reg [5:0] prev_test_2_oe_sigs;
|
reg [5:0] prev_test_2_oe_sigs;
|
reg [5:0] prev_test_3_oe_sigs;
|
reg [5:0] prev_test_3_oe_sigs;
|
|
|
// Make Asserted HIGH signals to prevent (cause?) confusion
|
// Make Asserted HIGH signals to prevent (cause?) confusion
|
wire frame_now = ~pci_ext_frame_l;
|
wire frame_now = ~pci_ext_frame_l;
|
wire irdy_now = ~pci_ext_irdy_l;
|
wire irdy_now = ~pci_ext_irdy_l;
|
wire devsel_now = ~pci_ext_devsel_l;
|
wire devsel_now = ~pci_ext_devsel_l;
|
wire trdy_now = ~pci_ext_trdy_l;
|
wire trdy_now = ~pci_ext_trdy_l;
|
wire stop_now = ~pci_ext_stop_l;
|
wire stop_now = ~pci_ext_stop_l;
|
wire perr_now = ~pci_ext_perr_l;
|
wire perr_now = ~pci_ext_perr_l;
|
// Delay PCI bus signals, used by several tests below.
|
// Delay PCI bus signals, used by several tests below.
|
// Detect Address Phases on the bus.
|
// Detect Address Phases on the bus.
|
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
|
// Ignore Dual Access Cycle, as mentioned in the PCI Local Bus Spec
|
// Revision 2.2 section 3.1.1.
|
// Revision 2.2 section 3.1.1.
|
reg [4:0] grant_prev;
|
reg [4:0] grant_prev;
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev;
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev;
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev;
|
reg frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
|
reg frame_prev, irdy_prev, devsel_prev, trdy_prev, stop_prev, perr_prev;
|
reg address_phase_prev, read_operation_prev;
|
reg address_phase_prev, read_operation_prev;
|
|
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
begin
|
begin
|
if (pci_ext_reset_l == 1'b0)
|
if (pci_ext_reset_l == 1'b0)
|
begin
|
begin
|
prev_real_oe_sigs <= 6'h00;
|
prev_real_oe_sigs <= 6'h00;
|
prev_test_0_oe_sigs <= 6'h00;
|
prev_test_0_oe_sigs <= 6'h00;
|
prev_test_1_oe_sigs <= 6'h00;
|
prev_test_1_oe_sigs <= 6'h00;
|
prev_test_2_oe_sigs <= 6'h00;
|
prev_test_2_oe_sigs <= 6'h00;
|
prev_test_3_oe_sigs <= 6'h00;
|
prev_test_3_oe_sigs <= 6'h00;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
|
prev_real_oe_sigs <= test_observe_r_oe_sigs[5:0];
|
prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
|
prev_test_0_oe_sigs <= test_observe_0_oe_sigs[5:0];
|
prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
|
prev_test_1_oe_sigs <= test_observe_1_oe_sigs[5:0];
|
prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
|
prev_test_2_oe_sigs <= test_observe_2_oe_sigs[5:0];
|
prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
|
prev_test_3_oe_sigs <= test_observe_3_oe_sigs[5:0];
|
end
|
end
|
end
|
end
|
|
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
if (($time > 0) & (pci_ext_reset_l == 1'b1))
|
if (($time > 0) & (pci_ext_reset_l == 1'b1))
|
begin
|
begin
|
Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (`Test_Master_Real, test_observe_r_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h0, test_observe_0_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h1, test_observe_1_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h2, test_observe_2_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
|
Watch_For_X_On_OE_Sigs (3'h3, test_observe_3_oe_sigs[5:0]);
|
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], test_observe_0_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], test_observe_1_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], test_observe_2_oe_sigs[5:0]);
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
|
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
Watch_For_Simultaneous_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
test_observe_2_oe_sigs[5:0], test_observe_3_oe_sigs[5:0]);
|
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h0,
|
test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h1,
|
test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h2,
|
test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (`Test_Master_Real, 3'h3,
|
test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
test_observe_r_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, `Test_Master_Real,
|
test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h1,
|
test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h2,
|
test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h0, 3'h3,
|
test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
test_observe_0_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h0,
|
test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, `Test_Master_Real,
|
test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h2,
|
test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h1, 3'h3,
|
test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
test_observe_1_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h0,
|
test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
test_observe_2_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h1,
|
test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
test_observe_2_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, `Test_Master_Real,
|
test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
test_observe_2_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h2, 3'h3,
|
test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
test_observe_2_oe_sigs[5:0], prev_test_3_oe_sigs[5:0]);
|
|
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h0,
|
test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
test_observe_3_oe_sigs[5:0], prev_test_0_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h1,
|
test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
test_observe_3_oe_sigs[5:0], prev_test_1_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, 3'h2,
|
test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
test_observe_3_oe_sigs[5:0], prev_test_2_oe_sigs[5:0]);
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
|
Watch_For_Back_To_Back_Drive_Of_OE_Sigs (3'h3, `Test_Master_Real,
|
test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
test_observe_3_oe_sigs[5:0], prev_real_oe_sigs[5:0]);
|
|
|
Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(`Test_Master_Real, prev_real_oe_sigs, test_observe_r_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h0, prev_test_0_oe_sigs, test_observe_0_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h1, prev_test_1_oe_sigs, test_observe_1_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h2, prev_test_2_oe_sigs, test_observe_2_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
Watch_For_Deassert_Before_Tristate(3'h3, prev_test_3_oe_sigs, test_observe_3_oe_sigs, perr_prev, frame_prev, irdy_prev, trdy_prev, stop_prev, devsel_prev) ;
|
|
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
|
|
|
wire [4:0] grant_now = {pci_ext_gnt_l[3:0], pci_real_gnt_l} ;
|
|
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
begin
|
begin
|
if (pci_ext_reset_l == 1'b0)
|
if (pci_ext_reset_l == 1'b0)
|
begin
|
begin
|
grant_prev <= 5'h00;
|
grant_prev <= 5'h00;
|
ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
|
ad_prev[PCI_BUS_DATA_RANGE:0] <= `PCI_BUS_DATA_X;
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= `PCI_BUS_CBE_X;
|
frame_prev <= 1'b0;
|
frame_prev <= 1'b0;
|
irdy_prev <= 1'b0;
|
irdy_prev <= 1'b0;
|
devsel_prev <= 1'b0;
|
devsel_prev <= 1'b0;
|
trdy_prev <= 1'b0;
|
trdy_prev <= 1'b0;
|
stop_prev <= 1'b0;
|
stop_prev <= 1'b0;
|
address_phase_prev <= 1'b0;
|
address_phase_prev <= 1'b0;
|
read_operation_prev <= 1'b0;
|
read_operation_prev <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
grant_prev <= {pci_ext_gnt_l[3:0], pci_real_gnt_l};
|
grant_prev <= grant_now ;
|
ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
|
ad_prev[PCI_BUS_DATA_RANGE:0] <= pci_ext_ad[PCI_BUS_DATA_RANGE:0];
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
|
cbe_l_prev[PCI_BUS_CBE_RANGE:0] <= pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0];
|
frame_prev <= frame_now;
|
frame_prev <= frame_now;
|
irdy_prev <= irdy_now;
|
irdy_prev <= irdy_now;
|
devsel_prev <= devsel_now;
|
devsel_prev <= devsel_now;
|
trdy_prev <= trdy_now;
|
trdy_prev <= trdy_now;
|
stop_prev <= stop_now;
|
stop_prev <= stop_now;
|
perr_prev <= perr_now ;
|
perr_prev <= perr_now ;
|
|
|
if (frame_now & ~frame_prev)
|
if (frame_now & ~frame_prev)
|
begin
|
begin
|
address_phase_prev <= 1'b1;
|
address_phase_prev <= 1'b1;
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
end
|
end
|
else if(address_phase_prev && (cbe_l_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE))
|
else if(address_phase_prev && (cbe_l_prev[PCI_BUS_CBE_RANGE:0] == PCI_COMMAND_DUAL_ADDRESS_CYCLE))
|
begin
|
begin
|
address_phase_prev <= 1'b1;
|
address_phase_prev <= 1'b1;
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
read_operation_prev <= ~pci_ext_cbe_l[0]; // reads have LSB == 0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
address_phase_prev <= 1'b0;
|
address_phase_prev <= 1'b0;
|
read_operation_prev <= read_operation_prev;
|
read_operation_prev <= read_operation_prev;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// Track the behavior of the PCI Arbiter. Rules:
|
// Track the behavior of the PCI Arbiter. Rules:
|
// 1) No grant during reset
|
// 1) No grant during reset
|
// 2) At most 1 grant at any time
|
// 2) At most 1 grant at any time
|
// 3) One non-grant cycle on any grant transition when the bus is idle
|
// 3) One non-grant cycle on any grant transition when the bus is idle
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
if ($time > 0)
|
if ($time > 0)
|
begin
|
begin
|
if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
|
if ((^{pci_ext_gnt_l[3:0], pci_real_gnt_l}) === 1'bX)
|
begin
|
begin
|
$display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
$display ("*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L unknown 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ((pci_ext_reset_l == 1'b0)
|
if ((pci_ext_reset_l == 1'b0)
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F))
|
begin
|
begin
|
$display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
$display ("*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - PCI GNT_L not deasserted during Reset 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ( (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
|
if ( (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[2])
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[1])
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[3] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[3] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[1])
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[2] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[2] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[1] & ~pci_ext_gnt_l[0])
|
|| (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[1] & ~pci_real_gnt_l)
|
|| (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
|
|| (~pci_ext_gnt_l[0] & ~pci_real_gnt_l) )
|
begin
|
begin
|
$display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
$display ("*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
$fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - More than 1 PCI GNT_L asserted 'h%x, at %t",
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
{pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ( (pci_ext_reset_l == 1'b1)
|
if ( (pci_ext_reset_l == 1'b1)
|
&& (~frame_prev & ~irdy_prev) // bus idle
|
&& (~frame_prev & ~irdy_prev) // bus idle
|
&& (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
|
&& (grant_prev != 5'h1F) && ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != 5'h1F)
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
|
&& ({pci_ext_gnt_l[3:0], pci_real_gnt_l} != grant_prev))
|
begin
|
begin
|
$display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
$display ("*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
$fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Changed from one Grant to another when bus idle 'h%x to 'h%x, at %t",
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
grant_prev, {pci_ext_gnt_l[3:0], pci_real_gnt_l}, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
|
|
// Classify bus activity and notice slow or dead devices.
|
// Classify bus activity and notice slow or dead devices.
|
// See the PCI Local Bus Spec Revision 2.2 section 3.5
|
// See the PCI Local Bus Spec Revision 2.2 section 3.5
|
reg master_activity_seen, target_activity_seen, target_subsequently_seen;
|
reg master_activity_seen, target_activity_seen, target_subsequently_seen;
|
reg [2:0] master_initial_latency_counter;
|
reg [2:0] master_initial_latency_counter;
|
reg [3:0] target_initial_latency_counter;
|
reg [3:0] target_initial_latency_counter;
|
reg [2:0] target_subsequent_latency_counter;
|
reg [2:0] target_subsequent_latency_counter;
|
reg [3:0] master_abort_timer;
|
reg [3:0] master_abort_timer;
|
reg master_abort;
|
reg master_abort;
|
|
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
always @(posedge pci_ext_clk or negedge pci_ext_reset_l)
|
begin
|
begin
|
if (pci_ext_reset_l == 1'b0)
|
if (pci_ext_reset_l == 1'b0)
|
begin
|
begin
|
master_activity_seen <= 1'b0;
|
master_activity_seen <= 1'b0;
|
master_initial_latency_counter <= 3'h0;
|
master_initial_latency_counter <= 3'h0;
|
target_activity_seen <= 1'b0;
|
target_activity_seen <= 1'b0;
|
target_initial_latency_counter <= 4'h0;
|
target_initial_latency_counter <= 4'h0;
|
target_subsequently_seen <= 1'b0;
|
target_subsequently_seen <= 1'b0;
|
target_subsequent_latency_counter <= 3'h0;
|
target_subsequent_latency_counter <= 3'h0;
|
master_abort_timer <= 4'h0;
|
master_abort_timer <= 4'h0;
|
master_abort <= 1'b0;
|
master_abort <= 1'b0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
if ((address_phase_prev) | (~frame_prev & ~irdy_prev)) // address or idle
|
if ((address_phase_prev) | (~frame_prev & ~irdy_prev)) // address or idle
|
begin
|
begin
|
master_abort_timer <= 4'h0;
|
master_abort_timer <= 4'h0;
|
master_abort <= 1'b0;
|
master_abort <= 1'b0;
|
master_activity_seen <= 1'b0;
|
master_activity_seen <= 1'b0;
|
master_initial_latency_counter <= 3'h0;
|
master_initial_latency_counter <= 3'h0;
|
target_activity_seen <= 1'b0;
|
target_activity_seen <= 1'b0;
|
target_initial_latency_counter <= 4'h0;
|
target_initial_latency_counter <= 4'h0;
|
target_subsequently_seen <= 1'b0;
|
target_subsequently_seen <= 1'b0;
|
target_subsequent_latency_counter <= 3'h0;
|
target_subsequent_latency_counter <= 3'h0;
|
end
|
end
|
else
|
else
|
begin
|
begin
|
// NOTE WORKING not debugged yet.
|
// NOTE WORKING not debugged yet.
|
master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
|
master_initial_latency_counter <= master_initial_latency_counter + 3'h1;
|
master_activity_seen <= master_activity_seen | irdy_now;
|
master_activity_seen <= master_activity_seen | irdy_now;
|
if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
|
if ((master_initial_latency_counter == 3'h7) & ~master_activity_seen)
|
begin
|
begin
|
$display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
$display ("*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Master didn't assert IRDY within 8 clocks of FRAME, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
master_activity_seen <= 1'b1;
|
master_activity_seen <= 1'b1;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
target_initial_latency_counter <= target_initial_latency_counter
|
target_initial_latency_counter <= target_initial_latency_counter
|
+ (devsel_now ? 4'h1 : 4'h0);
|
+ (devsel_now ? 4'h1 : 4'h0);
|
target_activity_seen <= target_activity_seen | trdy_now;
|
target_activity_seen <= target_activity_seen | trdy_now;
|
if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
|
if ((target_initial_latency_counter == 4'hF) & ~target_activity_seen)
|
begin
|
begin
|
$display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
$display ("*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 16 clocks of DEVSEL, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
target_activity_seen <= 1'b1;
|
target_activity_seen <= 1'b1;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
|
// NOTE This only detects Target misbehavior on the FIRST subsequent transfer!!!
|
target_subsequent_latency_counter <= target_subsequent_latency_counter
|
target_subsequent_latency_counter <= target_subsequent_latency_counter
|
+ (target_activity_seen ? 3'h1 : 3'h0);
|
+ (target_activity_seen ? 3'h1 : 3'h0);
|
target_subsequently_seen <= target_subsequently_seen
|
target_subsequently_seen <= target_subsequently_seen
|
| (target_activity_seen & trdy_now);
|
| (target_activity_seen & trdy_now);
|
if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
|
if ((target_subsequent_latency_counter == 3'h7) & ~target_subsequently_seen)
|
begin
|
begin
|
$display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
$display ("*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Target didn't assert TRDY within 8 clocks of first TRDY, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
target_subsequently_seen <= 1'b1;
|
target_subsequently_seen <= 1'b1;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
master_abort_timer <= master_abort_timer + 4'h1;
|
master_abort_timer <= master_abort_timer + 4'h1;
|
master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
|
master_abort <= (master_abort_timer >= 4'h2) ? 1'b1 : master_abort;
|
end
|
end
|
end
|
end
|
end
|
end
|
|
|
// Track the parity bit status on the bus. The rules are:
|
// Track the parity bit status on the bus. The rules are:
|
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
|
// 1) parity has to be correct whenever FRAME is asserted to be a valid address
|
// 2) parity has to be correct whenever IRDY is asserted on writes
|
// 2) parity has to be correct whenever IRDY is asserted on writes
|
// 3) parity has to be correct whenever TRDY is asserted on reads
|
// 3) parity has to be correct whenever TRDY is asserted on reads
|
// parity covers the ad bus, and the cbe wires. The PCI bus is even parity.
|
// parity covers the ad bus, and the cbe wires. The PCI bus is even parity.
|
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
|
// The number of bits set to 1 in AD plus CBE plus PAR is an EVEN number.
|
// This code will notice an error, but will only complain if the PERR and SERR
|
// This code will notice an error, but will only complain if the PERR and SERR
|
// bits don't match,
|
// bits don't match,
|
reg prev_calculated_ad_cbe_parity;
|
reg prev_calculated_ad_cbe_parity;
|
reg prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
|
reg prev_prev_calculated_ad_cbe_parity, read_operation_prev_prev;
|
reg prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
|
reg prev_prev_devsel, prev_prev_trdy, prev_prev_irdy, prev_pci_ext_par;
|
reg ad_prev_address_phase;
|
reg ad_prev_address_phase;
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
|
reg [PCI_BUS_DATA_RANGE:0] ad_prev_prev;
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
|
reg [PCI_BUS_CBE_RANGE:0] cbe_l_prev_prev;
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
// calculate 1 if an odd number of bits is set, 0 if an even number is set
|
// calculate 1 if an odd number of bits is set, 0 if an even number is set
|
prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
|
prev_calculated_ad_cbe_parity <= (^pci_ext_ad[PCI_BUS_DATA_RANGE:0])
|
^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
|
^ (^pci_ext_cbe_l[PCI_BUS_CBE_RANGE:0]);
|
prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
|
prev_prev_calculated_ad_cbe_parity <= prev_calculated_ad_cbe_parity;
|
read_operation_prev_prev <= read_operation_prev;
|
read_operation_prev_prev <= read_operation_prev;
|
ad_prev_address_phase <= address_phase_prev;
|
ad_prev_address_phase <= address_phase_prev;
|
prev_prev_devsel <= devsel_prev;
|
prev_prev_devsel <= devsel_prev;
|
prev_prev_trdy <= trdy_prev;
|
prev_prev_trdy <= trdy_prev;
|
prev_prev_irdy <= irdy_prev;
|
prev_prev_irdy <= irdy_prev;
|
prev_pci_ext_par <= pci_ext_par;
|
prev_pci_ext_par <= pci_ext_par;
|
ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
|
ad_prev_prev[PCI_BUS_DATA_RANGE:0] <= ad_prev[PCI_BUS_DATA_RANGE:0];
|
cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
|
cbe_l_prev_prev[PCI_BUS_CBE_RANGE:0] <= cbe_l_prev[PCI_BUS_CBE_RANGE:0];
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
begin
|
begin
|
if (ad_prev_address_phase)
|
if (ad_prev_address_phase)
|
begin
|
begin
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_serr_l))
|
begin
|
begin
|
$display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Undetected Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_serr_l))
|
begin
|
begin
|
$display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Invalid Address Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (read_operation_prev_prev & prev_prev_trdy)
|
if (read_operation_prev_prev & prev_prev_trdy)
|
begin
|
begin
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
begin
|
begin
|
$display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Undetected Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
begin
|
begin
|
$display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Invalid Read Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
|
if (~read_operation_prev_prev & prev_prev_irdy & prev_prev_devsel)
|
begin
|
begin
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
| ((prev_prev_calculated_ad_cbe_parity !== prev_pci_ext_par) & pci_ext_perr_l))
|
begin
|
begin
|
$display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Undetected Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
if (((prev_prev_calculated_ad_cbe_parity ^ prev_prev_calculated_ad_cbe_parity) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_pci_ext_par ^ prev_pci_ext_par) === 1'bX)
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
| ((prev_prev_calculated_ad_cbe_parity === prev_pci_ext_par) & ~pci_ext_perr_l))
|
begin
|
begin
|
$display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$display ("*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
$fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
$fdisplay (log_file_desc, "*** monitor - Invalid Write Data Parity Error, Address 'h%x, CBE 'h%x, PAR: 'h%x, at %t",
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
ad_prev_prev, cbe_l_prev_prev, prev_pci_ext_par, $time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
end
|
end
|
|
|
// Verify some of the state transitions observed on the bus.
|
// Verify some of the state transitions observed on the bus.
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
// See the PCI Local Bus Spec Revision 2.2 Appendix C.
|
// In general, transition tests should look at one present signal, and
|
// In general, transition tests should look at one present signal, and
|
// a bunch of previous signals.
|
// a bunch of previous signals.
|
// In general, simultaneous transition tests should look at two present
|
// In general, simultaneous transition tests should look at two present
|
// signals, and a bunch of previous signals.
|
// signals, and a bunch of previous signals.
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
begin
|
begin
|
if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
|
if (irdy_prev & ~read_operation_prev & ~(trdy_prev | stop_prev) & (pci_ext_ad != ad_prev))
|
begin // Appendix C line 2C
|
begin // Appendix C line 2C
|
$display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
$display ("*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Writing with IRDY Asserted and TRDY Deasserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
|
if (trdy_prev & read_operation_prev & ~irdy_prev & (pci_ext_ad != ad_prev))
|
begin // Appendix C line 2C
|
begin // Appendix C line 2C
|
$display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
$display ("*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - AD Bus Changed when Reading with TRDY Asserted and IRDY Deasserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
|
if (frame_prev & (frame_now | irdy_now) & ~address_phase_prev & ~trdy_now
|
& (pci_ext_cbe_l != cbe_l_prev))
|
& (pci_ext_cbe_l != cbe_l_prev))
|
begin // Appendix C line 3B
|
begin // Appendix C line 3B
|
$display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
$display ("*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - CBE Bus Changed when TRDY Desserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~frame_prev & frame_now & irdy_now)
|
if (~frame_prev & frame_now & irdy_now)
|
begin // Section 3.3.3.1 rule 2, Appendix C line 7B
|
begin // Section 3.3.3.1 rule 2, Appendix C line 7B
|
$display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
$display ("*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted while IRDY still Asserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~irdy_prev & irdy_now & ~frame_prev)
|
if (~irdy_prev & irdy_now & ~frame_prev)
|
begin // Appendix C line ? not in there!
|
begin // Appendix C line ? not in there!
|
$display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
$display ("*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - IRDY Asserted when FRAME Deasserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (frame_prev & ~frame_now & ~irdy_now)
|
if (frame_prev & ~frame_now & ~irdy_now)
|
begin // Section 3.3.3.1 rule 3, Appendix C line 7C
|
begin // Section 3.3.3.1 rule 3, Appendix C line 7C
|
$display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
$display ("*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - FRAME Desserted without IRDY being Asserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort)
|
& (frame_now != frame_prev))
|
& (frame_now != frame_prev))
|
begin // Section 3.3.3.1 rule 4, Appendix C line 7D
|
begin // Section 3.3.3.1 rule 4, Appendix C line 7D
|
$display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
$display ("*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
$fdisplay (log_file_desc, "*** monitor - FRAME changed while IRDY Asserted when not end of reference, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
|
if (irdy_prev & ~(trdy_prev | stop_prev | master_abort) & ~irdy_now)
|
begin // Section 3.3.3.1 rule 5, Appendix C line 7E
|
begin // Section 3.3.3.1 rule 5, Appendix C line 7E
|
$display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
$display ("*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
$fdisplay (log_file_desc, "*** monitor - IRDY Deasserted after being Asserted when not end of reference, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
|
// NOTE WORKING section 3.3.3.2.2, Appendix C line 10, REQ must be removed for
|
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
|
// NOTE WORKING IDLE and one clock on either side of IDLE upon retry or disconnect
|
if (stop_prev & frame_prev & frame_now & ~stop_now)
|
if (stop_prev & frame_prev & frame_now & ~stop_now)
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C
|
$display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
$display ("*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - STOP Deasserted while FRAME Asserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (stop_prev & ~frame_prev & frame_now & stop_now)
|
if (stop_prev & ~frame_prev & frame_now & stop_now)
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
|
begin // Section 3.3.3.2.1 rule 3, Appendix C line 12C, author addition
|
$display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
$display ("*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
$fdisplay (log_file_desc, "*** monitor - STOP didn't Deassert while FRAME Deasserted in fast back-to-back, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (devsel_prev != devsel_now))
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
$display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$display ("*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (trdy_prev != trdy_now))
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
$display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$display ("*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$fdisplay (log_file_desc, "*** monitor - TRDY changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
|
if ((trdy_prev | stop_prev) & ~irdy_prev & (stop_prev != stop_now))
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
begin // Section 3.3.3.2.1 rule 4, Appendix C line 12D
|
$display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$display ("*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$fdisplay (log_file_desc, "*** monitor - STOP changed while TRDY or STOP Asserted when not end of data phase, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~trdy_prev & trdy_now & ~devsel_now)
|
if (~trdy_prev & trdy_now & ~devsel_now)
|
begin // Appendix C line 14
|
begin // Appendix C line 14
|
$display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
$display ("*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - TRDY Asserted when DEVSEL Deasserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
|
if (~stop_prev & stop_now & ~(devsel_prev | devsel_now))
|
begin // Appendix C line 14
|
begin // Appendix C line 14
|
$display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
$display ("*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - STOP Asserted when DEVSEL Deasserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (~frame_prev & frame_now & (grant_prev == 5'h1F))
|
if (~frame_prev & frame_now & (grant_prev == 5'h1F))
|
begin // Appendix C line 21
|
begin // Appendix C line 21
|
$display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
$display ("*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
$fdisplay (log_file_desc, "*** monitor - FRAME Asserted when no GNT Asserted, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
|
if (devsel_prev & ~devsel_now & frame_prev & ~(stop_now & ~trdy_now))
|
begin // Appendix C line 30
|
begin // Appendix C line 30
|
$display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
$display ("*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
$time);
|
$time);
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
$fdisplay (log_file_desc, "*** monitor - DEVSEL Deasserted when FRAME Asserted, and no Target Abort, at %t",
|
$time);
|
$time);
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
|
|
// Verify some of the state transitions observed on the bus. See the
|
// Verify some of the state transitions observed on the bus. See the
|
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
|
// PCI Local Bus Spec Revision 2.2 section 3.2.1, plus Appendix C.
|
`ifdef VERBOSE_MONITOR_DEVICE
|
`ifdef VERBOSE_MONITOR_DEVICE
|
reg prev_pci_ext_reset_l;
|
reg prev_pci_ext_reset_l;
|
always @(pci_ext_reset_l)
|
always @(pci_ext_reset_l)
|
begin
|
begin
|
prev_pci_ext_reset_l <= pci_ext_reset_l;
|
prev_pci_ext_reset_l <= pci_ext_reset_l;
|
|
|
if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
|
if (($time > 0) && (pci_ext_reset_l !== prev_pci_ext_reset_l))
|
begin
|
begin
|
if (pci_ext_reset_l == 1'b0)
|
if (pci_ext_reset_l == 1'b0)
|
begin
|
begin
|
$display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
|
$display (" monitor - PCI External RESET_L asserted LOW at %t", $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
if (pci_ext_reset_l == 1'b1)
|
if (pci_ext_reset_l == 1'b1)
|
begin
|
begin
|
$display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
|
$display (" monitor - PCI External RESET_L deasserted HIGH at %t", $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
end
|
end
|
|
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0))
|
begin
|
begin
|
// report a Master Abort, which is not an error
|
// report a Master Abort, which is not an error
|
if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
|
if ((irdy_prev & ~irdy_now) & (~trdy_prev & ~stop_prev & master_abort))
|
begin
|
begin
|
$display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
|
$display (" monitor - IRDY Deasserted due to Master Abort, at %t", $time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
|
|
if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
|
if (~frame_prev & frame_now & irdy_prev & ~irdy_now)
|
begin
|
begin
|
$display (" Fast Back-to-Back reference with no Idle cycle started at %t",
|
$display (" Fast Back-to-Back reference with no Idle cycle started at %t",
|
$time);
|
$time);
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`endif // VERBOSE_MONITOR_DEVICE
|
`endif // VERBOSE_MONITOR_DEVICE
|
|
|
`ifdef VERBOSE_MONITOR_DEVICE
|
`ifdef VERBOSE_MONITOR_DEVICE
|
always @(posedge pci_ext_clk)
|
always @(posedge pci_ext_clk)
|
begin
|
begin
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
|
if (($time > 0) && (pci_ext_reset_l !== 1'b0) && address_phase_prev)
|
begin
|
begin
|
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
|
// command list taken from PCI Local Bus Spec Revision 2.2 section 3.1.1.
|
case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
|
case (cbe_l_prev[PCI_BUS_CBE_RANGE:0])
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
PCI_COMMAND_INTERRUPT_ACKNOWLEDGE:
|
$display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Interrupt Acknowledge started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);,
|
PCI_COMMAND_SPECIAL_CYCLE:
|
PCI_COMMAND_SPECIAL_CYCLE:
|
$display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Special Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_IO_READ:
|
PCI_COMMAND_IO_READ:
|
$display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - IO Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_IO_WRITE:
|
PCI_COMMAND_IO_WRITE:
|
$display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - IO Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_RESERVED_READ_4:
|
PCI_COMMAND_RESERVED_READ_4:
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_RESERVED_WRITE_5:
|
PCI_COMMAND_RESERVED_WRITE_5:
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_MEMORY_READ:
|
PCI_COMMAND_MEMORY_READ:
|
$display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Memory Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_MEMORY_WRITE:
|
PCI_COMMAND_MEMORY_WRITE:
|
$display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Memory Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_RESERVED_READ_8:
|
PCI_COMMAND_RESERVED_READ_8:
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_RESERVED_WRITE_9:
|
PCI_COMMAND_RESERVED_WRITE_9:
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Reserved started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_CONFIG_READ:
|
PCI_COMMAND_CONFIG_READ:
|
$display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Configuration Read started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_CONFIG_WRITE:
|
PCI_COMMAND_CONFIG_WRITE:
|
$display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Configuration Write started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_MEMORY_READ_MULTIPLE:
|
PCI_COMMAND_MEMORY_READ_MULTIPLE:
|
$display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Memory Read Multiple started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
PCI_COMMAND_DUAL_ADDRESS_CYCLE:
|
$display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Dual Address Cycle started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_MEMORY_READ_LINE:
|
PCI_COMMAND_MEMORY_READ_LINE:
|
$display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Memory Read Line started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
PCI_COMMAND_MEMORY_WRITE_INVALIDATE:
|
$display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display (" monitor - Memory Write and Invalidate started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
default:
|
default:
|
begin
|
begin
|
$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
|
$display ("*** monitor - Unknown operation started, AD: 'h%x, CBE: 'h%x, at time %t",
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
ad_prev[PCI_BUS_DATA_RANGE:0], cbe_l_prev[PCI_BUS_CBE_RANGE:0], $time);
|
$fdisplay (log_file_desc,
|
|
error_detected <= ~error_detected;
|
error_detected <= ~error_detected;
|
end
|
end
|
endcase
|
endcase
|
end
|
end
|
`NO_ELSE;
|
`NO_ELSE;
|
end
|
end
|
`endif // VERBOSE_MONITOR_DEVICE
|
`endif // VERBOSE_MONITOR_DEVICE
|
endmodule
|
|
|
|
|
initial get_pci_op.timeout_val = 32'hffff ;
|
|
|
|
reg [4:0] cur_transaction_owner ;
|
|
|
|
initial cur_transaction_owner = 5'h1F ;
|
|
|
|
task get_pci_op ;
|
|
output [31:0] address_o ;
|
|
output [3:0 ] bus_command_o ;
|
|
reg [31:0] timeout_val ;
|
|
reg in_use ;
|
|
begin:main
|
|
if (in_use === 1'b1)
|
|
begin
|
|
$display("%m re-entered!") ;
|
|
$fdisplay(log_file_desc, "%m re-entered!") ;
|
|
error_detected <= ~error_detected;
|
|
disable main ;
|
|
end
|
|
|
|
in_use = 1'b1 ;
|
|
|
|
fork
|
|
begin:get_op_blk
|
|
wait(pci_ext_reset_l === 1'b1) ;
|
|
|
|
@(posedge pci_ext_clk) ;
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while ((frame_now !== 1'b1) | (frame_prev !== 1'b0) )
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@(posedge pci_ext_clk) ;
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disable timeout_blk ;
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address_o = pci_ext_ad ;
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bus_command_o = pci_ext_cbe_l ;
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cur_transaction_owner = grant_now ;
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end
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begin:timeout_blk
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#(timeout_val) ;
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disable get_op_blk ;
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address_o = 32'hxxxx_xxxx ;
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bus_command_o = 4'hx ;
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end
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join
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in_use = 1'b0 ;
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end
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endtask // get_pci_op
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task get_pci_op_num_of_transfers ;
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output [31:0] num_of_transfers_o ;
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output gnt_deasserted_o ;
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reg [7:0] num_of_cycles_without_transfer ;
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reg in_use ;
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begin:main
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if (in_use === 1'b1)
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begin
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$display("%m re-entered!") ;
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$fdisplay(log_file_desc, "%m re-entered!") ;
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error_detected <= ~error_detected;
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disable main ;
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end
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in_use = 1'b1 ;
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num_of_transfers_o = 0 ;
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num_of_cycles_without_transfer = 0 ;
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@(posedge pci_ext_clk) ;
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while( (frame_now === 1'b1) & (num_of_cycles_without_transfer < 128) )
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begin
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if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
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begin
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num_of_transfers_o = num_of_transfers_o + 1'b1 ;
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num_of_cycles_without_transfer = 0 ;
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end
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else
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begin
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num_of_cycles_without_transfer = num_of_cycles_without_transfer + 1'b1 ;
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end
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@(posedge pci_ext_clk) ;
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end
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if (num_of_cycles_without_transfer === 128)
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begin
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$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
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$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
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error_detected <= ~error_detected ;
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num_of_transfers_o = 32'hxxxx_xxxx ;
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gnt_deasserted_o = 1'bx ;
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end
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else
|
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begin
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gnt_deasserted_o = ( cur_transaction_owner != grant_now ) ;
|
|
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while ( (irdy_now === 1'b1) & (trdy_now === 1'b0) & (stop_now === 1'b0) )
|
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@(posedge pci_ext_clk) ;
|
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if ( (irdy_now === 1'b1) & (trdy_now === 1'b1) & (devsel_now === 1'b1))
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num_of_transfers_o = num_of_transfers_o + 1'b1 ;
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end
|
|
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in_use = 1'b0 ;
|
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end
|
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endtask // get_pci_op_num_of_transfers
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|
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task get_pci_op_num_of_cycles ;
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output [31:0] frame_asserted_cycles_o ;
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reg [31:0] num_of_cycles_after_last_data_phase_termination ;
|
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reg in_use ;
|
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begin:main
|
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if (in_use === 1'b1)
|
|
begin
|
|
$display("%m re-entered!") ;
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$fdisplay(log_file_desc, "%m re-entered!") ;
|
|
error_detected <= ~error_detected;
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disable main ;
|
|
end
|
|
|
|
in_use = 1'b1 ;
|
|
|
|
frame_asserted_cycles_o = 1 ;
|
|
num_of_cycles_after_last_data_phase_termination = 1 ;
|
|
|
|
@(posedge pci_ext_clk) ;
|
|
while( (frame_now === 1'b1) & (num_of_cycles_after_last_data_phase_termination < 128) )
|
|
begin
|
|
|
|
if (irdy_prev & trdy_prev & devsel_prev )
|
|
begin
|
|
|
|
frame_asserted_cycles_o = frame_asserted_cycles_o + num_of_cycles_after_last_data_phase_termination ;
|
|
|
|
num_of_cycles_after_last_data_phase_termination = 1 ;
|
|
end
|
|
else
|
|
num_of_cycles_after_last_data_phase_termination = num_of_cycles_after_last_data_phase_termination + 1'b1 ;
|
|
|
|
@(posedge pci_ext_clk) ;
|
|
|
|
end
|
|
|
|
if ( num_of_cycles_after_last_data_phase_termination === 128)
|
|
begin
|
|
$display("%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
|
$fdisplay(log_file_desc, "%m, no transfers in 128 pci clock cycles! Terminating!") ;
|
|
error_detected <= ~error_detected ;
|
|
frame_asserted_cycles_o = 32'hxxxx_xxxx ;
|
|
end
|
|
|
|
in_use = 1'b0 ;
|
|
end
|
|
endtask // get_pci_op_num_of_cycles
|
|
|
|
task get_pci_master_abort ;
|
|
output [31:0 ] ret_adr_o ;
|
|
output [ 3:0 ] ret_bc_o ;
|
|
output ret_mabort_detected_o ;
|
|
begin:main
|
|
ret_mabort_detected_o = 1'b0 ;
|
|
get_pci_op(ret_adr_o, ret_bc_o) ;
|
|
|
|
if ( (ret_adr_o ^ ret_adr_o) !== 0 )
|
|
disable main ;
|
|
|
|
if ( (ret_bc_o ^ ret_bc_o) !== 0 )
|
|
disable main ;
|
|
|
|
while (frame_now !== 1'b0)
|
|
begin
|
|
if (devsel_now !== 1'b0)
|
|
begin
|
|
// exit immediately on target response detection
|
|
ret_mabort_detected_o = 1'b0 ;
|
|
disable main ;
|
|
end
|
|
|
|
@(posedge pci_ext_clk) ;
|
|
end
|
|
|
|
while(irdy_now !== 1'b0)
|
|
begin
|
|
|
|
if (devsel_now !== 1'b0)
|
|
begin
|
|
// exit immediately on target response detection
|
|
ret_mabort_detected_o = 1'b0 ;
|
|
disable main ;
|
|
end
|
|
|
|
@(posedge pci_ext_clk) ;
|
|
end
|
|
|
|
ret_mabort_detected_o = 1'b1 ;
|
|
end
|
|
endtask // get_pci_master_abort
|
|
endmodule
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