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PCI IP Core
Specification
Authors: Miha Dolenc & Tadej Markovic
mihad@opencores.org
tadej@opencores.org
Rev. 0.6
TIME \@ "MMMM d, yyyy" January 28, 2002
Revision History
Rev.DateAuthorDescription0.05/1/01Miha Dolenc
Tadej MarkovicFirst Draft0.15/8/01Miha Dolenc
Tadej MarkovicWaveforms added for WISHBONE slave0.25/15/01Miha Dolenc
Tadej MarkovicDetailed description of FIFO added, Operation of PCI target unit added, Waveforms added for PCI target0.35/22/01Miha Dolenc
Tadej MarkovicFIFO structure changed0.410/13/01Jeanne WiegelmannFirst review0.510/20/01Miha Dolenc
Tadej MarkovicUpdated register descriptions and Configuration Space access0.601/28/02Miha Dolenc
Tadej MarkovicUpdated descriptions and added Software obligations
List of Contents
TOC \o "2-3" \h \z \t "Headeing 1 Name;1;Index;1;Appendix Name;1;Heading 1 appendix;1" HYPERLINK \l "_Toc156141" Introduction PAGEREF _Toc156141 \h 1
HYPERLINK \l "_Toc156142" 1.1 What is a PCI Bridge? PAGEREF _Toc156142 \h 1
HYPERLINK \l "_Toc156143" 1.2 PCI IP Core Introduction PAGEREF _Toc156143 \h 1
HYPERLINK \l "_Toc156144" 1.3 PCI IP Core Features PAGEREF _Toc156144 \h 1
HYPERLINK \l "_Toc156145" Architecture PAGEREF _Toc156145 \h 3
HYPERLINK \l "_Toc156146" 2.1 Overview PAGEREF _Toc156146 \h 3
HYPERLINK \l "_Toc156147" 2.2 WISHBONE Slave Unit PAGEREF _Toc156147 \h 4
HYPERLINK \l "_Toc156148" 2.2.1 WISHBONE Slave Unit Architecture PAGEREF _Toc156148 \h 5
HYPERLINK \l "_Toc156149" 2.3 PCI Target Unit PAGEREF _Toc156149 \h 6
HYPERLINK \l "_Toc156150" 2.3.1 PCI Target Unit Architecture PAGEREF _Toc156150 \h 6
HYPERLINK \l "_Toc156151" 2.4 Clocks PAGEREF _Toc156151 \h 8
HYPERLINK \l "_Toc156152" 2.5 FIFO PAGEREF _Toc156152 \h 8
HYPERLINK \l "_Toc156153" 2.6 Address Translation Logic PAGEREF _Toc156153 \h 10
HYPERLINK \l "_Toc156154" 2.6.1 Description of Address Translation Logic PAGEREF _Toc156154 \h 10
HYPERLINK \l "_Toc156155" Operation PAGEREF _Toc156155 \h 12
HYPERLINK \l "_Toc156156" 3.1 Configuration Space PAGEREF _Toc156156 \h 12
HYPERLINK \l "_Toc156157" 3.1.1 Configuration Space Access for Host Bus Bridges PAGEREF _Toc156157 \h 13
HYPERLINK \l "_Toc156158" 3.1.2 Configuration Space Access for Guest Bridges PAGEREF _Toc156158 \h 14
HYPERLINK \l "_Toc156159" 3.1.3 Configuration Cycles PAGEREF _Toc156159 \h 15
HYPERLINK \l "_Toc156160" 3.1.4 Generating Configuration Cycles PAGEREF _Toc156160 \h 16
HYPERLINK \l "_Toc156161" 3.1.5 Generating Interrupt Acknowledge Cycles PAGEREF _Toc156161 \h 18
HYPERLINK \l "_Toc156162" 3.2 WISHBONE Slave Unit PAGEREF _Toc156162 \h 18
HYPERLINK \l "_Toc156163" 3.2.1 WISHBONE Slave Unit Functionality PAGEREF _Toc156163 \h 19
HYPERLINK \l "_Toc156164" 3.2.2 Addressing and Images of the WISHBONE Slave Unit PAGEREF _Toc156164 \h 20
HYPERLINK \l "_Toc156165" 3.2.3 WISHBONE to PCI Write Cycles PAGEREF _Toc156165 \h 21
HYPERLINK \l "_Toc156166" 3.2.4 WISHBONE to PCI Read Cycles PAGEREF _Toc156166 \h 23
HYPERLINK \l "_Toc156167" 3.3 PCI Target Unit PAGEREF _Toc156167 \h 25
HYPERLINK \l "_Toc156168" 3.3.1 PCI Target Unit Functionality PAGEREF _Toc156168 \h 25
HYPERLINK \l "_Toc156169" 3.3.2 Addressing and Images of the PCI Target Unit PAGEREF _Toc156169 \h 26
HYPERLINK \l "_Toc156170" 3.3.3 PCI to WISHBONE Write Cycles PAGEREF _Toc156170 \h 28
HYPERLINK \l "_Toc156171" 3.3.4 PCI to WISHBONE Read Cycles PAGEREF _Toc156171 \h 30
HYPERLINK \l "_Toc156172" 3.4 Transaction Ordering PAGEREF _Toc156172 \h 32
HYPERLINK \l "_Toc156173" 3.5 Parity PAGEREF _Toc156173 \h 33
HYPERLINK \l "_Toc156174" 3.6 Interrupts PAGEREF _Toc156174 \h 33
HYPERLINK \l "_Toc156175" Registers PAGEREF _Toc156175 \h 35
HYPERLINK \l "_Toc156176" 4.1 Register List and Description PAGEREF _Toc156176 \h 35
HYPERLINK \l "_Toc156177" 4.1.1 WISHBONE Slave Unit Control & Status PAGEREF _Toc156177 \h 38
HYPERLINK \l "_Toc156178" 4.1.2 PCI Target Unit Control & Status PAGEREF _Toc156178 \h 42
HYPERLINK \l "_Toc156179" 4.1.3 Reporting Registers PAGEREF _Toc156179 \h 51
HYPERLINK \l "_Toc156180" 4.1.4 Interrupt Control & Status Registers PAGEREF _Toc156180 \h 57
HYPERLINK \l "_Toc156181" 4.2 Software obligations PAGEREF _Toc156181 \h 60
HYPERLINK \l "_Toc156182" IO Ports PAGEREF _Toc156182 \h 61
HYPERLINK \l "_Toc156183" 5.1 PCI Interface PAGEREF _Toc156183 \h 61
HYPERLINK \l "_Toc156184" 5.1.1 Required PCI Interface Pins PAGEREF _Toc156184 \h 61
HYPERLINK \l "_Toc156185" 5.1.2 Implemented Optional PCI Interface Pins PAGEREF _Toc156185 \h 62
HYPERLINK \l "_Toc156186" 5.2 WISHBONE Interface PAGEREF _Toc156186 \h 63
HYPERLINK \l "_Toc156187" Waveforms PAGEREF _Toc156187 \h 65
HYPERLINK \l "_Toc156188" 6.1 Wishbone Slave Unit PAGEREF _Toc156188 \h 65
HYPERLINK \l "_Toc156189" 6.1.1 WISHBONE Configuration Accesses PAGEREF _Toc156189 \h 65
HYPERLINK \l "_Toc156190" 6.1.2 WISHBONE to PCI Accesses PAGEREF _Toc156190 \h 67
HYPERLINK \l "_Toc156191" 6.1.3 PCI Cycles PAGEREF _Toc156191 \h 67
HYPERLINK \l "_Toc156192" 6.1.4 PCI Terminations PAGEREF _Toc156192 \h 70
HYPERLINK \l "_Toc156193" 6.2 PCI Target Unit PAGEREF _Toc156193 \h 74
HYPERLINK \l "_Toc156194" 6.1.2 PCI Configuration Accesses PAGEREF _Toc156194 \h 74
HYPERLINK \l "_Toc156195" 6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles PAGEREF _Toc156195 \h 75
HYPERLINK \l "_Toc156196" 6.2.3 WISHBONE Terminations PAGEREF _Toc156196 \h 77
HYPERLINK \l "_Toc156197" Core HW Configuration PAGEREF _Toc156197 \h 78
HYPERLINK \l "_Toc156198" A.1 HW Configuration Parameters PAGEREF _Toc156198 \h 78
HYPERLINK \l "_Toc156199" Index PAGEREF _Toc156199 \h 82
TOC \o "3-3" \h \z \t "Heading 2,2,Headeing 1 Name,1,Index,1,Appendix,1" HYPERLINK \l "_Toc530197944" Introduction PAGEREF _Toc530197944 \h 1
HYPERLINK \l "_Toc530197945" 1.1 What is a PCI Bridge? PAGEREF _Toc530197945 \h 1
HYPERLINK \l "_Toc530197946" 1.2 PCI IP Core Introduction PAGEREF _Toc530197946 \h 1
HYPERLINK \l "_Toc530197947" 1.3 PCI IP Core Features PAGEREF _Toc530197947 \h 1
HYPERLINK \l "_Toc530197948" Architecture PAGEREF _Toc530197948 \h 3
HYPERLINK \l "_Toc530197949" 2.1 Overview PAGEREF _Toc530197949 \h 3
HYPERLINK \l "_Toc530197950" 2.2 WISHBONE Slave Unit PAGEREF _Toc530197950 \h 4
HYPERLINK \l "_Toc530197951" 2.2.1 WISHBONE Slave Unit Architecture PAGEREF _Toc530197951 \h 5
HYPERLINK \l "_Toc530197952" 2.3 PCI Target Unit PAGEREF _Toc530197952 \h 6
HYPERLINK \l "_Toc530197953" 2.3.1 PCI Target Unit Architecture PAGEREF _Toc530197953 \h 6
HYPERLINK \l "_Toc530197954" 2.4 Clocks PAGEREF _Toc530197954 \h 8
HYPERLINK \l "_Toc530197955" 2.5 FIFO PAGEREF _Toc530197955 \h 8
HYPERLINK \l "_Toc530197956" 2.6 Address Translation Logic PAGEREF _Toc530197956 \h 10
HYPERLINK \l "_Toc530197957" 2.6.1 Description of Address Translation Logic PAGEREF _Toc530197957 \h 10
HYPERLINK \l "_Toc530197958" Operation PAGEREF _Toc530197958 \h 12
HYPERLINK \l "_Toc530197959" 3.1 Configuration Space PAGEREF _Toc530197959 \h 12
HYPERLINK \l "_Toc530197960" 3.1.1 Configuration Space Access for Host Bus Bridges PAGEREF _Toc530197960 \h 13
HYPERLINK \l "_Toc530197961" 3.1.2 Configuration Space Access for Guest Bridges PAGEREF _Toc530197961 \h 14
HYPERLINK \l "_Toc530197962" 3.1.3 Configuration Cycles PAGEREF _Toc530197962 \h 15
HYPERLINK \l "_Toc530197963" 3.1.4 Generating Configuration Cycles PAGEREF _Toc530197963 \h 16
HYPERLINK \l "_Toc530197964" 3.1.5 Generating Interrupt Acknowledge Cycles PAGEREF _Toc530197964 \h 18
HYPERLINK \l "_Toc530197965" 3.2 WISHBONE Slave Unit PAGEREF _Toc530197965 \h 18
HYPERLINK \l "_Toc530197966" 3.2.1 WISHBONE Slave Unit Functionality PAGEREF _Toc530197966 \h 19
HYPERLINK \l "_Toc530197967" 3.2.2 Addressing and Images of the WISHBONE Slave Unit PAGEREF _Toc530197967 \h 20
HYPERLINK \l "_Toc530197968" 3.2.3 WISHBONE to PCI Write Cycles PAGEREF _Toc530197968 \h 21
HYPERLINK \l "_Toc530197969" 3.2.4 WISHBONE to PCI Read Cycles PAGEREF _Toc530197969 \h 23
HYPERLINK \l "_Toc530197970" 3.3 PCI Target Unit PAGEREF _Toc530197970 \h 25
HYPERLINK \l "_Toc530197971" 3.3.1 PCI Target Unit Functionality PAGEREF _Toc530197971 \h 25
HYPERLINK \l "_Toc530197972" 3.3.2 Addressing and Images of the PCI Target Unit PAGEREF _Toc530197972 \h 26
HYPERLINK \l "_Toc530197973" 3.3.3 PCI to WISHBONE Write Cycles PAGEREF _Toc530197973 \h 27
HYPERLINK \l "_Toc530197974" 3.3.3.4 PCI to WISHBONE Read Cycles PAGEREF _Toc530197974 \h 30
HYPERLINK \l "_Toc530197975" 3.4 Transaction Ordering PAGEREF _Toc530197975 \h 32
HYPERLINK \l "_Toc530197976" 3.5 Parity PAGEREF _Toc530197976 \h 33
HYPERLINK \l "_Toc530197977" 3.6 Interrupts PAGEREF _Toc530197977 \h 33
HYPERLINK \l "_Toc530197978" Registers PAGEREF _Toc530197978 \h 34
HYPERLINK \l "_Toc530197979" 4.1 Register List and Description PAGEREF _Toc530197979 \h 34
HYPERLINK \l "_Toc530197980" 4.1.1 WISHBONE Slave Unit Control & Status PAGEREF _Toc530197980 \h 37
HYPERLINK \l "_Toc530197981" 4.1.2 PCI Target Unit Control & Status PAGEREF _Toc530197981 \h 41
HYPERLINK \l "_Toc530197982" 4.1.3 Reporting Registers PAGEREF _Toc530197982 \h 50
HYPERLINK \l "_Toc530197983" 4.1.4 Interrupt Control & Status Registers PAGEREF _Toc530197983 \h 56
HYPERLINK \l "_Toc530197984" IO Ports PAGEREF _Toc530197984 \h 59
HYPERLINK \l "_Toc530197985" 5.1 PCI Interface PAGEREF _Toc530197985 \h 59
HYPERLINK \l "_Toc530197986" 5.1.1 Required PCI Interface Pins PAGEREF _Toc530197986 \h 59
HYPERLINK \l "_Toc530197987" 5.1.2 Implemented Optional PCI Interface Pins PAGEREF _Toc530197987 \h 60
HYPERLINK \l "_Toc530197988" 5.2 WISHBONE Interface PAGEREF _Toc530197988 \h 61
HYPERLINK \l "_Toc530197989" Waveforms PAGEREF _Toc530197989 \h 63
HYPERLINK \l "_Toc530197990" 6.1 Wishbone Slave Unit PAGEREF _Toc530197990 \h 63
HYPERLINK \l "_Toc530197991" 6.1.1 WISHBONE Configuration Accesses PAGEREF _Toc530197991 \h 63
HYPERLINK \l "_Toc530197992" 6.1.2 WISHBONE to PCI Accesses PAGEREF _Toc530197992 \h 65
HYPERLINK \l "_Toc530197993" 6.1.3 PCI Cycles PAGEREF _Toc530197993 \h 65
HYPERLINK \l "_Toc530197994" 6.1.4 PCI Terminations PAGEREF _Toc530197994 \h 68
HYPERLINK \l "_Toc530197995" 6.2 PCI Target Unit PAGEREF _Toc530197995 \h 72
HYPERLINK \l "_Toc530197996" 6.1.2 PCI Configuration Accesses PAGEREF _Toc530197996 \h 72
HYPERLINK \l "_Toc530197997" 6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles PAGEREF _Toc530197997 \h 73
HYPERLINK \l "_Toc530197998" 6.2.3 WISHBONE Terminations PAGEREF _Toc530197998 \h 75
HYPERLINK \l "_Toc530197999" Appendix A PAGEREF _Toc530197999 \h 76
HYPERLINK \l "_Toc530198000" A.1 HW Configuration Parameters PAGEREF _Toc530198000 \h 76
HYPERLINK \l "_Toc530198001" Index PAGEREF _Toc530198001 \h 77
List of Tables
TOC \h \z \t "Caption,1" HYPERLINK \l "_Toc530198002" Table 3 1: Value on AD[31:11] PCI bus lines during address phase of configuration cycle Type 0 PAGEREF _Toc530198002 \h 17
HYPERLINK \l "_Toc530198003" Table 3 2: Valid ADDR_O(1:0) and SEL_O(3:0) combinations for I/O mapped address space access PAGEREF _Toc530198003 \h 22
HYPERLINK \l "_Toc530198004" Table 3 3: Bus command encoding for Read cycles through PCI master module PAGEREF _Toc530198004 \h 24
HYPERLINK \l "_Toc530198005" Table 3 4: Valid AD(1:0) and BE# (3:0) combinations for I/O mapped address space accesses PAGEREF _Toc530198005 \h 28
HYPERLINK \l "_Toc530198006" Table 3 5: Burst Ordering combinations for memory mapped address space accesses PAGEREF _Toc530198006 \h 29
HYPERLINK \l "_Toc530198007" Table 3 6: Bus command encoding for Read cycles through PCI target module PAGEREF _Toc530198007 \h 31
HYPERLINK \l "_Toc530198008" Table 4 1: List of registers PAGEREF _Toc530198008 \h 38
HYPERLINK \l "_Toc530198009" Table 4 2: WISHBONE configuration space Base Address register PAGEREF _Toc530198009 \h 38
HYPERLINK \l "_Toc530198010" Table 4 3: WISHBONE Image Control register PAGEREF _Toc530198010 \h 39
HYPERLINK \l "_Toc530198011" Table 4 4: WISHBONE Image Control register bit descriptions PAGEREF _Toc530198011 \h 40
HYPERLINK \l "_Toc530198012" Table 4 5: WISHBONE Base Address register PAGEREF _Toc530198012 \h 40
HYPERLINK \l "_Toc530198013" Table 4 6: WISHBONE Base Address register bit descriptions PAGEREF _Toc530198013 \h 40
HYPERLINK \l "_Toc530198014" Table 4 7: WISHBONE Address Mask register PAGEREF _Toc530198014 \h 41
HYPERLINK \l "_Toc530198015" Table 4 8: WISHBONE Address Mask register bit descriptions PAGEREF _Toc530198015 \h 41
HYPERLINK \l "_Toc530198016" Table 4 9: WISHBONE Translation Address register PAGEREF _Toc530198016 \h 42
HYPERLINK \l "_Toc530198017" Table 4 10: WISHBONE Translation Address register bit descriptions PAGEREF _Toc530198017 \h 42
HYPERLINK \l "_Toc530198018" Table 4 11: Command register of PCI configuration header PAGEREF _Toc530198018 \h 45
HYPERLINK \l "_Toc530198019" Table 4 12: Status register of PCI configuration header PAGEREF _Toc530198019 \h 46
HYPERLINK \l "_Toc530198020" Table 4 13: Base Address register of PCI configuration header for memory mapped space PAGEREF _Toc530198020 \h 47
HYPERLINK \l "_Toc530198021" Table 4 14: Base Address register of PCI configuration header for I/O mapped space PAGEREF _Toc530198021 \h 47
HYPERLINK \l "_Toc530198022" Table 4 15: PCI Image0 Base Address register PAGEREF _Toc530198022 \h 47
HYPERLINK \l "_Toc530198023" Table 4 16: PCI Image Control Register PAGEREF _Toc530198023 \h 48
HYPERLINK \l "_Toc530198024" Table 4 17: PCI Image Control Register bit descriptions PAGEREF _Toc530198024 \h 48
HYPERLINK \l "_Toc530198025" Table 4 18: PCI Base Address register PAGEREF _Toc530198025 \h 49
HYPERLINK \l "_Toc530198026" Table 4 19: PCI Base Address register bit descriptions PAGEREF _Toc530198026 \h 49
HYPERLINK \l "_Toc530198027" Table 4 20: PCI Address Mask register PAGEREF _Toc530198027 \h 50
HYPERLINK \l "_Toc530198028" Table 4 21: PCI Address Mask register bit descriptions PAGEREF _Toc530198028 \h 50
HYPERLINK \l "_Toc530198029" Table 4 22: PCI Translation Address register PAGEREF _Toc530198029 \h 51
HYPERLINK \l "_Toc530198030" Table 4 23: PCI Translation Address register bit descriptions PAGEREF _Toc530198030 \h 51
HYPERLINK \l "_Toc530198031" Table 4 24: WISHBONE Error Control and Status register PAGEREF _Toc530198031 \h 52
HYPERLINK \l "_Toc530198032" Table 4 25: WISHBONE Error Control and Status register bit descriptions PAGEREF _Toc530198032 \h 53
HYPERLINK \l "_Toc530198033" Table 4 26: WISHBONE Erroneous Address register PAGEREF _Toc530198033 \h 53
HYPERLINK \l "_Toc530198034" Table 4 27: WISHBONE Erroneous Data register PAGEREF _Toc530198034 \h 53
HYPERLINK \l "_Toc530198035" Table 4 28: PCI Error Control and Status register PAGEREF _Toc530198035 \h 53
HYPERLINK \l "_Toc530198036" Table 4 29: PCI Error Control and Status register Bit Descriptions PAGEREF _Toc530198036 \h 55
HYPERLINK \l "_Toc530198037" Table 4 30: PCI Erroneous Address register PAGEREF _Toc530198037 \h 55
HYPERLINK \l "_Toc530198038" Table 4 31: PCI Erroneous Data Register PAGEREF _Toc530198038 \h 55
HYPERLINK \l "_Toc530198039" Table 4 32: Configuration Address register PAGEREF _Toc530198039 \h 55
HYPERLINK \l "_Toc530198040" Table 4 33: Configuration Address register bit descriptions PAGEREF _Toc530198040 \h 56
HYPERLINK \l "_Toc530198041" Table 4 34: Configuration Data Register PAGEREF _Toc530198041 \h 57
HYPERLINK \l "_Toc530198042" Table 4 35: Interrupt Acknowledge register PAGEREF _Toc530198042 \h 57
HYPERLINK \l "_Toc530198043" Table 4 36: Interrupt Control register PAGEREF _Toc530198043 \h 57
HYPERLINK \l "_Toc530198044" Table 4 37: Interrupt Control Register bit descriptions PAGEREF _Toc530198044 \h 58
HYPERLINK \l "_Toc530198045" Table 4 38: Interrupt Status register PAGEREF _Toc530198045 \h 59
HYPERLINK \l "_Toc530198046" Table 4 39: Interrupt Status register bit descriptions PAGEREF _Toc530198046 \h 60
HYPERLINK \l "_Toc530198047" Table 5 1: PCI address and data pins PAGEREF _Toc530198047 \h 61
HYPERLINK \l "_Toc530198048" Table 5 2: PCI interface control pins PAGEREF _Toc530198048 \h 62
HYPERLINK \l "_Toc530198049" Table 5 3: PCI error reporting pins PAGEREF _Toc530198049 \h 62
HYPERLINK \l "_Toc530198050" Table 5 4: PCI arbitration pins (INITIATOR only) PAGEREF _Toc530198050 \h 62
HYPERLINK \l "_Toc530198051" Table 5 5: PCI system pins PAGEREF _Toc530198051 \h 62
HYPERLINK \l "_Toc530198052" Table 5 6: PCI interrupt pin PAGEREF _Toc530198052 \h 62
HYPERLINK \l "_Toc530198053" Table 5 7: PCI interface control pins PAGEREF _Toc530198053 \h 63
HYPERLINK \l "_Toc530198054" Table 5 8: PCI target units WISHBONE interface (master) PAGEREF _Toc530198054 \h 63
HYPERLINK \l "_Toc530198055" Table 5 9: WISHBONE slave units WISHBONE interface (slave) PAGEREF _Toc530198055 \h 64
HYPERLINK \l "_Toc530198056" Table 5 10: WISHBONE common control and system I/Os PAGEREF _Toc530198056 \h 64
List of Figures & Examples
TOC \h \z \t "Caption 1,1" HYPERLINK \l "_Toc530198057" Figure 2 1: PCI bridge core architecture PAGEREF _Toc530198057 \h 4
HYPERLINK \l "_Toc530198058" Figure 2 2: WISHBONE slave unit architecture PAGEREF _Toc530198058 \h 5
HYPERLINK \l "_Toc530198059" Figure 2 3: PCI target unit architecture overview PAGEREF _Toc530198059 \h 7
HYPERLINK \l "_Toc530198060" Figure 2 4: Detailed Description of FIFO Register Lines PAGEREF _Toc530198060 \h 8
HYPERLINK \l "_Toc530198061" Figure 2 5: FIFO Architecture PAGEREF _Toc530198061 \h 9
HYPERLINK \l "_Toc530198062" Figure 2 6: Address Translation Logic PAGEREF _Toc530198062 \h 11
HYPERLINK \l "_Toc530198063" Figure 3 1: PCI Bridge Configuration Space PAGEREF _Toc530198063 \h 13
HYPERLINK \l "_Toc530198064" Figure 3 2: Configuration space access for Host Bus Bridges PAGEREF _Toc530198064 \h 14
HYPERLINK \l "_Toc530198065" Figure 3 3: Configuration space access for Guest Bridges PAGEREF _Toc530198065 \h 15
HYPERLINK \l "_Toc530198066" Figure 3 4: WISHBONE Slave Unit Architecture Overview PAGEREF _Toc530198066 \h 19
HYPERLINK \l "_Toc530198067" Example 3 1: Address range of WISHBONE slave image PAGEREF _Toc530198067 \h 20
HYPERLINK \l "_Toc530198068" Example 3 2: Address translation PAGEREF _Toc530198068 \h 21
HYPERLINK \l "_Toc530198069" Figure 3 5: PCI target unit architecture overview PAGEREF _Toc530198069 \h 25
HYPERLINK \l "_Toc530198070" Example 3 3: Address range of WISHBONE slave image PAGEREF _Toc530198070 \h 27
HYPERLINK \l "_Toc530198071" Example 3 4: Address translation PAGEREF _Toc530198071 \h 28
HYPERLINK \l "_Toc530198072" Figure 4 1: WISHBONE configuration space Base Address register layout PAGEREF _Toc530198072 \h 39
HYPERLINK \l "_Toc530198073" Figure 4 2: WISHBONE Image Control register layout PAGEREF _Toc530198073 \h 39
HYPERLINK \l "_Toc530198074" Figure 4 3: WISHBONE Base Address register layout PAGEREF _Toc530198074 \h 40
HYPERLINK \l "_Toc530198075" Figure 4 4: WISHBONE Address Mask register layout PAGEREF _Toc530198075 \h 41
HYPERLINK \l "_Toc530198076" Figure 4 5: WISHBONE Translation Address register layout PAGEREF _Toc530198076 \h 42
HYPERLINK \l "_Toc530198077" Figure 4 6: PCI Configuration Space Header (Header type 00h) PAGEREF _Toc530198077 \h 43
HYPERLINK \l "_Toc530198078" Figure 4 7: PCI Image0 Base Address register layout Image0 used for accessing the PCI Configuration Space Header (type 00h) PAGEREF _Toc530198078 \h 48
HYPERLINK \l "_Toc530198079" Figure 4 8: PCI Image Control register layout PAGEREF _Toc530198079 \h 48
HYPERLINK \l "_Toc530198080" Figure 4 9: PCI Base Address Register Layout PAGEREF _Toc530198080 \h 49
HYPERLINK \l "_Toc530198081" Figure 4 10: PCI Address Mask register layout PAGEREF _Toc530198081 \h 50
HYPERLINK \l "_Toc530198082" Figure 4 11: PCI Translation Address register layout PAGEREF _Toc530198082 \h 51
HYPERLINK \l "_Toc530198083" Figure 4 12: WISHBONE Error Control and Status register layout PAGEREF _Toc530198083 \h 52
HYPERLINK \l "_Toc530198084" Figure 4 13: PCI Error Control and Status register layout PAGEREF _Toc530198084 \h 54
HYPERLINK \l "_Toc530198085" Figure 4 14: Configuration Address register layout PAGEREF _Toc530198085 \h 56
HYPERLINK \l "_Toc530198086" Figure 4 15: Interrupt Control register layout PAGEREF _Toc530198086 \h 57
HYPERLINK \l "_Toc530198087" Figure 4 16: Interrupt Status register layout PAGEREF _Toc530198087 \h 59
HYPERLINK \l "_Toc530198088" Figure 6 1: WISHBONE configuration Read cycle PAGEREF _Toc530198088 \h 65
HYPERLINK \l "_Toc530198089" Figure 6 2: WISHBONE Configuration Write cycle PAGEREF _Toc530198089 \h 66
HYPERLINK \l "_Toc530198090" Figure 6 3: WISHBONE configuration RMW cycle PAGEREF _Toc530198090 \h 66
HYPERLINK \l "_Toc530198091" Figure 6 4: WISHBONE access to PCI address space PAGEREF _Toc530198091 \h 67
HYPERLINK \l "_Toc530198092" Figure 6 5: PCI Single Read cycle PAGEREF _Toc530198092 \h 68
HYPERLINK \l "_Toc530198093" Figure 6 6: PCI Single Write PAGEREF _Toc530198093 \h 68
HYPERLINK \l "_Toc530198094" Figure 6 7: PCI Burst Read Cycle PAGEREF _Toc530198094 \h 69
HYPERLINK \l "_Toc530198095" Figure 6 8: PCI Burst Write cycle PAGEREF _Toc530198095 \h 69
HYPERLINK \l "_Toc530198096" Figure 6 9: Master Abort termination PAGEREF _Toc530198096 \h 70
HYPERLINK \l "_Toc530198097" Figure 6 10: Timeout termination PAGEREF _Toc530198097 \h 71
HYPERLINK \l "_Toc530198098" Figure 6 11: Target Abort PAGEREF _Toc530198098 \h 71
HYPERLINK \l "_Toc530198099" Figure 6 12: Target Retry PAGEREF _Toc530198099 \h 72
HYPERLINK \l "_Toc530198100" Figure 6 13: Target Disconnect without data PAGEREF _Toc530198100 \h 73
HYPERLINK \l "_Toc530198101" Figure 6 14: Target Disconnect with data PAGEREF _Toc530198101 \h 73
HYPERLINK \l "_Toc530198102" Figure 6 15: PCI Configuration Read cycle PAGEREF _Toc530198102 \h 74
HYPERLINK \l "_Toc530198103" Figure 6 16: PCI Configuration Write cycle PAGEREF _Toc530198103 \h 74
HYPERLINK \l "_Toc530198104" Figure 6 17: PCI Target Read cycle PAGEREF _Toc530198104 \h 75
HYPERLINK \l "_Toc530198105" Figure 6 18: PCI to WISHBONE Read cycle PAGEREF _Toc530198105 \h 75
HYPERLINK \l "_Toc530198106" Figure 6 19: PCI Initiator to Target Burst Read cycle PAGEREF _Toc530198106 \h 76
HYPERLINK \l "_Toc530198107" Figure 6 20: PCI Initiator to Target Burst Write cycle PAGEREF _Toc530198107 \h 76
HYPERLINK \l "_Toc530198108" Figure 6 21: WISHBONE Write transfer caused by PCI to WISHBONE Write cycle PAGEREF _Toc530198108 \h 76
HYPERLINK \l "_Toc530198109" Figure 6 22: Retry on WISHBONE bus caused by PCI to WISHBONE transfer PAGEREF _Toc530198109 \h 77
HYPERLINK \l "_Toc530198110" Figure 6 23: Error on WISHBONE bus caused by PCI to WISHBONE transfer PAGEREF _Toc530198110 \h 77
Introduction
1.1 What is a PCI Bridge?
PCI bridges XE "PCI bridge, introduction:function" are used in applications and devices that want to utilize resources provided on a PCI local bus. Systems that have multiple buses must to enable communication between them provide an interface that connects the internal buses to the PCI local bus. PCI bridges provide such an interface.
1.2 PCI IP Core Introduction
The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
The core has been designed to offer as much flexibility as possible to all kinds of applications.
1.3 PCI IP Core Features
The following lists the main features of the PCI IP core:
32-bit PCI interface
Fully PCI 2.2 compliant (with 66 MHz PCI specification)
Separated initiator and target functional blocks
Supported initiator commands and functions:
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
I/O Read, I/O Write
Configuration Read, Configuration Write
Bus Parking
Interrupt Acknowledge
Host Bridging
Supported target commands and functions:
Type 0 Configuration Space Header
(Type 0 is used to configure agents on the same bus segment)
(Type 1 is used to configure across PCI-to-PCI bridges) Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
Memory Write and Invalidate (MWI)
I/O Read, I/O Write
Configuration Read, Configuration Write
Target Abort, Target Retry, Target Disconnect
Fast Back-to-Back Capable Target response
Full Command/Status registers
WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
Configurable on-chip FIFOs XE "features, PCI IP core" \r "features"
Architecture
2.1 Overview
The PCI bridge consists of two units: the PCI target unit XE "PCI target unit" XE "PCI bridge, introduction:PCI target unit" and the WISHBONE slave unit XE "PCI bridge, introduction:WISHBONE slave unit" . Each holds its own set of functions to support bridging operations from WISHBONE to PCI and from PCI to WISHBONE. The WISHBONE slave unit acts as a slave on the WISHBONE side of the bridge and initiates transactions as a master on the PCI bus. The PCI target unit acts as a target on the PCI side of the bridge and as a master on its WISHBONE side. Both units operate independently of each other. The PCI target unit implements the target interface on the PCI bus and the master interface on the WISHBONE bus, the WISHBONE slave unit implements the slave interface on the WISHBONE bus and the master interface on the PCI bus.
The PCI interface XE "compliances:PCI interface" is PCI Specification 2.2 compliant, whereas the WISHBONE XE "compliances:WISHBONE" is SoC Interconnection Specification Rev. B compliant. The WISHBONE implementation carries out 32-bit bus operations and does not support other bus widths.
Following figure gives an overview of the PCI bridge core architecture XE "PCI bridge, introduction:architecture" XE "architecture:PCI bridge, general overview" .
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 1: PCI bridge core architecture
2.2 WISHBONE Slave Unit
The WISHBONE bus agents XE "WISHBONE:bus agents" can access the PCI bus through the WISHBONE slave unit XE "WISHBONE:slave unit:function" . One to five configurable images XE "WISHBONE:slave unit:images, configurable" can be used to access the PCI address space.
Each image consists of:
Base address register
Address mask register
Translation address register
Image control register
Decoder
The Base address, stored in the Base Address register, is masked with a value stored in the Address Mask register. The decoder XE "decoder" XE "WISHBONE:slave unit:decoder" compares the WISHBONE bus address with the masked base address to identify valid WISHBONE cycles. If needed, each valid address can be translated to a different value before accessing the PCI bus. The value for an address to be presented on the PCI bus is stored in the Address Translation register. The Image Control register is used to control the behavior of an image.
Each image can be configured to access memory or I/O address space on the PCI bus.
Write cycles through the WB slave unit are processed as Posted Writes XE "write cycles:posted writes" and Read cycles as delayed read XE "read cycles:delayed reads" s. Reads can also be pre-fetched if the image accessed is configured properly. The only exception to that rule is Configuration Write, which is initiated by a special mechanism and therefore described separately in subsequent chapters.
The WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" (WBW_FIFO) is used to post writes performed on the WISHBONE bus; the WISHBONE XE "WISHBONE:slave unit:read FIFO" Read FIFO XE "FIFO:WISHBONE read FIFO" (WBR_FIFO) accumulates pre-fetched reads. The WISHBONE slave unit connects to WISHBONE masters by acting as a slave.
This section describes the architecture of a WISHBONE slave unit and is divided into subsections.
2.2.1 WISHBONE Slave Unit Architecture
The WISHBONE slave unit consists of a few functional parts allowing the WISHBONE master to perform Read/Write access to the PCI bus. The following sections provide detailed descriptions.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 2: WISHBONE slave unit architecture
2.2.1.1 WISHBONE Slave Module
The WISHBONE slave module XE "WISHBONE:slave unit:slave module" , which includes one to six image units for address translation from the WISHBONE bus, is a 32-bit WISHBONE slave interface as defined in WISHBONE Specification Rev. 1B. It handles Read/Write cycles to images of PCI address space and configuration space accesses.
2.2.1.2 WBW_FIFO
The WISHBONE slave module uses WBW_FIFO (WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" ) for posting memory and I/O Write cycles performed by the WISHBONE master. Parameterized depth provides the option to define the WBW_FIFO with regard to application specific needs for posting more or less Write cycles.
The WISHBONE bus determines the speed of Write cycles to the WBW_FIFO, whereas the PCI bus regulates the speed of Write cycles from the WBW_FIFO.
2.2.1.3 WBR_FIFO
The WISHBONE slave module uses WBR_FIFO (WISHBONE Read FIFO XE "FIFO:WISHBONE read FIFO" XE "WISHBONE:slave module:read FIFO" ) for storing data read XE "WISHBONE:slave unit:PCI master module" from PCI targets.
The PCI bus determines the speed of Read cycles to the WBR_FIFO, and the WISHBONE bus regulates the speed of Read cycles from the WBR_FIFO.
2.2.1.4 PCI Master Module
The PCI master module uses information provided by the WISHBONE slave module to perform PCI bus cycles. It is a 32-bit/66MHz (33MHz in FPGA), PCI Local Bus Specification Rev. 2.2 compliant initiator interface. XE "WISHBONE:slave unit:architecture" \r "SlaveUnitWishboneArchitecture" XE "architecture:WISHBONE slave unit" \r "SlaveUnitWishboneArchitecture"
2.3 PCI Target Unit
PCI agents can access the WISHBONE bus through the PCI target unit XE "PCI target unit:function" of the bridge, which provides twoone to six images of the WISHBONE side memory space. Each image is selected XE "PCI target unit:images, selecting" by an address provided during the address phase on the PCI bus. It is compared to the base address masked with a mask value stored in PCI Configuration registers and can be mapped into the memory or I/O space. An address can also be translated to a value stored in the Translation Address register if the image is properly configured.
Write cycles through the PCI target unit are handled as Posted Writes XE "write cycles:posted writes" . Read cycles and can be pre-fetched.
The PCIW_FIFO stores Posted Write XE "write cycles:posted writes" cycles; the PCIR_FIFO saves pre-fetched Read cycles.
2.3.1 PCI Target Unit Architecture
This part describes the architecture of the PCI target unit. The following sections provide detailed descriptions.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 3: PCI target unit architecture overview
The PCI target unit consists of a few functional parts allowing PCI initiators to perform Read/Write accesses to the WISHBONE bus.
The PCI target module is a 32-bit/66MHz (33MHz in FPGA), PCI Local Bus Specification Rev. 2.2 compliant target interface that includes two to six image units for address translation from the PCI bus. Therefore, it handles Read/Write cycles to images of WISHBONE address space and configuration space accesses.
2.3.1.1 PCI Target Module
The PCI target module XE "PCI target unit:target module" uses PCIW_FIFO (PCI Write FIFO XE "FIFO:PCI write FIFO" ) for posting memory and I/O Write cycles performed by the PCI initiator. Parameterized depth provides the option to define the PCIW_FIFO with regard to application specific needs for posting more or less Write cycles.
The PCI bus determines the speed of Write cycles to the PCIW_FIFO, whereas the WISHBONE bus regulates the speed of Write cycles from the PCIW_FIFO.
2.3.1.2 PCIR_FIFO
The WISHBONE master module uses PCIR_FIFO (PCI Read FIFO XE "FIFO:PCI read FIFO" XE "PCI target unit:read FIFO" XE "PCI target unit:read FIFO" ) for storing data read from WISHBONE slaves.
The WISHBONE bus determines the speed of Read cycles to PCIR_FIFO, and the PCI bus regulates the speed of Read cycles from the PCIR_FIFO.
2.3.1.3 WISHBONE Master Module
The WISHBONE master module XE "PCI target unit:WISHBONE master module" is a 32-bit WISHBONE master interface as defined in WISHBONE Specification Rev. 1B. Through its WISHBONE master module, the core sends requests to the WISHBONE bus. Chapter REF _Ref527740890 \h 5.2 WISHBONE Interface, provides detailed information on the WISHBONE interface of the core. XE "PCI target unit:architecture" \r "TargetUnitPCI" XE "architecture:PCI target unit" \r "TargetUnitPCI"
2.4 Clocks
The PCI core has two clock XE "architecture:clocks" XE "clocks" domains, one from the PCI bus, the other one from the WISHBONE bus. With its interconnection logic, the FIFO XE "FIFO:architecture" adjusts the different bus clocks. There is no difference between all four FIFOs, because it is not decisive which bus operates on higher frequency.
2.5 FIFO
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 4: Detailed Description of FIFO XE "FIFO:register lines" Register Lines
The FIFO is structured by more than one line. The number of FIFO lines, which is configurable, determines the depth number (the Design Document and Implementation Notes discuss in detail how FIFO depth is defined). REF _Ref514001600 \h \* MERGEFORMAT Figure 2 4 describes the structure of one FIFO line, which consists of 4 control bits (the Design Document describes in detail how they are usede.g. one bit is used to sign the last data of the burst transfer etc.), 4 command or byte enable bits (coding will be described in detail in the Design Document), and 32 address or data bits.
FIFOs are implemented as circular data buffers between WISHBONE and PCI interfaces ( REF _Ref514006520 \h \* MERGEFORMAT Figure 2 5) and adapt to different bus speeds with their interconnection logic. The input bus clock XE "clocks" , which is also connected to FIFO registers, writes data to the input side of the FIFO. The input pointer (input counter), which has the same clock frequency as the input bus side, stores the value of the input offset address of the first free FIFO line.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 5: FIFO XE "FIFO:architechture" Architecture
The output pointer (output counter) stores the output offset address value of the first FIFO line from which data is to be read. It has the same clock XE "clocks" frequency as the output bus side that reads the data.
The comparator between both pointers (counters) validates if any data is waiting in the FIFO to be read (the Design Document describes in detail the exact counter/comparator operation). Another comparator is between the counter, which has the value of an input pointer incremented to one, and the output pointer. When both variables are equal, the FIFO is full. XE "FIFO" \r "FIFO" XE "First in First out" \t "See also FIFO" XE "First in First out" \r "FIFO" XE "architecture:FIFO" \r "FIFO"
2.6 Address Translation Logic
WISHBONE slave unit and PCI target unit incorporate several address space images. Each image must have address translation logic ( REF _Ref514007812 \h \* MERGEFORMAT Figure 2 6) including its own set of 32-bit registers XE "address translation logic:registers" :
Base Address register [31:0]
Address Mask register [31:0]
Translation Address register [31:0]
Image Control register [31:0]
2.6.1 Description of Address Translation Logic
For a description of the address translation logic, see REF _Ref514007812 \h \* MERGEFORMAT Figure 2 6. All AND blocks and OR blocks are bit-oriented operators that stand for logic operations between bits of the same weight (e.g. logic function between bit[n-2] of bus A and bit[n-2] of bus B).
The base address is written into the Base Address register. The Address Mask register, which also defines the size of an image, decides how many most significant bits are masked and replaced by translation address bits. There is a rule how to set the Address Mask register XE "address translation logic:address mask register, setting rule" : Address bits that can be masked must start with the MS bit (bit[31]) and continue to the twelfth bit (bit[11]). All bits allowed to be masked define the smallest size of 4KB that can be assigned. No zeros must be between mask bits; otherwise this image will have two base addresses but only one Base Address registera situation that does not comply with the PCI Specification.
To find out if an address falls into the correct address range XE "address translation logic:address range" , the masked bits of input address and base address must be compared (the number of masked bits defines the unchanging address of the current address range and thereby the size of this image).
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 6: Address Translation Logic XE "address translation logic:architecture" XE "architecture:address translation logic" \r "AddressTranslationLogic"
Operation
3.1 Configuration Space
Depending on core implementation, either the PCI or the WISHBONE agents have full access to configuration space XE "configuration space:access, general" . If the core is implemented as a host bus bridge, the WISHBONE slave unit has exclusive access to this space, whereas the PCI target unit has read-only access (this image can be canceled or changed to normal PCI to WB image). If the core is implemented as a guest (expansion bus bridge), exclusive access to configuration space lies with the PCI target unit and the WISHBONE slave unit has read-only access (this image can also be canceled).
Configuration space XE "configuration space:definition" has a configurable block size and is divided into two partsone intended for Configuration, Control, and Status registers of the WB slave unit, the other one for PCI Target Unit registers. If the core is implemented as a host bus bridge, accessing specific registers in the configuration space from the WISHBONE bus can generate PCI configuration cycles; otherwise, another agent on the PCI bus must perform these cycles. Configuration space is accessible only with Single Read XE "read cycles:single reads" and Single Write XE "write cycles:single writes" cycles (e.g. it cannot be accessed with bursts from the PCI side).
All registers in the configuration space of a core are 32-bits wide with 8-bit granularity. All accesses must be DWORD aligned (e.g. two LS bits of address must be 00). The PCI standard defines special encoding for those two bits used for PCI bus memory access. If any of them are non-zero, the WISHBONE slave module signals a bus error, while PCI target module stops burst after one data is transferred. To access individual bytes, the BE# signals for PCI bus access and the SEL_O signals for WISHBONE bus access must carry an appropriate value.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 1: PCI Bridge Configuration Space
3.1.1 Configuration Space Access for Host Bus Bridges
The cores host bus bridge XE "configuration space:access for host bus bridges" implementation provides two types of access to configuration space: Read/Write access for the WISHBONE slave unit and read-only access for the PCI target unit (unless all 6 PCI Target images 0 areis canceled or used to access the WISHBONE busin which case other PCI device can not read configuration space. See also REF _Ref528224024 \h 3.3.2 Addressing and Images of the PCI Target Unit and REF _Ref528223128 \h 4.1 Register List and Description). Thus, the WISHBONE master takes full responsibility for configuring core registers and any other PCI devices residing on the PCI bus. The WISHBONE side configuration space base address is predefined and cannot be changed once the core has been implemented (the Design Document describes in detail how and where the base address is defined.).
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 2: Configuration space access for Host Bus Bridges
The WISHBONE master can access configuration space either by Single Read XE "read cycles:single reads" , Single Write XE "write cycles:single writes" , or Read Modify Write XE "write cycles:read modify writes (RMW)" (RMW) cycles. If the WISHBONE master attempts a Write cycle to non-implemented space, the cycle is acknowledged by the WISHBONE slave module while Read cycles to non-implemented space return all 0s.
The PCI side configuration space base address must be set by the WISHBONE master. The WISHBONE master must perform a Write cycle to the PCI side configuration space Base Address register to enable read-only access to PCI agents. The PCI target module provides read-only access to configuration space from the PCI bus, supporting Memory Read and Memory Write commands, but ignoring all other commands. The Memory Write command has no effect on Configuration registers. During the first data phase, the PCI target module signals Target Disconnect XE "termination signals:target disconnect with data" with Data to the initiator. Read cycles to non-implemented regions of configuration space return all 0s, whereas Write cycles have no effect.
3.1.2 Configuration Space Access for Guest Bridges
The implementation of the core as a guest bridge XE "configuration space:access for guest bus bridges" (more commonly referred to as expansion bus bridge XE "expansion bus bridges" \t "See guest bus bridges" ) provides two types of configuration space access: Read/Write access for the PCI target unit and read-only access for the WISHBONE slave unit (unless WB slave image 0 is canceled). Other PCI agents take full responsibility for configuring core registers and any other PCI devices residing on the PCI bus. An agent on the PCI bus (most commonly the host bus bridge) sets the PCI side configuration space base address by performing a Type 0 configuration cycle and writing the base address to the PCI configuration space, as stated in the PCI Local Bus Specification Rev. 2.2. The PCI side configuration space Base Address register 0 holds the same value as the first Base Address register in the PCI configuration space Header at offset 0x10. This enables device-independent software to map the bridge configuration space anywhere into the memory address space. After the base address has been set by a Type 0 configuration cycle XE "configuration cycles" and the bridge is in a normal mode of operation, the PCI agent can re-map configuration space anywhere within the memory space by writing to the PCI side configuration space Base Address register 0.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 3: Configuration space access for Guest Bridges
Configuration space access can be provided to the PCI initiator as Memory Read or Memory Write. In case the PCI initiator requests configuration space access by using a different bus command, the PCI target module does not respond. If the PCI initiator attempts an access (Read or Write) to non-implemented space, the initial data phase is terminated by signaling Target Disconnect XE "termination signals:target disconnect with data" with Data XE "termination signals:target disconnect with data" . Write cycles have no effect on non-implemented configuration space, but Read cycles return all 0s.
The WISHBONE slave module provides read-only access to configuration space from the WISHBONE bus. The WISHBONE side configuration space base address is predefined and cannot be changed (the Design Document describes in detail how and where a base address is defined). The WISHBONE slave module accepts Read or Write transfers to configuration space. Write cycles to configuration space have no effect on Configuration Space registers. When the WISHBONE master attempts to access a non-implemented region, Write cycles are acknowledged with no effect on configuration space, but Read cycles return all 0s.
3.1.3 Configuration Cycles
Configuration cycles XE "configuration cycles:access to configuration space" XE "configuration space:access to configuration cycles" are another way of accessing the configuration space of the core. Only the lower 256 bytes of configuration space are available for Read/Write access with Type 0 configuration cycles for guest (expansion bus) implementation of the core. The host bus bridge implementation provides the Configuration Read operation only. Configuration Write cycles are accepted and acknowledged but have no effect on Configuration registers.
Addressing in configuration cycles is different from normal Read and Write cycles on a PCI bus (For more information, see PCI Local Bus Specification Rev 2.2, chapter 3.1.1, Command Definition).
Only Type 00h predefined header portion has been implemented in the lower 256 bytes of the configuration space (in this document also called PCI configuration space). For its organization, see PCI Local Bus Specification Rev 2.2, chapter 6.1.
3.1.4 Generating Configuration Cycles
The host bus bridge implementation of the core provides a mechanism for generating XE "configuration cycles:generating configuration cycles on a PCI bus by accessing the CNF_ADDR and CNF_DATA register.
Step 1: The WISHBONE master must write the appropriate data to the CNF_ADDR register, which holds information about register offset, function, device, and bus number. The TYPE bit in this register defines a type of configuration cycle that is generated on the PCI bus (0 = Type 0, 1 = Type 1). The Offset field in the CNF_ADDR register identifies a register offset to or from which the WISHBONE master wishes to write or read. The Function field is set to the function number of multifunctional devices being a target of configuration cycles. The Device field, which identifies the address line that drives high for generating the IDSEL signal for a Type 0 configuration cycle, is set to the device number on the PCI bus. The Bus field is set to the bus number the targeted device resides on.
Step 2: To actually begin a configuration cycle on the PCI bus, the WISHBONE master must access the CNF_DATA register. Accesses to CNF_DATA are treated as Single Delayed transactions. The WISHBONE masters access to this register is retried. If it is a Read cycle, the PCI master module arbitrates for the PCI bus, performs the Configuration Read command with byte enables provided by the WISHBONE master (signals SEL_O(3..0)), and provides data on the WISHBONE interface when the WISHBONE master retries the transaction. In case of a Write access, the PCI master module arbitrates for the PCI bus, performs a Write cycle with provided byte enables (signals SEL_O(3..0)), and acknowledges the transaction when retried by the WISHBONE master.
Driving of PCI bus AD lines during the configuration cycle address phase depends on the TYPE of the configuration cycle. If the WISHBONE master sets the TYPE bit of CNF_ADDR to 1 (indicating Type 1 configuration cycle), the value of lines on the PCI bus is driven with contents of the CNF_ADDR register (AD[31..0] <= CNF_ADDR[31..0]) during address phase. If the TYPE bit indicates TYPE 0 configuration cycle, then AD[31..11] lines on the PCI bus are driven according to the following table (driving depends on the Device field in the CNF_ADDR register):
DEVICE field valueValue on AD[31..11] lines during address phase of configuration cycle0000 00000 0000 0000 0000 0000 10000 10000 0000 0000 0000 0001 00001 00000 0000 0000 0000 0010 00001 10000 0000 0000 0000 0100 00010 00000 0000 0000 0000 1000 00010 10000 0000 0000 0001 0000 00011 00000 0000 0000 0010 0000 00011 10000 0000 0000 0100 0000 00100 00000 0000 0000 1000 0000 00100 10000 0000 0001 0000 0000 00101 00000 0000 0010 0000 0000 00101 10000 0000 0100 0000 0000 00110 00000 0000 1000 0000 0000 00110 10000 0001 0000 0000 0000 00111 00000 0010 0000 0000 0000 00111 10000 0100 0000 0000 0000 01000 00000 1000 0000 0000 0000 01000 10001 0000 0000 0000 0000 01001 00010 0000 0000 0000 0000 01001 10100 0000 0000 0000 0000 01010 01000 0000 0000 0000 0000 01010 10000 0000 0000 0000 0000 01011 00000 0000 0000 0000 0000 01011 10000 0000 0000 0000 0000 01100 00000 0000 0000 0000 0000 01100 10000 0000 0000 0000 0000 01101 00000 0000 0000 0000 0000 01101 10000 0000 0000 0000 0000 01110 00000 0000 0000 0000 0000 01110 10000 0000 0000 0000 0000 01111 00000 0000 0000 0000 0000 01111 10000 0000 0000 0000 0000 0Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 1: Value XE "field values, configuration cycles" \r "FieldValues" on AD[31:11] PCI bus lines during address phase of configuration cycle Type 0 XE "configuration cycles:field values" \r "FieldValues"
Specified driving of PCI bus lines AD[31..11] provides a mechanism for tying IDSEL signals of target devices directly to AD lines. This way, device 0 is connected with its IDSEL signal to AD[11], device number 1 to AD[12], until device 20 connects to AD[31]. A total of 21 targets can be accessed with configuration cycles through the PCI bridge. Combinations of Device field values of CNF_ADDR register 10101 through 11111 are valid and terminate Master Abort XE "termination signals:master abort" on the PCI bus since none of the targets can respond to the cycle without its IDSEL signal being asserted. Configuration Write data is discarded while Read cycles return all 1s on the WISHBONE bus. The transaction is acknowledged as specified in PCI Specification Rev. 2.2.
Other AD lines on the PCI bus are driven during the address phase of the Type 0 configuration cycle with data stored in the CNF_ADDR register, as described in PCI Specification Rev. 2.2. XE "configuration cycles" \r "ConfigurationCycles"
3.1.5 Generating Interrupt Acknowledge Cycles
A special mechanism provides the generation of Interrupt Acknowledge cycles XE "interrupt acknowledge cycles:generating" XE "configuration space:interrupt acknowledge cycles" on the PCI bus. The WISHBONE master must perform a Read cycle to the INT_ACK register. This Read cycle is treated as Single Delayed transaction retried until the PCI master module arbitrates for the PCI bus and fetches the data requested. Address and byte enables on the PCI bus are exact copies of ADR_O(31..0) and SEL(3..0). The address has no meaning during an interrupt acknowledge cycle while byte enables indicate the size of the interrupt vector returned.
Read cycles of this register from the PCI bus have no effect and return all 0s. Write cycles from the WISHBONE or PCI side are accepted but have no effect. XE "operation:configuration space" \r "ConfigurationSpace" XE "configuration space" \r "ConfigurationSpace"
3.2 WISHBONE Slave Unit
The WISHBONE slave unit connects to WISHBONE masters acting as a slave. This section describes its basic functionality. It is divided into subsections, each of them describing what the WISHBONE master needs to do to initiate WISHBONE to PCI transactions.
3.2.1 WISHBONE Slave Unit Functionality
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 4: WISHBONE Slave Unit Architecture XE "architecture:WISHBONE slave unit" Overview
The WISHBONE slave unit consists of a few functional parts allowing the WISHBONE master to perform Read/Write accesses to the PCI bus.
3.2.1.1 WISHBONE Slave Module
The WISHBONE slave module XE "WISHBONE:slave unit:slave module" is a 32-bit WISHBONE slave interface as defined in WISHBONE Specification Rev. 1B. It handles Read/Write cycles to images of PCI address space and configuration space accesses.
3.2.1.2 WBW_FIFO
The WISHBONE slave module uses WBW_FIFO (WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" ) for posting Memory and I/O Write cycles performed by the WISHBONE master. WBW_FIFO also performs a different bus clock adaptation.
3.2.1.3 WBR_FIFO
The WISHBONE slave module uses WBR_FIFO (WISHBONE Read FIFO XE "FIFO:WISHBONE read FIFO" XE "WISHBONE:slave unit:read FIFO" ) for storing data read from PCI targets. WBR_FIFO also performs a different bus clock adaptation.
3.2.1.4 PCI Master Module
The PCI master module XE "WISHBONE:slave unit:PCI master module" is a 32-bit/66MHz, PCI Local Bus Specification Rev. 2.2 compliant initiator interface. The core requests the PCI bus through its PCI master module and performs bus operations as described in the following subsections. Chapter REF _Ref527745161 \h 5.1 PCI Interface provides a detailed overview of the PCI interface of the core.
3.2.2 Addressing and Images of the WISHBONE Slave Unit
As mentioned before, the WISHBONE slave unit incorporates 1 to 5 configurable WISHBONE address space images XE "WISHBONE:slave unit:images, configurable" (the Design Document and Implementation Notes discuss in detail how the number of images is defined) and one image used for configuration space accesses from the WISHBONE bus with a fixed base address. This fixed base address points to the starting address of the configuration space. The base address for WISHBONE configuration space points to the 0x0 offset address of the whole configuration space and is different from the first Base Address register in the PCI header that is also used for the same configuration space, but different bus (PCI).
The behavior of each image is controlled by its WISHBONE Base Address (W_BA1 W_BA5), WISHBONE Translation Address (W_TA1 W_TA5), WISHBONE Image Control (W_IMG_CTRL1 W_IMG_CTRL5) and WISHBONE Address Mask (W_AM1 W_AM5) registers. Statuses, errors, and interrupts for each image are recorded in the Status registers of an image described later in this document. The WISHBONE slave module claims the cycle initiated by the master on the WISHBONE bus if one of the WISHBONE images is selected and enabled. An image is enabled if the IMG_EN bit of its W_AM register is set to 1. An image is selected when the address provided during the initial cycle on the WISHBONE bus falls into the memory range of that image. The range is determined by values of W_BA and W_AM registers. Each image can represent 4KB to 2GB of PCI address space. Whether an image is mapped to memory or I/O space is determined by the address space-mapping bit (ASM) of the images P_Bax register. If this bit is 0, the image maps to memory space, otherwise to I/0 space.
How to specify a 1MB image of PCI address space with an address range of 0x10100000 - 0x101FFFFF?
The software must write a value of 0x10100XX0 to the images Base Address register (the LSB of this register is set to 0 to indicate a memory space mapping). This way, the base address is set at 0x10100000. Twelve LS bits are marked as Dont Cares. The minimum block size is 4KB. Then, the software writes a value of 0xFFF00XXX into the W_AM register of the corresponding image. The IMG_EN bit is the MS bit and set to a value of 1 (it is also used for address masking i.e. how we limit a maximum image size to 2GB). Each bit in the W_AM register corresponds to one address line if a bit is 1, this address line is used for address comparison, and otherwise it is not. A value of 0xFFF00000 in the W_AM register means that ADDR_O(31..20) signals are compared to W_BA[31..20] values. If values match, the image is selected. In this case, ADDR_O(19..0) lines define an offset in an address range of 1MB.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 1: Address range XE "WISHBONE:slave unit:address range, example" of WISHBONE slave image
If enabled for a selected image (AT_EN bit of W_IMG_CTRLx is 1), address translation is performed between WISHBONE and PCI address by replacing the masked part of a WISHBONE address with the corresponding bits from the W_AT register. This provides very flexible address mapping.
Lets assume that base address and address mask are set as described in the previous example. We want a WISHBONE address range of 0x10100000 0x101FFFFF to be mapped elsewhere on the PCI bus, e.g. 0x01000000 0x010FFFFF. To achieve this, we need a translation of addresses coming from the WISHBONE master and set the AT_EN bit of the corresponding W_IMG_CTRL register to a value of 1 and of the corresponding W_AT register to a value of 0x01000XXX. The W_AM register is already set, so address translation replaces ADDR_O(31..20) provided by the WISHBONE master with a value of 0x010 set in the W_AT register for accesses on the PCI bus. This way, a PCI address range of 0x01000000 0x010FFFFF is accessible on the WISHBONE bus within a range of 0x10100000 0x101FFFFF.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 2: Address translation XE "WISHBONE:slave unit:address translation, example"
3.2.3 WISHBONE to PCI Write Cycles
This section gives a detailed description of Write accesses, assuming that the WISHBONE XE "WISHBONE:slave unit:write cycles to PCI" slave unit has decoded an address to fall within a range of one of its enabled images.
The WISHBONE slave module is capable of handling Single XE "write cycles:single writes" and Block Write transfers XE "write cycles:block writes" through one of its WISHBONE slave images. Read Modify Write XE "write cycles:read modify writes (RMW)" (RMF) cycles are not supported.
Note:
Serial block transfers (bursts) are still under discussion because the WISHBONE Bus Specification does not provide a mechanism to identify them. Until serial block transfers are specified, Block Write XE "write cycles:block writes" cycles will be handled as Single Write cycles XE "write cycles:single writes" . Proposal: It might be good to use an internal signal hardwired to a value indicating non-burst transfers. The definition of bursts in the WISHBONE Specification can be used to indicate whether a block transfer is serial or not. All Write cycles from the WISHBONE master to the PCI bus are handled as Posted Writes XE "write cycles:posted writes" and are acknowledged on the WISHBONE bus immediately after receiving a request (before they are finished on the PCI bus) and stored in WBW_FIFO. Each image can be mapped to I/O or memory space, which is determined by a value of the address space-mapping bit (ASM) the W_BAx register of the corresponding image. If an image maps to I/O space, serial block transfers are not possible and the WISHBONE master receives an error signal. Normal block transfers are possible to I/O and memory space since every data beat in a block is treated as Single Posted Write XE "write cycles:posted writes" cycle.
A Write cycle to an address range occupied by an image that is mapped into memory space must be DWORD-aligned (e.g. ADDR_O(1:0) must be 00), otherwise an error terminates the cycle on the WISHBONE bus.
A Write cycle to an address range occupied by an image that is mapped into I/O space must be byte-aligned. The following table describes valid SEL_O(3:0) encoding XE "WISHBONE:slave unit:encoding" XE "encoding" for different values on ADDR_O(1:0).
Value on ADDR_O(1:0) linesValid SEL_O(3:0) encoding00SEL_O(0) must be active01SEL_O(1) must be asserted, SEL_O(0) cannot be asserted10SEL_O(2) must be asserted, SEL_O(1:0) cant be asserted11SEL_O(3) must be asserted, SEL_O(2:0) cannot be assertedTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 2: Valid ADDR_O(1:0) and SEL_O(3:0) combinations for I/O mapped address space access
All other combinations are invalid. An invalid access is terminated with Error XE "termination signals:error" on the WISHBONE bus.
In some cases, Write cycles initiated by the WISHBONE master cannot be accepted and are terminated with Retry XE "termination signals:retry" :
WBW_FIFO is full or does not have enough space left to accommodate another transfer.
An uncompleted Delayed Read XE "read cycles:delayed reads" request is still pending in a WISHBONE slave unit (Write cycles cannot be posted until a Read cycle finishes on the PCI bus).
The PCI master module requests a PCI bus after a complete transaction has been stored in the WISHBONE slave unit WBW_FIFO. After the PCI bus has been granted to the PCI master module, it initiates a transaction on the PCI bus. The module uses Memory Write or I/O Write PCI bus commands, depending on the value of the address space-mapping bit (0 = memory, 1 = I/O) of the image W_BAx register. In case the WISHBONE master posted a serial Block Write XE "write cycles:block writes" cycle, the PCI master module performs a burst of the same length to the PCI target. Single Posted Write XE "write cycles:posted writes" cycles or non-serial Block Write XE "write cycles:block writes" cycles are completed as Single Write XE "write cycles:single writes" cycles on the PCI bus. If the PCI bus arbiter revokes mastership from the PCI master module (#GNT is deasserted), it finishes the current cycle and releases the PCI bus for which it afterwards has to re-arbitrate in order to continue any Posted Write XE "write cycles:posted writes" cycles left in a WBW_FIFO. The core handles Retry XE "termination signals:retry" and Target Disconnect XE "termination signals:target disconnect" terminations by retrying the transaction until it completes or some other termination is signaled.
Because all Write cycles are posted to and are therefore immediately acknowledged by the WISHBONE master, there is an alternate way of communicating errors signaled on the PCI bus when Posted Write XE "write cycles:posted writes" cycles have already been written to their final destination: Error Reporting registers provide an Error Reporting mechanism. Error Reporting must be enabled by the errors enable (ERR_EN) bit of the WISHBONE Error Control and Status (W_ERR_CS) register. When enabled, errors can generate interrupts if the error interrupt enable (EINT_EN) bit of the W_ERR_CS register is 1. Each of the Error Reporting registers stores a part of information about the Posted Write XE "write cycles:posted writes" transaction on the PCI that was terminated with an error.
A value of 1 in the error signaled bit (ERR_SIG) of the W_ERR_CS register indicates that an error has been recorded. The Field Bus Command (BC) of this register stores a bus command used for an access that has been terminated with Error XE "termination signals:error" , while field Byte Enables (BE) stores the value of byte enables during the transfer. The error source bit (ES) indicates the source of an error (1 = Master (Master Abort XE "termination signals:master abort" ), 0 = Target (Target Abort XE "termination signals:target abort" )).
W_ERR_ADDR stores a 32-bit address that the PCI master module tried to access when the error occurred.
W_ERR_DATA stores 32 bits of data used in a transfer that was terminated with an error.
Error XE "termination signals:error" terminated write transactions are discarded while other posted transactions proceed normally. XE "WISHBONE:slave unit:write cycles to PCI" \r "WriteCyclesToPCI" XE "write cycles:WISHBONE to PCI" \r "WriteCyclesToPCI" XE "WISHBONE:slave unit:error reporting mechanism" \r "ErrorReportingWISHBONE"
3.2.4 WISHBONE to PCI Read Cycles
Read cycles initiated by the WISHBONE XE "WISHBONE:slave unit:read cycles to PCI" master are handled as Single Delayed Read XE "read cycles:delayed reads" cycles. Multiple Delayed Read XE "read cycles:delayed reads" cycles are not supported. Delayed transactions must be completed on the PCI bus before they can be completed on the WISHBONE bus. The section on addressing and images has described how the WISHBONE slave unit decodes addresses to know if it is a slave for a current cycle. Handling of Read transactions is encoded in the Image Control register (W_IMG_CTRLx). There are a few options how to define the behavior of the WISHBONE slave unit during Read transactions for images mapped to memory space XE "WISHBONE:slave unit:images mapped to memory space" :
The PREF_EN bit indicates that the address range of an image is prefetchable, which means that the bridge core can pre-fetch data from the target and store it in WBR_FIFO. This method increases the system performance since a Delayed Read XE "read cycles:delayed reads" transaction only knows the starting address of the transfer.
The MRL_EN bit indicates that the PCI master module is free to use the Memory Read Line bus command for Burst Read XE "read cycles:burst reads" cycles.
When both PREF_EN and MRL_EN bits are set, the bridge will use the Memory Read multiple bus command on the PCI bus.
Images mapped to I/O space XE "WISHBONE:slave unit:images mapped to I/O space" handle any Read transaction as single Delayed Read XE "read cycles:delayed reads" cycle (not as Burst Read cycle). If the WISHBONE master attempts to perform a serial Block Read XE "read cycles:block reads" cycle from an I/O space mapped image, the cycle is terminated with an error by the WISHBONE slave module.
The bridge core performs pre-fetched Read cycles only through images mapped to memory space. Prefetchable address space is assumed only when the PREF_EN bit or MRL_EN bit of the corresponding W_IMG_CTRLx register is set, and the WISHBONE master signals a serial Block Read XE "read cycles:block reads" cycle.
Non-prefetchable address space XE "WISHBONE:slave unit:address space, non-prefetchable" is assumed for the following conditions:
Accesses to I/O mapped address space are always non-prefetched.
The WISHBONE master performs a Single or Block Read XE "read cycles:block reads" cycle, or the PREF_EN bit is cleared.
When the WISHBONE slave unit latches address and SEL(3:0) data of a Read request, the PCI master module requests mastership for the PCI bus. When mastership is granted, the PCI master module initiates a PCI Read transaction. The bus command used for the transaction depends on various parameters described in the following table:
Address space mapping of imageCycle initiated by WISHBONE masterPREF_EN bit valueMRL_EN bit valueBus command usedI/OSingle or Block ReadXXI/O Read MemorySingle or Block ReadXX
Memory Read
Serial Block Read00Memory Read01Memory Read Line10Memory Read11Memory Read MultipleTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 3: Bus command encoding XE "encoding" XE "WISHBONE:slave unit:encoding" for Read cycles through PCI master module
Read cycles to address space that is not prefechable are performed in one data phase on the PCI bus. Only those byte enables are active on the PCI bus, as SEL(3:0) data were active during the Read request. After the first data phase, the PCI master module releases the PCI bus.
All Delayed Read XE "read cycles:delayed reads" s from address space marked as prefetchable are performed in Burst Read XE "read cycles:burst reads" cycles. Here are all byte enables active on the PCI bus, since PCI bridge can not determine, which bytes are significant for a WB device, that initiated the transaction (SEL(3:0) data were active during the Read request only for first data phase). The PCI master module reads data from the target and puts it into WBR_FIFO. The PCI master module finishes a Burst Read XE "read cycles:burst reads" cycle and releases the PCI bus if any of the following conditions is met:
WBR_FIFO is full.
The target issues Target Disconnect XE "termination signals:target disconnect" .
The mastership of the PCI bus is revoked by the PCI arbiter (#GNT is de-asserted).
When the WISHBONE master retries this Read transaction, data is ready and the WISHBONE slave module pulls data out of the WBR_FIFO and provides it on the WISHBONE bus.
Any data left in WBR_FIFO after the WISHBONE master ends a Read cycle is flushed immediately.
So far, WISHBONE to PCI Read cycles have been described as if always completed successfully, but it is common for PCI bus targets or masters to generate error terminations. Terminations from the PCI bus must be propagated to the WISHBONE bus to let the WISHBONE master know what happened to the transaction it initiated.
The PCI target is capable to operate the following terminations XE "PCI target unit:termination signals" :
Retry XE "termination signals:retry"
Disconnect XE "termination signals:disconnect with data" with data
Disconnect XE "termination signals:disconnect without data" without data
Target Abort XE "termination signals:target abort"
The Retry XE "termination signals:retry" termination is not propagated back to the WISHBONE bus. The bridge core simply retries the transaction.
Disconnect XE "termination signals:disconnect" is a valid termination for Single Read XE "read cycles:single reads" cycles. The PCI master module does not retry these transactions but stores data for Single Read XE "read cycles:single reads" cycles and waits for the WISHBONE master to fetch it.
Target Abort XE "termination signals:target abort" is an error signaled to the WISHBONE master. Retrying the transaction, it receives a bus error termination (the WISHBONE slave module asserts ERR_I).
Master Abort XE "termination signals:master abort" is an error termination. The WISHBONE master receives an error when a transaction ends with Master Abort XE "termination signals:master abort" on the PCI bus. The only exception to this rule is a Configuration Read cycle, which returns all 0s. XE "operation:WISHBONE slave unit" \r "SlaveUnitWishboneOperation" XE "WISHBONE:slave unit:operation" \r "SlaveUnitWishboneOperation" XE "WISHBONE:slave unit:read cycles to PCI" XE "read cycles:WISHBONE to PCI" \r "WriteCyclesToPCI"
Block Read length can be of Cache Line size or WBR_FIFO depth. It is the WBR_FIFO depth if Memory Read Multiple bus command is performed on the PCI bus (see REF _Ref71325 \h Table 3 3, when this command is performed). But there is NO Block Read if Cache Line size is set to 1 or it is set to unsupported value (valid Cache Line sizes are multiples of 4 - see chapter 4.1.2).
3.3 PCI Target Unit
The PCI target unit connects to PCI initiators acting as a target. This section describes the basic functionality XE "PCI target unit:basic functionality" of the PCI target unit and is divided into subsections, each of them defining what a PCI initiator needs to do to initiate PCI to WISHBONE transactions.
3.3.1 PCI Target Unit Functionality
This part gives a functional overview of the PCI target unit. Detailed description is provided in the following sections.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 5: PCI target unit architecture overview XE "architecture:PCI target unit" XE "PCI target unit:architecture"
The PCI target unit consists of several functional parts allowing PCI initiators to perform Read/Write access to the WISHBONE bus.
3.3.1.1 PCI Target Module
The PCI target module XE "PCI target unit:target module" is a 32-bit/66MHz (33MHz for FPGA implementation) PCI Local Bus Specification Rev. 2.2 compliant target interface. It handles Read/Write cycles to images of WISHBONE address space and configuration space accesses.
3.3.1.2 PCIW_FIFO
The PCI target module uses PCIW_FIFO (PCI Write FIFO XE "FIFO:PCI write FIFO" XE "PCI target unit:write FIFO" ) for posting Memory and I/O Write cycles performed by the PCI initiator. PCIW_FIFO also performs a different bus clock adaptation.
3.3.1.3 PCIR_FIFO
The WISHBONE master module uses PCIR_FIFO (PCI Read FIFO XE "FIFO:PCI read FIFO" XE "PCI target unit:read FIFO" ) for storing data read from WISHBONE slaves. PCIR_FIFO performs a different bus clock adaptation.
3.3.1.4 WISHBONE Master Module
The WISHBONE master module XE "PCI target unit:WISHBONE master module" is a 32-bit WISHBONE master interface as defined in WISHBONE Specification Rev. 1B. The core requests the WISHBONE bus through its WISHBONE master module. Chapter REF _Ref527749431 \h 5.2 WISHBONE Interface, describes in detail the WISHBONE interface of the core.
3.3.2 Addressing and Images of the PCI Target Unit
As mentioned above, the PCI target unit incorporates 1 to 5 configurable PCI address space images XE "PCI target unit:images, configurable" (The Design Document and Implementation Notes discuss in detail how to define the number of images) and one special image used for configuration space accesses from the PCI bus with a configurable base address. In host bridge implementations, this special image can be configured to provide access to normal address space or can be canceled therefore configuration space would not be accessible (see also REF _Ref528223750 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528223783 \h 4.1 Register List and Description).
The behavior of each image is controlled by its PCI Base Address (P_BA0 P_BA5), PCI Translation Address (P_TA0 P_TA5), PCI Image Control (P_IMG_CTRL0 P_IMG_CTRL5), and PCI Address Mask (P_AM0 P_AM5) registers. Status, errors, and interrupts for each image are recorded in the Status registers described later in this document. The PCI target module claims the cycle started by the initiator on the PCI bus if one of the PCI images is selected and enabled. An image is enabled if the IMG_EN bit of its P_AM register is set to 1. An image is selected when the address provided during the initial cycle on the PCI bus is placed within the memory range of that image. The range is determined with values of P_BA and P_AM registers. Each image can represent 4KB to 2GB of the WISHBONE address space.
Each image can be mapped to memory or I/O space, determined by the address space-mapping bit (ASM) of the images P_BAx register (bit 0). If the ASM bit is 0, the image maps to memory space, and otherwise to I/O space. For host bridge implementations, the predefined values can later be changed by writing an appropriate value, but for guest bridge implementations, the predefined values are fixed (hardwired), because device independent software must know in advance where to map each PCI Base Address.
How to specify a 1MB image of WISHBONE address space with an address range of 0x10100000 0x101FFFFF?
Software must write a value of 0x10100XX0 to the Base Address register of an image (the LSB of this register is set to 0 to indicate memory space mapping). This way, the base address is set at 0x10100000. Twelve LS bits are marked as Dont Cares. The minimum block size is 4KB.Software writes a value of 0xFFF00XXX into the P_AM register of the corresponding image. The MS bit is the IMG_EN bit, which is set to a value of 1. It is also used for address masking, i.e. how we limit a maximum image size to 2GB. Each bit in the P_AM register corresponds to one address line. If the bit is 1, then this address line is used in address comparison, and otherwise it is not. A value of 0xFFF00000 in the P_AM register means that ADDR_O(31..20) signals are compared with a P_BA[31..20] value. If values match, the image is selected. In this case, ADDR_O(19..0) lines define an offset in an address range of 1MB.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 3: Address range XE "PCI target unit:address range, example" of WISHBONE slave image
If address translation is enabled for a selected image (AT_EN bit of P_IMG_CTRLx is 1), it is performed between PCI and WISHBONE address. Address translation is done by replacing the masked part of the PCI address with the corresponding bits from the P_AT register. This provides very flexible address mapping (off course address translation must be implemented).
Lets assume that base address and address mask are set as described in previous example. We want a PCI address range of 0x10100000 0x101FFFFF to be mapped elsewhere on the WISHBONE bus, e.g. at 0x01000000 0x010FFFFF. To achieve this, we need a translation of addresses coming from the PCI initiator. The AT_EN bit of the corresponding IMG_CTRL register is set to a value of 1 and of the corresponding P_AT register to a value of 0x01000XXX, respectively. The P_AM register is already set, so address translation replaces AD(31..20) provided by the PCI initiator with a 0x010 value set in the P_AT register for accesses on the WISHBONE bus. This way, we have a WISHBONE address range of 0x01000000 0x010FFFFF, accessible on the PCI bus in a range of 0x10100000 0x101FFFFF.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 4: Address translation XE "PCI target unit:address translation, example"
3.3.3 PCI to WISHBONE Write Cycles
The previous section described how a PCI target unit knows if it is the target of a current cycle initiated by a PCI initiator. In this section, Write accesses are described in detail, assuming that a PCI target unit decodes an address to fall within a range of one of its enabled images.
The PCI target module is capable of handling Single XE "write cycles:single writes" and Burst Write transfers through one of its PCI target images.
Note:
Serial block transfers (bursts on the WISHBONE bus) are still under discussion because the WISHBONE Bus Specification does not provide a mechanism to identify them. Until serial block transfers will be specified, all bursts from the PCI bus are handled as Block Write XE "write cycles:block writes" cycles.
All Write cycles from the PCI master to the WISHBONE bus are handled as Posted Writes XE "write cycles:posted writes" . Due to this, the Read Modify Write command is not supported on the WISHBONE bus. Write cycles are claimed on the PCI bus immediately after receiving a request and are stored in PCIW_FIFO. Each image can be mapped to I/O or memory space that is determined by a value of the address space-mapping bit (ASM) in the P_BAx register of the corresponding image (for guest bridges ASM bit is fixed, for host bridges ASM bit can be changed, see chapter 3.3.2).
If an image maps to I/O space, all 32 AD lines are used for full byte address decoding, and AD(1:0) lines indicate the least significant valid byte for the transaction. The byte enable lines BE#(3:0) indicate the size of the transfer within the DWORD. They must be consistent with AD(1:0) as seen in REF _Ref514473566 \h \* MERGEFORMAT Table 3 5. All other combinations are invalid. Invalid access is terminated with Target Abort XE "termination signals:target abort" on the PCI bus.
All PCI bursts to I/O space are treated as Single Posted Write XE "write cycles:posted writes" s; therefore, Burst transfers are broken into single transfers. Their data phase is terminated with Target Disconnect XE "termination signals:target disconnect with data" with Data. The PCI initiator then attempts to perform the next access with the data following the first transfer. This is repeated until the burst transfer has finished.
Value on AD(1:0) linesStarting ByteValid BE#(3:0) encoding XE "PCI target unit:encoding" XE "encoding" 00Byte 0xxx001Byte 1xx0110Byte 2x01111Byte 30111Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 4: Valid AD(1:0) and BE# (3:0) combinations for I/O mapped address space accesses XE "PCI target unit:address space access:I/O mapped"
If an image maps to memory space, 30 AD lines (the AD(31:2) bus) provide a DWORD-aligned address. The AD(1:0) lines are not part of the address decoded, but they indicate the order in which the PCI initiator requests data to be transferred, as seen in REF _Ref514473566 \h \* MERGEFORMAT Table 3 5. The Linear Incrementing Burst mode is fully supported, while the Cache-line Wrap mode is broken into single transfers whose data phase is terminated with Target Disconnect XE "termination signals:target disconnect with data" with Data. The PCI initiator then attempts to perform the next access with the data following the first transfer. This is repeated until the Cache-line Wrap mode burst transfer has finished.
Value on AD(1:0) linesBurst Ordering encoding XE "PCI target unit:encoding" XE "encoding" 00Linear Incrementing01Reserved (disconnect after first data phase)10Cache-line Wrap mode11Reserved (disconnect after first data phase)Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 5: Burst Ordering combinations for memory mapped address space accesses XE "PCI target unit:address space access:memory mapped"
All other combinations are reserved (because of an earlier version of the PCI Specification). Therefore, accesses must be terminated with Disconnect XE "termination signals:disconnect" after the first data phase, but requested memory address space is not affected. There are additional reasons for the PCI target to terminate a current bus-cycle.
When the PCI target unit is unable to respond within its subsequent latency requirement, it terminates a transfer with Disconnect XE "termination signals:disconnect with/without data" with/without Data while data is being transferred, or immediately afterwards, on the initial data phase. This applies to the following conditions:
The target is not capable of doing a burst (as mentioned above).
The target is temporarily unable to continue bursting when PCIW_FIFO is already fulfilled with the current Burst Write XE "write cycles:burst writes" .
The PCI target unit abnormally terminates a transfer with Target Abort XE "termination signals:target abort" when it detects a fatal error of the following kind (otherwise it would not be able to complete the requested transfer):
The master initiates a non-valid combination of AD(1:0) and BE#(3:0) when accessing I/O mapped image space (as mentioned above).
When it is busy and temporarily unable to process the transaction, the PCI target unit terminates a transfer with Retry XE "termination signals:retry" before any data is transferred. This applies to the following situations:
An internal resource conflict emerges when PCIW_FIFO is full or cannot provide enough space to accommodate another burst transfer.
The target is locked by another master when an uncompleted Delayed Read XE "read cycles:delayed reads" request is still pending in a PCI target unit (Write cycles cannot be posted until a Read cycle finishes on the WISHBONE bus).
The target is locked by WBU, when there is still a WB to PCI delayed read pending or processing.
All PCI bus transfer terminations described above are PCI target terminations, but masters may also terminate transactions.
Regardless whether image mapping occurs to MEMORY or I/O space, the PCI initiator or target can insert wait cycles into the current Write transfer.
The PCI target module must perform address decoding every time the PCI initiator induces a Write transfer in order to determine if this transfer is related to it. The WISHBONE master module initiates a transaction on the WISHBONE bus after a complete transaction has been stored in the PCIW_FIFO unit of the PCI target. The module uses Single Write XE "write cycles:single writes" or Block Write XE "write cycles:block writes" transfers, depending on the value of the control bit in the PCIW_FIFO line that indicates a burst from the PCI bus. Block Write XE "write cycles:block writes" cycles on the WISHBONE bus have the same length as bursts from the PCI. If a burst on the PCI bus was cut because of smaller PCIW_FIFO depth, the block size is as large as the size of the burst written into the PCIW_FIFO. When a PCI initiator completes a Burst Write XE "write cycles:burst writes" cycle with the next access, it is treated as a new burst transfer written to PCIW_FIFO.
Because all Write cycles are posted and therefore immediately claimed by the PCI Target module and stored to the PCIW_FIFO, there is an alternate way of communicating errors signaled on a WISHBONE bus when Posted Write XE "write cycles:posted writes" cycles actually have been written to their final destinationthe mechanism of Error Reporting, which is provided through Error XE "termination signals:error" Reporting registers. The error enable bit (ERR_EN) of the PCI Error XE "termination signals:error" Control and Status register (P_ERR_CS) must enable this mechanism. If Error XE "termination signals:error" Reporting is enabled, errors can generate interrupts when the error interrupt enable bit (EINT_EN) of the P_ERR_CS register is 1. Each Error XE "termination signals:error" Reporting register stores part of the information about the Posted Write XE "write cycles:posted writes" transaction on the WISHBONE bus that was terminated with an error.
A value of 1 in the error signaled bit (ERR_SIG) of the P_ERR_CS register indicates that an error has been recorded. The Field Bus Command (BC) of this register stores the bus command used on the PCI bus for the access that terminated with an error on the WISHBONE bus while the field Byte Enables (BE) stores the value of byte enables (SEL_O(3:0) lines) during the transfer.
P_ERR_ADDR stores the 32-bit address the WISHBONE master module tried to access when the error occurred.
P_ERR_DATA stores the 32 bits of data used in the transfer on the WISHBONE bus that terminated with an error.
Only the Write transaction that generated an error is discarded, any subsequent transactions are processed normally. XE "PCI target unit:write cycles to WISHBONE" \r "WriteCyclesToWISHBONE" XE "write cycles:PCI to WISHBONE" \r "WriteCyclesToWISHBONE" XE "PCI target unit:error reporting mechanism" \r "ErrorReportingPCI"
3.3.3.4 PCI to WISHBONE Read Cycles
Read cycles induced by the PCI initiator are handled as Single Delayed Read XE "read cycles:delayed reads" cycles. This explains why the Read Modify Write command on the WISHBONE bus as well as Multiple Delayed Read XE "read cycles:delayed reads" cycles are not supported. Delayed transactions must be completed on the WISHBONE bus before they can complete on the PCI bus.
Above, the section on addressing and images described how the PCI target unit decodes an address to find out if it is the target for a current cycle. Handling Read transactions is encoded in the PCI Image Control register (P_IMG_CTRLx). To define the PCI target units behavior towards images mapped to memory space XE "PCI target unit:images mapped to memory space" during Read transactions, several options exist:
The PREF_EN bit indicates that the address range of the PCI memory image is prefetchable, which means that the bridge core can pre-fetch data from the slave and store it in WBR_FIFO. This method increases system performance since the Delayed Read XE "read cycles:delayed reads" transaction has information on starting address of the transfer only. Read below REF _Ref68697 \h Table 3 6 for valid byte enables information.
Images mapped to I/O space XE "PCI target unit:images mapped to I/O space" handle any Read transaction as Single Delayed Read XE "read cycles:delayed reads" cycle (no bursts). If the PCI initiator attempts a Burst Read XE "read cycles:burst reads" cycle from an image mapped to I/O space, the cycle is terminated with Disconnect XE "termination signals:disconnect with data" with Data; thus the initiator can continue reading the rest of the data (by disconnecting the bursts).
The bridge core performs pre-fetched Reads only through images mapped to memory space. Prefetchable address space is assumed for the following conditions:
The PREF_EN bit of the corresponding P_IMG_CTRLx register is set (see REF _Ref68697 \h Table 3 6).
Non-prefetchable address space XE "PCI target unit:address space, non-prefetchable" is assumed for the following conditions:
Accesses to I/O mapped address space are always non-prefetched.
The PCI initiator performs a Single Read XE "read cycles:single reads" cycle, and the PREF_EN bit is cleared.
The following table shows PCI bus Read commands that are considered single or block transfers regarding the PREF_EN bit.
Address space mapping of imageBus command initiated by PCI initiatorPREF_EN bit valueUsed cycle by WISHBONE masterI/OI/O ReadXSingle ReadMemoryMemory Read0Single ReadMemory Read1Block ReadMemory Read LineXBlock ReadMemory Read MultipleXBlock ReadTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 6: Bus command encoding XE "encoding" XE "PCI target unit:encoding" for Read cycles through PCI target module
Non-prefetchable address spaceSingle Read cycles are performed in one data phase on the WISHBONE bus. Only those byte enables (SEL(3:0)) are active on the WB bus, as PCI byte enables were active during the Read request. After the first data phase, the WISHBONE master module releases the WISHBONE bus.
All Delayed Read XE "read cycles:delayed reads" cycles from memory address space marked as prefetchable (and MRL and MRM commands) are performed as Block Read XE "read cycles:block reads" cycles. Here are all byte enables active on the WB bus, since PCI bridge can not determine, which bytes are significant for a PCI device, that initiated the transaction (PCI byte enables were active during the Read request only for first data phase). The WISHBONE master module reads data from the WISHBONE slave and puts it into PCIR_FIFO. It finishes a Block Read XE "read cycles:block reads" cycle and releases the WISHBONE bus if any of the following conditions occurs:
PCIR_FIFO is full.
The WISHBONE slave issues Error XE "termination signals:error" or Retry XE "termination signals:retry" .
When the PCI initiator retries this Read transaction, data is ready and the PCI target module pulls out data from PCIR_FIFO and provides it on the PCI bus. When PCIR_FIFO is empty or the PCI initiator issues the Read cycle of an address that is not one DWORD higher than the previous address within the same block transfer, the PCI target module latches information about a new Read request and terminates the cycle with Retry XE "termination signals:retry" .
Any data left in PCIR_FIFO is flushed immediately.
Until now, PCI TO WISHBONE reads have been described as though all of them are completed successfully, but it is common for WISHBONE bus slaves or masters to generate error terminations. Terminations from the WISHBONE bus must be propagated to the PCI bus in to let the PCI initiator know what happened with the initiated transaction.
Following terminations XE "WISHBONE:slave unit:termination signals" are possible through WISHBONE slaves:
Retry XE "termination signals:retry" , which is not propagated back to the PCI bus. The bridge core simply retries the transaction.
Error XE "termination signals:error" is a termination signaled to the PCI initiator. Retrying the transaction, the PCI initiator receives Target Abort XE "termination signals:target abort" .
There are additional reasons for the PCI target to terminate a current bus cycle.
The PCI target unit terminates XE "PCI target unit:termination signals" a transfer with Disconnect XE "termination signals:disconnect with/without data" with/without Data while data is being transferred, or immediately afterwards, on the initial data phase, when it is unable to respond within its subsequent latency requirement:
The target is not capable of doing a burst (reading from I/O mapped space, as mentioned above).
The target is temporarily unable to continue bursting when PCIR_FIFO is cleared of the current Burst Read XE "read cycles:burst reads" cycle.
The PCI target unit abnormally terminates a transfer with Target Abort XE "termination signals:target abort" (otherwise it will never be able to complete the requested transfer) if the master initiates a non-valid combination of AD(1:0) and BE#(3:0) when accessing the I/O mapped image space.
The PCI target unit terminates a transfer with Retry XE "termination signals:retry" before any data is transferred when it is busy and temporarily unable to process the transaction. An internal resource conflict emerges when PCIR_FIFO is empty.
All PCI bus transfer terminations described above are PCI target terminations, but masters may also terminate transactions.
Regardless whether image mapping occurs to MEMORY or I/O space, the PCI initiator or target can insert Wait cycles into the current Write transfer.
On the other side of the PCI target module, the side of the WISHBONE master unit, the WISHBONE slave can also insert Wait cycles.
Block Read length can be of Cache Line size or PCIR_FIFO depth. It is the PCIR_FIFO depth if Memory Read Multiple bus command was performed on the PCI bus (see REF _Ref68697 \h Table 3 6, for all read command). But there is NO Block Read if Cache Line size is set to 1 or it is set to unsupported value (valid Cache Line sizes are multiples of 4 - see chapter 4.1.2).
3.4 Transaction Ordering
In order to satisfy PCI transaction ordering XE "transaction ordering" rules, the following functionality is implemented:
When the WISHBONE slave unit receives a Read request and no other Delayed Read XE "read cycles:delayed reads" request is pending or waiting to be retried by the WISHBONE master, it latches address and byte enable information and terminates the cycle with Retry XE "termination signals:retry" .
After receiving a Read request, the WISHBONE slave unit locks out any non-configuration space access. (All requests to the WISHBONE slave unit are terminated with Retry XE "termination signals:retry" .)
Posted Write XE "write cycles:posted writes" cycles from WBW_FIFO are processed until WBW_FIFO is empty.
The PCI master module completes a Read cycle on the PCI bus.
When a Read cycle is complete (e.g. when it becomes a Delayed Read XE "read cycles:delayed reads" completion), Posted Write XE "write cycles:posted writes" cycles are accepted again in WBW_FIFO.
The PCI target module retries all non-configuration space accesses from the PCI bus.
All Posted Write XE "write cycles:posted writes" cycles from PCIW_FIFO are completed on the WISHBONE bus until PCIW_FIFO is empty.
The WISHBONE slave unit allows a Read cycle to be completed on the WISHBONE bus.
If the Read cycle not complete, WISHBONE slave and PCI target unit allow the posting of Write cycles. XE "operation:transaction ordering" \r "TransactionOrdering" XE "transaction ordering" \r "TransactionOrdering"
3.5 Parity
Parity monitoring and generation is required by all PCI agents according to the PCI Local Bus Specification. The PCI master module monitors a PAR signal during Read cycles and drives it during Write cycles. The PAR signal provides even parity through C/BE# [3:0] and AD [31:0] lines during address and data phase. If the PCI master performs a Write cycle, the target is responsible for monitoring PAR and asserting PERR# if an error is detected. During Read cycles, the PCI master module monitors PAR and asserts PERR# if an error is detected. If a master detects a parity error during a Read transaction or samples the PERR# signal asserted during a Write transaction, it must set the parity error detected bit in its configuration space Status register.
If the parity error response bit is set, the PCI master module must signal a parity error by asserting the PERR# signal during Read transactions.
When the PERR_INT_EN bit is set, the core signals an interrupt request in an additional response to parity errors, as recommended by the PCI Bus Specification. Parity error detection has no influence on the PCI master moduleit continues the transaction until finished or until terminated by the target. XE "operation:parity" \r "Parity" XE "parity" \r "Parity"
3.6 Interrupts
The PCI IP core is capable of generating interrupts in response to different events. Interrupt Control and Interrupt Status registers control these interrupts. If the core is implemented as a guest bridge, interrupts are reported on the PCI bus through assertion of the INTA# pin; if it is implemented as a host, they are reported on the WISHBONE bus through assertion of the INTA_O pin. The Interrupt Control register is used for enabling/disabling interrupts originating from different sources. The interrupt Status register is used to determine the source of an interrupt and to clear interrupt requests. See chapter 4.1.4 what must be enabled to cause appropriate interrupts and which are implemented.
The software must locate and clear the source of an interrupt request before clearing status bits in a bridge core. When a reported error caused an interrupt, error must be cleared before interrupt. XE "operation:interrupts" \r "Interrupts" XE "interrupts, generating and reporting" \r "Interrupts"
Registers
This section describes all Control and Status registers inside the PCI core, also called configuration space. It consists of the PCI Configuration Space Header (Type 00h) and device specific Configuration Space registers. The Width field specifies the number of bits in the register, Access specifies the valid access types, R/W stands for Read and Write access, and R for Read Only access.
4.1 Register List and Description
NameAddressWidthAccessDescriptionPCI Configuration Space0x000 0x0FFPCI Specification Rev. 2.2 configuration spaceP_IMG_CTRL0*0x10032R/WPCI Image0 Control registerP_BA0*0x010 and 0x10432R/WPCI Image0 Base Address registerP_AM0*0x10832R/WPCI Image0 Address Mask registerP_TA0*0x10C32R/WPCI Image0 Translation Address registerP_IMG_CTRL10x11032R/WPCI Image1 Control registerP_BA10x014 and 0x11432R/WPCI Image1 Base Address registerP_AM10x11832R/WPCI Image1 Address Mask registerP_TA10x11C32R/WPCI Image1 Translation Address registerP_IMG_CTRL20x12032R/WPCI Image2 Control registerP_BA20x018 and 0x12432R/WPCI Image2 Base Address registerP_AM20x12832R/WPCI Image2 Address Mask registerP_TA20x12C32R/WPCI Image2 Translation Address registerP_IMG_CTRL30x13032R/WPCI Image3 Control registerP_BA30x01C and 0x13432R/WPCI Image3 Base Address registerP_AM30x13832R/WPCI Image3 Address Mask registerP_TA30x13C32R/WPCI Image3 Translation Address registerP_IMG_CTRL40x14032R/WPCI Image4 Control registerP_BA40x020 and 0x14432R/WPCI Image4 Base Address registerP_AM40x14832R/WPCI Image4 Address Mask registerP_TA40x14C32R/WPCI Image4 Translation Address registerP_IMG_CTRL50x15032R/WPCI Image5 Control registerP_BA50x024 and 0x15432R/WPCI Image5 Base Address registerP_AM50x15832R/WPCI Image5 Address Mask registerP_TA50x15C32R/WPCI Image5 Translation Address registerP_ERR_CS0x16032R/WPCI Error Control and Status registerP_ERR_ADDR0x16432RPCI Erroneous Address registerP_ERR_DATA0x16832RPCI Erroneous Data registerWB_CONF_SPC_BAR (Base for WISHBONE bus)0x18032RWISHBONE Configuration Space Base AddressW_IMG_CTRL10x18432R/WWISHBONE Image1 Control registerW_BA10x18832R/WWISHBONE Image1 Base Address registerW_AM10x18C32R/WWISHBONE Image1 Address Mask registerW_TA10x19032R/WWISHBONE Image1 Translation Address registerW_IMG_CTRL20x19432R/WWISHBONE Image2 Control registerW_BA20x19832R/WWISHBONE Image2 Base Address registerW_AM20x19C32R/WWISHBONE Image2 Address Mask registerW_TA20x1A032R/WWISHBONE Image2 Translation Address registerW_IMG_CTRL30x1A432R/WWISHBONE Image3 Control registerW_BA30x1A832R/WWISHBONE Image3 Base Address registerW_AM30x1AC32R/WWISHBONE Image3 Address Mask registerW_TA30x1B032R/WWISHBONE Image3 Translation Address registerW_IMG_CTRL40x1B432R/WWISHBONE Image4 Control registerW_BA40x1B832R/WWISHBONE Image4 Base Address registerW_AM40x1BC32R/WWISHBONE Image4 Address Mask registerW_TA40x1C032R/WWISHBONE Image4 Translation Address registerW_IMG_CTRL50x1C432R/WWISHBONE Image5 Control registerW_BA50x1C832R/WWISHBONE Image5 Base Address registerW_AM50x1CC32R/WWISHBONE Image5 Address Mask registerW_TA50x1D032R/WWISHBONE Image5 Translation Address registerW_ERR_CS0x1D432R/WWISHBONE Error Control and Status registerW_ERR_ADDR0x1D832RWISHBONE Erroneous Address registerW_ERR_DATA0x1DC32RWISHBONE Erroneous Data registerCNF_ADDR0x1E032R/WConfiguration Cycle Generation Address registerCNF_DATA0x1E432R/WConfiguration Cycle Generation Data registerINT_ACK0x1E832RInterrupt Acknowledge registerICR0x1EC32R/WInterrupt Control registerISR0x1F032R/WInterrupt Status register* ( All 4 PCI Image0 Control and Address registers are implemented when the PCI bridge is implemented as HOST and all 6 images arePCI Image0 is used to access WB bus or none of all 4 PCI Image0 Control and Address registers are implemented if the PCI bridge is implemented as HOST and PCI Image0 is canceled. Otherwise only the PCI Image0 Base Address register (P_BA0) is implemented on the same offset address and is used for access to the entire Configuration Space (see also REF _Ref528224091 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528224105 \h 3.3.2 Addressing and Images of the PCI Target Unit).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 1: List of registers XE "registers:list of" \r "ListRegisters"
4.1.1 WISHBONE Slave Unit Control & Status
The registers of the WISHBONE slave unit start at offset 0x180 from the base address. The base address is pre-defined during the design phase for WISHBONE bus accesses; the base address for the PCI bus is defined with a configuration cycle for Guest Implementation or with writing to this register by the WISHBONE master for Host Implementation (see also chapter 3.1, Configuration Space).
4.1.1.1 WISHBONE Configuration Space BAR
Bit #AccessResetDescription32R*This register stores the base address to access core registers from the WISHBONE bus. It is read only.* ( Value at reset is defined before implementation in parameter file
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 2: WISHBONE configuration space Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 1: WISHBONE configuration space Base Address register layout
The register is read only. Bits 31 12 define the WISHBONE configuration space base address. Bits 11 0 are always 0 because the minimum image size is 4KB.
4.1.1.2 WISHBONE Image Control and Address Registers
Five configurable WISHBONE slave images can be implemented. Each of these images implements its own set of registers. Image Control and Address registers are the same for all five images.
Image Control registers: W_IMG_CTRL1 - W_IMG_CTRL5
Bit #AccessResetDescription32RW0x00000000The register value controls the WISHBONE slave unit behavior when an image is selected and enabled.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 3: WISHBONE Image Control register
Register layout:
31 240x0023 160x0015 80x007 432100x00AT_ENPREF_ENMRL_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 2: WISHBONE Image Control register layout
Bit descriptions:
Bit #AccessDescription31 3N/ANot used2Address Translation EnableIf this bit is set, address translation for the corresponding image is enabled.1Prefetch enableThis bit marks address space occupied by an image as prefetchable.0Memory Read Line EnableWhen the WISHBONE master performs block read cycles, this bit enables the usage of memory access optimizing commands. If the prefetch-enable bit is also set, read will be performed using Memory Read Multiple command, otherwise the Memory Read Line command will be used.
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 4: WISHBONE Image Control register bit descriptions
Base Address registers: W_BA1- W_BA5
WidthAccessResetDescription32RW0x00000000This register value holds the WISHBONE bus base address of an image.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 5: WISHBONE Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 432100x0000ASMFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 3: WISHBONE Base Address register layout
Bit descriptions:
Bit #AccessDescription31 12Base AddressImage base address. How many bits from this field are compared with ADDR_I(31:0) is defined in the Address Mask register.11-1N/ABecause the minimum block size is 4KB, this field is reserved.0Address Space MappingThis bit defines to which address space an image maps on the PCI bus.
0 Memory space mapping
1 I/O space mappingTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 6: WISHBONE Base Address register bit descriptions
Address Mask registers: W_AM1 W_AM5
WidthAccessResetDescription32RW0x00000000This register value represents an address mask. If the corresponding bit is 1, the address line in the same position is compared with the value in the Base Address register. If the bit is 0, the corresponding address line is not compared with the value in the BA register.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 7: WISHBONE Address Mask register
Register layout:
3130 24IMG_ENAM23 16AM15 1211 8AM0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 4: WISHBONE Address Mask register layout
Bit descriptions:
Bit #AccessDescription31Image Enable & Address Mask (31)This bit must be set to enable an image. If 0, the corresponding image is not enabled. This bit is also used in Address Masking, i.e. how a limit of 2GB per image is implemented (at least ADDR_I(31)) must be compared with BA for each image.30 12Address MaskThe remainder of the Address Mask. If bit(x) of the address mask is 1, ADDR_I(x) is compared with the BA(x) bit in the Base Address register; otherwise it is not. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never compared with the BA register value).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 8: WISHBONE Address Mask register bit descriptions
Translation Address registers: W_TA1 W_TA5
WidthAccessResetDescription32RW0x00000000If address translation is enabled, compared address lines from the WISHBONE bus (specified with AM value) are replaced by corresponding values in this register for PCI bus accesses. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 9: WISHBONE Translation Address register
Register layout:
31 24TA23 16TA15 1211 8TA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 5: WISHBONE Translation Address register layout
Bit descriptions:
Bit #AccessDescription31 12Translation AddressThis register value is used when address translation is enabled. Each value on ADDR_I lines not masked by AM register setting is replaced by the corresponding bit value of the Translation Address register for PCI bus accesses. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never replaced).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 10: WISHBONE Translation Address register bit descriptions XE "registers:WISHBONE slave unit, control & status"
4.1.2 PCI Target Unit Control & Status
Guest bridge implementation always provides R/W access to Configuration space by configuring the Base Address 0 register. Other PCI agents are responsible for this by performing a Type 0 configuration cycle. Host bridge implementation can provide read-only access to Configuration Space or choosecan be set not to do that at all. This way, all six PCI Base Addresses can be used for accessing the WISHBONE address space (see PCI IP Core Design document and chapter A.1, which images are implemented in current design).
Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 6: PCI Configuration Space Header (Header type 00h)
All PCI-compliant devices must support Vendor ID, Device ID, Command, Status, Revision ID, Class Code, and Header Type. The Header Type is type 00h, which defines the header XE "device identification" \t "See configuration space header" XE "identification" \t "See configuration space header" structure of REF _Ref514551570 \* MERGEFORMAT Figure 4 6.
The configuration space header used for device identification includes the following:
Vendor ID XE "configuration space:header:vendor ID" : This field identifies the manufacturer of the device. To ensure uniqueness, the PCI SIG allocates valid vendor identifiers. 0FFFFh is an invalid value for the Vendor ID.
Device ID XE "configuration space:header:device ID" : This field identifies the particular device. It is allocated by the vendor.
Revision ID XE "configuration space:header:revision ID" : This register specifies a device specific revision identifier whose value is chosen by the vendor. An acceptable value is zero. This field should be viewed as a vendor-defined extension to the Device ID.
Header Type XE "configuration space:header:header type" : This byte identifies the layout of the second part of the predefined header (beginning at byte 10h in configuration space) and also whether or not the device contains multiple functions. Bit 7 in this register is used to identify a multi-functional device. If the bit is 0, the device is single-functional. If the bit is 1, it has multiple functions. Bits 6 through 0 identify the layout of the second part of the predefined header.
Class Code XE "configuration space:header:class code" : The Class Code register is read only. It is used to identify the generic function of the device and, in some cases, a specific register-level programming interface (see the PCI 2.2 Specification for detailed description).
The Command register serves device control functions. When 0, the device is logically disconnected from the bus (except for configuration accesses). The following table shows bit descriptions.
Bit #ImplementedDescription15 10Reserved9NOFast Back-to-Back Enable. This optional Read/Write bit controls whether or not a master can do fast back-to-back transactions to different devices. A value of 1 indicates that the master is allowed to generate fast back-to-back transactions to different agents. A value of 0 means that fast back-to-back transactions are allowed only to the same agent. The state after RST# is 0.8 " S E R R # e n a b l e . A v a l u e o f 0 d i s a b l e s t h e S E R R # d r i v e r , a v a l u e o f 1 e n a b l e s i t . T h e s t a t e o f t h i s b i t a f t e r R S T # i s 0 . A d d r e s s p a r i t y e r r o r s a r e r e p o r t e d o n l y i f t h i s b i t a n d b i t 6 a r e 1 . 7 N O S t e p p i n g c o n t r o l . T h i s b i t i s u s e d t o c o n t r o l w h e t h e r o r n o t a d e v i c e d o e s a d d r e s s / d a t a s t e p p i n g . D e v i c e s t h a t n e v e r d o s t e p p i n g m u s t h a r d w i r e t h i s b i t t o 0 . 6 " P a r i t y E r r o r R e s p o n s e . T h i s b i t c o n t r o l s t h e d e v i c e s r e s p o n s e t o p a r i t y e r r o r s . I f s e t , t h e d e v i c e m u s t t a k e i t s n o r m a l a c t i o n w h e n a p a r i t y e r r o r i s d e t ected. If the bit is 0, the device sets its detected parity error status bit (bit 15 in the Status register) when an error is detected but does not assert PERR# and continues normal operation. The state after RST# is 0. 5NOVGA Palette Snoop. This bit controls how VGA compatible devices and graphics devices handle access to the VGA Palette registers. When this bit is 1, palette snooping is enabled (i.e. the device does not respond to Palette Register Write cycles and snoops the data). 4NOMemory Write and Invalidate. This is an enable bit for using the Memory Write and Invalidate command. When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead. The state after RST# is 0.3NOSpecial cycles. Controls a devices action on Special Cycle operations. A value of 0 causes the device to ignore all Special Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. The state after RST# is 0.2 " B u s m a s t e r . T h i s b i t c o n t r o l s t h e d e v i c e s a b i l i t y t o a c t a s a m a s t e r o n t h e P C I b u s . A v a l u e o f 0 d i s a b l e s t h e d e v i c e f r o m g e n e r a t i n g P C I a c c e s s e s . A v a l u e o f 1 a l l o w s t h e d e v i c e t o b e h a v e a s a b u s m a s t e r . T h e s t a t e a f t e r R S T # i s 0 . 1 " M e m o r y s p a c e . T h i s b i t c o n t r o l s t h e r e s p o n s e t o m e m o r y s p a c e a c c e s s . A v a l u e o f 0 d i s a b l e s t h e d e v i c e r e s p o n s e . A v a l u e o f 1 a l l o w s r e s p o n d i n g t o m e m o r y s p a c e a c c e s s . T h e s t a t e a f t e r R S T # i s 0 . 0 " I / O s p a c e . T h i s b i t c o n t r o l s t h e r e s p o n s e t o I / O s p a c e a c c e s s . A v a l u e o f 0 disables the device response. A value of 1 allows the device to respond to I/O space access. The state after RST# is 0.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 11: Command register of PCI configuration header
The Status register notes the device status. Reserved bits are read only and return 0 after reading. A 1 bit is reset whenever a 1 is written to a corresponding bit location. The following table provides a description of the corresponding bits.
Bit descriptions:
Bit #ImplementedD e s c r i p t i o n 1 5 " D e t e c t e d P a r i t y E r r o r . T h e d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t d e t e c t s a p a r i t y e r r o r , e v e n i f p a r i t y e r r o r h a n d l i n g i s d i s a b l e d ( a s c o n t r o l l e d b y b i t 6 i n t h e C o m m a n d r e g i s t e r ) . 1 4 " S i g n a l e d S y s t e m E r r o r X E " t e r m i n a t i o n s i g n a l s : s y s t e m e r r o r " . T h i s b i t m u s t b e s e t w h e n e v e r t h e d e v i c e a s s e r t s S E R R # . 1 3 " R e c e i v e d M a s t e r A b o r t X E " t e r m i n a t i o n s i g n a l s : m a s t e r a b o r t " . A m a s t e r d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t s t r a n s a c t i o n ( e x c e p t f o r s p e c i a l c y c l e s ) i s t e r m i n a t e d w i t h M a s t e r A b o r t X E " t e r m i n a t i o n s i g n a l s : m a s t e r a b o r t " . A l l m a s t e r d e v i c e s m u s t i m p l e m e n t t h i s b i t . 1 2 " R e c e i v e d T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . A m a s t e r d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t s t r a n s a c t i o n i s t e r m i n a t e d w i t h T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . 1 1 " S i g n a l e d T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . A t a r g e t d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t t e r m i n a t e s a t r a n s a c t i o n w i t h T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . 1 0 9 " D E V S E L t i m i n g : 0 0 f a s t ; 0 1 m e d i u m ; 1 0 s l o w . T h e s e b i t s a r e r e a d - o n l y a n d m u s t i n d i c a t e t h e s l o w e s t t i m e t h a t a d e v i c e n e e d s t o a s s e r t D E V S E L # f o r a n y b u s c o m m a n d , e x c e p t C o n f i g u r a t i o n R e a d a n d C o n f i g u r a t i o n W r i t e . 8 " M a s t e r D a t a P a r i t y E r r o r . T h i s b i t i s i m p lemented by bus masters only. It is set when three conditions are met: 1) The bus agent asserted PERR# itself (on a Read cycle) or observed PERR# asserted (on a Write cycle). 2) The agent setting the bit acted as the bus master for the operation during which the error occurred. 3) The parity error response bit (Command register) is set.7 " F a s t B a c k - t o - B a c k C a p a b l e . T h i s o p t i o n a l r e a d o n l y b i t i n d i c a t e s w h e t h e r o r n o t t h e t a r g e t i s c a p a b l e o f a c c e p t i n g f a s t b a c k - t o - b a c k t r a n s a c t i o n s w h e n t h e t r a n s a c t i o n s d o n o t r e f e r t o t h e s a m e a g e n t . 6 R e s e r v e d 5 " 6 6 M H z c a p a b l e . T h i s o p t i o n a l r e a d only bit indicates whether or not this device is capable of running at 66 MHz. A value of 1 indicates that the device is 66 MHz capable.4NOList of compatibilities. A value of zero indicates that no new capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in configuration space to a linked list of new capabilities.3 0-ReservedTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 12: Status register of PCI configuration header
The following descriptions include only miscellaneous (device independent), already implemented registers:
The Cache Line Size register specifies the size of burst reads, except for a Memory Read Multiple command, which size is Read_FIFO depth. Valid values for this register are multiples of 4 (including 1). In invalid value is written (including 0), then the value of 1 is assumed by both WBU and PCIU and no burst reads are performed.
The Latency Timer register specifies the timer value in units of PCI bus clocks. After RST#, the register value is 0.
The Interrupt Line register tells to which input of the system interrupt controller(s) the devices interrupt pin is connected (the Design Document describes in detail how it is implemented).
The Interrupt Pin register tells which interrupt pin the device uses. A value of 1 corresponds to INTA# and so on. The values from 05h to FFh are reserved.
There are 6 Base Address registers, in Configuration space Header. This registers are the same and also accessed in the PCI part of the Configuration space. and eEach one of them consists of a 28-bit base address for MEMORY mapping or a 30-bit base address for I/O mapping. Here are only up to 20 MSBits implemented. Other bits are control bits and described in the following table.
Bit descriptions:
Bit #Description31 4Base address (only the upper 20 bits are valid)3Prefetchable2 1Type: 00 32-bit address space; 01 reserved; 10 64-bit address space; 11 reserved0Memory space indicator = 0 (always for MEMORY mapped space)!!!Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 13: Base Address register of PCI configuration header for memory mapped space
Bit descriptions:
Bit #Description31 2Base address (only the upper 20 bits are valid)1Reserved0I/O space indicator = 1 (always for I/O mapped space)Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 14: Base Address register of PCI configuration header for I/O mapped space
XE "PCI target unit:configuration space header" \r "ConfigurationSpaceHeader" XE "registers:PCI target unit, configuration space header" \r "ConfigurationSpaceHeader" XE "configuration space:header:registers" \r "ConfigurationSpaceHeaderRegisters"
4.1.2.2 PCI Image Control and Address Registers
There are six possible configurable PCI target images. Each of these images implements its own set of registers.
The only exception is the set of 4 PCI Image0 Control and Address registers, which is implemented only when the PCI bridge is implemented as HOST and all 6 imagesImage0 is used to access WB bus are used (see REF _Ref527975562 \h Table 4 16, REF _Ref527975503 \h Table 4 18, REF _Ref527975513 \h Table 4 20 and REF _Ref527975518 \h Table 4 22). Otherwise, there are five possible configurable PCI target images (PCI image1 PCI image5), and only the PCI Image0 Base Address register (P_BA0) is implemented for the PCI image0 on the same offset address and is used for access to the entire Configuration Space (see REF _Ref527976313 \h Table 4 15 and REF _Ref527976348 \h Figure 4 7). The other 3 registers are not implemented and therefore cannot be written to (see also REF _Ref528224163 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528224176 \h 3.3.2 Addressing and Images of the PCI Target Unit).
Base Address Registers: P_BA0
WidthAccessResetDescription32RW0x00000000This register stores the base address for accessing core registers from the PCI bus.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 15: PCI Image0 Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 7: PCI Image0 Base Address register layout Image0 used for accessing the PCI Configuration Space Header (type 00h)
Image Control registers: P_IMG_CTRL0 (P_IMG_CTRL1) P_IMG_CTRL5
WidthAccessResetDescription32RW0x00000000The register value controls the PCI target unit behavior when an image is selected and enabled.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 16: PCI Image Control Register
Register layout:
31 240x0023 160x0015 80x007 432100x00AT_ENPREF_EN0Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 8: PCI Image Control register layout
Bit descriptions:
Bit #NameDescription31 3N/ANot used2Address Translation EnableIf this bit is set, address translation for the corresponding image is enabled.1Pre-fetch enableThis bit marks address space occupied by an image as prefetchable.0N/ANot usedTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 17: PCI Image Control Register bit descriptions
Base Address Registers: P_BA0 (P_BA1) - P_BA5
WidthAccessResetDescription32RW0x00000000The register value holds the PCI bus base address of an image.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 18: PCI Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 432100x0000ASMFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 9: PCI Base Address Register Layout
Bit descriptions:
Bit #NameDescription31 12Base AddressImage base address. The Address Mask register defines how many bits from this field are compared with ADDR_I(31:0).11-1N/ABecause the minimum block size is 4KB, this field is reserved.0Address Space MappingThis bit defines to which address space an image maps on the PCI bus.
Predefined value can be changed later for HOST bridges.
Predefined value can NOT be changed for GUEST bridges (see chapter 3.3.2 Addressing and Images of the PCI Target Unit).
0 Memory space mapping
1 I/O space mappingTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 19: PCI Base Address register bit descriptions
Address Mask registers: P_AM0 (P_AM1) P_AM5
WidthAccessResetDescription32RW0x00000000The register value represents the address mask. If the corresponding bit is 1, the address line in the same position is compared with a value in the Base Address register. If the bit is 0, the corresponding address line is not compared with a value in the BA register.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 20: PCI Address Mask register
Register layout:
3130 24IMG_ENAM23 16AM15 1211 8AM0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 10: PCI Address Mask register layout
Bit descriptions:
Bit #NameDescription31Image Enable & Address Mask(31)This bit must be set for an image to be enabled. If the bit is 0, the corresponding image is not enabled. This bit is also used in Address Masking, i.e. how a limit of 2GB per image is implemented (at least ADDR_I(31) must be compared with BA for each image).30 12Address MaskThis is the remainder of the Address Mask. If bit(x) of the address mask is 1, then ADDR_I(x) is compared with the BA(x) bit in the Base Address Register; otherwise it is not.11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never compared with the BA register value).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 21: PCI Address Mask register bit descriptions
Translation Address registers: P_TA0 (P_TA1) P_TA5
WidthAccessResetDescription32RW0x00000000If address translation is enabled, compared address lines from the PCI bus (specified with AM value) are replaced by corresponding values in this register for WISHBONE bus accesses. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 22: PCI Translation Address register
Register layout:
31 24TA23 16TA15 1211 8TA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 11: PCI Translation Address register layout
Bits descriptions:
Bit #NameDescription31 12Translation AddressThis register value is used when address translation is enabled. Each value on ADDR_I lines that is not masked by AM register setting is replaced. by the corresponding bit value of the Translation Address register for WISHBONE bus accesses. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never replaced).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 23: PCI Translation Address register bit descriptions XE "registers:PCI target unit, control & status"
4.1.3 Reporting Registers
Error Reporting registers are provided because of Posted Write XE "write cycles:posted writes" cycles, which are always acknowledged on the WISHBONE bus before they actually complete on the PCI bus, and vice-versa, so errors detected on PCI or WISHBONE buses cannot be reported back to WISHBONE master or PCI initiator using the standard bus protocol.
4.1.3.1 WISHBONE Slave Unit Error Reporting Registers
WISHBONE Error Control and Status register: W_ERR_CS
WidthAccessResetDescription32RW0x00000000Part of this register is used for controlling the Error Reporting mechanism, another part for reporting statuses and additional information about an error that occurred during the completion of a Posted Write cycle on the PCI bus. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 24: WISHBONE Error Control and Status register
Register layout:
31 2827 24BEBC23 160x0015 121110980x00RTY_EXPESERR_SIG7 432100x0000ERR_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 12: WISHBONE Error Control and Status register layout
Bit descriptions:
Bit #NameDescription31 28Byte EnablesThe field value reports the state of BE# signals used in the Posted Write cycle that terminated with an error.27-24Bus CommandThis field value reports a bus command used for the Posted Write cycle that terminated with an error.16 11N/ANot used10Retry XE "termination signals:retry" Counter ExpiredTHIS BIT IS RESERVED FOR FUTURE USE! Its function is to report that a Posted Write cycle has been retried MAX_RETRY times.9Error XE "termination signals:error" SourceThe ES bit indicates that the master terminated the transaction with Master Abort XE "termination signals:master abort" . Software can distinguish between two kinds of Master Abort XE "termination signals:master abort" terminations the PCI module performs: If the RTY_EXP bit is cleared, Master Abort XE "termination signals:master abort" was performed because no target claimed the transaction; if the RTY_EXP is set, the target signaled too many Retry XE "termination signals:retry" terminations. See description of bit 10!
A cleared ES bit indicates that the target of the transaction signaled Target Abort XE "termination signals:target abort" .8Error XE "termination signals:error" SignaledIf set, this bit indicates that an error has been reported. While this bit is set, all WISHBONE slave unit operation is frozen. Software must clear this bit to enable transactions to resume their path through the WISHBONE slave unit. A bit is cleared by writing 1 to its location.7-1N/ANot used0Error XE "termination signals:error" EnableSetting this bit enables the Error Reporting mechanism. Clearing this bit means that Error Reporting is not performedthe transaction that caused an error is discarded, other transactions continue normally.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 25: WISHBONE Error Control and Status register bit descriptions
WISHBONE Erroneous Address Register: W_ERR_ADDR
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores the address of the transaction on the PCI bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 26: WISHBONE Erroneous Address register
WISHBONE Erroneous Data: W_ERR_DATA
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores data of the transaction on the PCI bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 27: WISHBONE Erroneous Data register XE "WISHBONE:slave unit:error reporting registers" \r "ErrorReportingRegistersWISHBONE"
4.1.3.2 PCI Target Unit Error Reporting Registers
PCI Error Control and Status register: P_ERR_CS
WidthAccessResetDescription32RW0x00000000Part of this register is used for controlling the Error Reporting mechanism, another part for reporting statuses and additional information about an error that occurred during the completion of a Posted Write cycle on the WISHBONE bus. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 28: PCI Error Control and Status register
Register layout:
31 2827 24BEBC23 160x0015 121110980x00RTY_EXPESERR_SIG7 432100x0000ERR_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 13: PCI Error Control and Status register layout
Bit descriptions:
Bit #NameDescription31 28Byte EnablesThis field value reports the state of byte enable signals SEL_O(3:0) used in the Posted Write cycle that terminated with an error on the WB bus.27-24Bus CommandThis field value reports a bus command from the PCI bus used for a Posted Write cycle that terminated with an error on the WB bus.16 11N/ANot used10Retry XE "termination signals:retry" Counter ExpiredThis bit reports that a Posted Write cycle has been retried MAX_RETRY times or that there was no response on the WISHBONE bus for MAX_RETRY times (internal Retry XE "termination signals:retry" is generated if the WISHBONE slave does not respond for 8 cycles).9Error XE "termination signals:error" SourceThe ES bit indicates that the WISHBONE Master Module of the PCI Target Unit stopped (terminated) the write transaction. The WISHBONE slave signaled too many Retry XE "termination signals:retry" terminations. In this case, the RTY_EXP bit is also set.
A cleared ES bit indicates that the WISHBONE Master Module of the PCI Target Unit was not able to continue the write transaction because of the WISHBONE slave: If the RTY_EXP bit is cleared, the WISHBONE slave signaled an Error XE "termination signals:error" termination; if the RTY_EXP bit is set, the WISHBONE slave did not respond to the initiated transaction.8Error XE "termination signals:error" SignaledIf set, this bit indicates that an error has been reported. The bit is cleared by writing 1 to its location.7-1N/ANot used0Error XE "termination signals:error" EnableSetting this bit enables the Error Reporting mechanism. Clearing this bit means that Error Reporting will not be performed the transaction that caused an error is discarded, other transactions continue normally.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 29: PCI Error XE "termination signals:error" Control and Status register Bit Descriptions
PCI Erroneous Address Register: P _ERR_ADDR
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores the address of the transaction on the WISHBONE bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 30: PCI Erroneous Address register
PCI Erroneous Data: P_ERR_DATA
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores data of the transaction on the WISHBONE bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 31: PCI Erroneous Data Register XE "PCI target unit:error reporting registers" \r "ErrorReportingRegistersPCI"
4.1.3.3 Configuration Cycle Generation Registers
Two registers are provided for generating configuration cycles on the PCI bus. The WISHBONE master initiates a configuration cycle in two steps:
It writes the appropriate value in the CNF_ADDR register and
Reads cycles from or writes cycles to the CNF_DATA register to generate a Configuration Read or Write cycle respectively.
Configuration address: CNF_ADDR
WidthAccessResetDescription32RW0x00000000This register stores all information needed to drive address lines during the Address phase of a configuration cycle (e.g. it is used within a host PCI device).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 32: Configuration Address register
Register layout:
31 24Reserved23 16BUS NUMBER15 1110 8DEVICEFUNCTION7 210OFFSET0TYPEFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 14: Configuration Address register layout
Bit descriptions:
Bit #NameDescription31 24N/AA value in this field is ignored for any kind and type of configuration cycle.23 16Bus numberThis field holds a bus number on which a target of the configuration space access resides. It is only used in Type 1 configuration cycles (TYPE bit = 1).15 11Device numberThe value in this field represents a device number. This field is driven directly to AD(15:11) lines during the Address phase for Type1 (TYPE = 1) configuration cycle and is decoded for Type0 configuration cycles (See Table XY for Device number decoding). 10 8Function numberThe value in this field is a function number for multifunctional devices.7 2Register numberThis field holds the register offset for a device addressed with configuration cycle.1N/ANot usedalways 00TypeType of configuration cycle
(0 Type 0, 1 Type 1)Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 33: Configuration Address register bit descriptions
A Read cycle from or a Write cycle to this register will perform a configuration cycle on the PCI bus using information written to the CNF_ADDR register.
Configuration data: CNF_DATA
WidthAccessResetDescription32RW0x00000000This register stores Read or Write data for configuration cycles.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 34: Configuration Data Register XE "configuration cycles:registers" \r "ConfigurationCyclesRegisters"
4.1.3.4 Interrupt Acknowledge Cycle Generation Register
A Read cycle from the INT_ACK register generates an Interrupt Acknowledge cycle XE "interrupt acknowledge cycles:register" on the PCI bus.
WidthAccessResetDescription32R0x00000000This register stores interrupt vector data returned during an Interrupt Acknowledge cycle.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 35: Interrupt Acknowledge register XE "registers:reporting"
4.1.4 Interrupt Control & Status Registers
Interrupt Control register: ICR
WidthAccessResetDescription32RW0x00000000This register is used to enable/disable the generation of interrupt requests from various sources.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 36: Interrupt Control register
Register layout:
313210SW_RST0000x0023 160x0015 80x007 5432100x0SERR_
INT_ENPERR_
INT_ENPCI_
EINT_ENWB_
EINT_ENINT_
PROP_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 15: Interrupt Control register layout
Bit descriptions:
Bit #NameDescription0Interrupt Propagation EnableFor Guest bridge implementation this bit indicates that INT_I line assertion on the WISHBONE bus will generate an interrupt request on the PCI bus through an assertion of the INTA# pin.
For Host bridge implementation this bit indicates that an assertion of the INTA# pin on the PCI bus will generate an interrupt request on the WISHBONE bus through an assertion of the INT_O pin.1WISHBONE Error Interrupt EnableIf set, this bit enables interrupt request generation when an error is signaledREPORTED during the execution of Posted Write cycles through the WISHBONE slave unit. A cleared bit disables these interrupts but does not disable Error Reporting (see bits 0 and 8 of WB Error Control and Status register W_ERR_CS).**2PCI Error Interrupt EnableIf set, this bit enables interrupt request generation when an error is signaledREPORTED during the execution of Posted Write cycles through the PCI target unit. A cleared bit disables these interrupts but does not disable Error Reporting (see bits 0 and 8 of PCI Error Control and Status register P_ERR_CS).**3Parity Error Interrupt enableThis bit enables/disables the generation of interrupt requests when a parity error is detected by the PCI master module. This interrupt is meaningful on Host Bridge Implementation only.*4System Error Interrupt EnableThis bit enables/disables the generation of interrupt requests when a system error (address parity error) is detected by the PCI master module.
This interrupt is decisive on Host Bridge Implementation only.*31Software ResetSetting this bit causes software initiated reset. Host bridge implementation uses this bit to reset the PCI bus, Guest implementation uses it to reset the WISHBONE bus. * Interrupt triggering upon PERR# and SERR# detection for Guest Implementation has no meaning because Guest Implementation triggers interrupts on the PCI bus. An agent that is responsible for routing interrupts to a host processor may trigger an interrupt when one of these errors is detected.
** For reporting Error Interrupt, appropriate Error Reporting Enable bit must be SET (bit 0 of P_ERR_CS and W_ERR_CS registers) besides Error Interrupt Enable bit (see also chapters 4.1.3.1 and 4.1.3.2).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 37: Interrupt Control Register bit descriptions
Interrupt Status Register: ISR
WidthAccessResetDescription32RW0x00000000This register is used to enable/disable the generation of interrupt requests from various sources.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 38: Interrupt Status register
Register layout:
31 240x0023 160x0015 80x007 5432100x0SERR_INTPERR_INTPCI_EINTWB_EINTINTFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 16: Interrupt Status register layout
Bit descriptions:
Bit #NameDescription0Interrupt For Guest bridge implementation this bit indicates that an INT_I input on the WISHBONE bus has been asserted and propagated to the INTA# pin on the PCI bus. This is to say that some device on the WISHBONE bus generated an interrupt request to the host processor.
For Host Bridge Implementation this bit indicates that the INTA# pin on the PCI bus has been asserted and propagated to the INT_O pin on the WISHBONE bus. This means that some device residing on the PCI bus generated an interrupt request to the host processor.1WISHBONE Error InterruptIf set, this bit indicates an interrupt request from the Error Reporting mechanism, which detected an error during the execution of a Posted Write cycle through the WISHBONE slave unit. Only reported error causes this interrupt.**2PCI Error InterruptIf set, this bit indicates an interrupt request from the Error Reporting mechanism, which detected an error during the execution of a Posted Write cycle through the PCI target unit. Only reported error causes this interrupt.**3Parity Error InterruptThis bit indicates that an interrupt request has been generated due to a Parity Error on the PCI bus.
This interrupt has meaning only on Host Bridge Implementation.*4System Error Interrupt EnableThis bit indicates that an interrupt request has been generated due to System Error (Address Parity) on the PCI bus. This interrupt has meaning only on Host Bridge Implementation.** Interrupt triggering upon PERR# and SERR# detection for Guest Implementation has no meaning because Guest Implementation triggers interrupts on the PCI bus. In Guest Implementation, these two bits will never be set.
** For reporting Error Interrupt, appropriate Error Reporting Enable bit must be SET (bit 0 of P_ERR_CS and W_ERR_CS registers) besides Error Interrupt Enable bit (see also chapters 4.1.3.1 and 4.1.3.2).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 39: Interrupt Status register bit descriptions
4.2 Software obligations
If bridge is implemented as GUEST, software (running on a PCI host device) should during initialization phase first set the registers in the PCI Configuration Space Header with configuration cycles (PCI Base Addresses must be mapped without interleaving and not used images must be disabled and finally PCI Master and Target Memory and/or IO spaces must be enabled). Other control and status registers and WBU registers can now be set through Image0 with memory cycles.
If bridge is implemented as HOST, software (running on a WB host device) should during initialization phase first set the PCI and WB Image registers and other status and control registers (PCI and WB Base Addresses must be mapped without interleaving and not used images must be disabled and finally PCI Master and Target Memory and/or IO spaces must be enabled).
When system is running, software MUST NOT just change any Image related registers, but must first disable appropriate Unit (WBU or PCIU or both), otherwise no one can determine what transactions were processed and where (e.g. if Translation Address is changed when the opposite side is writing through that Image).
If bridge is implemented as HOST, WB device can always access Configuration space and change WB Image related registers, since WB device is accessing Configuration space. Before changing the PCI Image relate registers, WB device must first disable PCI Target Memory and IO spaces.
If bridge is implemented as GUEST, PCI host device can always access Configuration space and change PCI Image related registers, since PCI device is accessing Configuration space. Care must be taken, if PCI host device wont to change PCI Base Address 0 (through which it is accessing Configuration space). This must be done with PCI configuration cycles. Before changing the WB Image relate registers, PCI host device must first disable PCI Master operation.
XE "registers:interrupt, control & status"
IO Ports
5.1 PCI Interface
The PCI interface contains both required and optional pins. All of them are organized in functional groups. Required pins must be implemented but there is also a description of implemented optional pins (needed for requested features).
5.1.1 Required PCI Interface Pins
PortWidthDirectionDescriptionAD32I/OMultiplexed address and data bus (little endian)C/BE#4I/OMultiplexed command and byte enable bus (This bus indicates a PCI command during address phases and Byte Enables during data phases.)PAR1I/OParity bitTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 1: PCI address and data pins XE "IO ports:PCI interface:address and data pins"
PortWidthDirectionDescriptionFRAME#1I/OStart and end of a transactionIRDY#1I/OInitiator ready (The assertion of this signal indicates that the initiator is ready to send or receive data.)DEVSEL#1I/ODevice selected (When a target recognizes its address on the bus it asserts this signal to claim the transaction.)TRDY#1I/OTarget ready (The assertion of this signal indicates that the target is ready to send or receive data.)STOP#1I/OStop (This pin is used by a target to signal various terminating conditions.)IDSEL1IIndividual device select (This signal is used for configuration and requests a unique IDSEL line per agent.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 2: PCI interface control pins XE "IO ports:PCI interface:interface control pins, required"
PortWidthDirectionDescriptionPERR#1I/OParity errorSERR#1I/OSystem errorTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 3: PCI error reporting pins XE "IO ports:PCI interface:error reporting pins"
PortWidthDirectionDescriptionREQ#1OAsserted by initiator to request bus ownershipGNT#1IAsserted by Arbiter to grant bus ownershipTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 4: PCI arbitration pins XE "IO ports:PCI interface:arbitration pins" (INITIATOR only)
PortWidthDirectionDescriptionCLK1IPCI input clock (Signals are sampled on the rising edge of the clock.)RST#1I/OAsynchronous reset (The PCI device must tri-state all signals during reset.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 5: PCI system pins XE "IO ports:PCI interface:system pins" XE "pins:required" \r "PinsRequired"
5.1.2 Implemented Optional PCI Interface Pins
PortWidthDirectionDescriptionINTA#1OAsserted by initiator to request an interrupt.Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 6: PCI interrupt pin XE "IO ports:PCI interface:interrupt pins, optional"
PortWidthDirectionDescriptionM66EN1IMode 66 MHz Enable (This signal indicates to a device whether the bus segment is operating at 66 or 33 MHz.)CLKRUN#1I/O/ZClock running (This is the central resource request permission to stop or slow down CLK. The central resource must provide the pull-up for CLKRUN#.).PME#1OPower Management Event (This signal can be used by a device to request a change in the device or system power state. The assertion and deassertion of PME# is asynchronous to CLK.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 7: PCI interface control pins XE "IO ports:PCI interface:interface control pins, optional" XE "pins:optional" \r "PinsOptional"
5.2 WISHBONE Interface
The SoC interface is a WISHBONE Rev. B compliant interface. The WISHBONE slave unit of the PCI IP core is connected to the WISHBONE bus as a slave while the PCI target unit connects to the WISHBONE bus as a master.
PortWidthDirectionDescriptionADDR_O32OAddress outputMDATA_I32IData inputMDATA_O32OData outputSEL_O4OWE_O asserted indicates valid bytes on the MDATA_O bus
WE_O deasserted indicates which bytes must be supplied by slave on MDATA_I busWE_O1OWrite enable indicates a Write cycle when asserted high and a Read cycle when lowCYC_O1OEncapsulates a valid transfer cycleSTB_O1OIndicates a valid transfer to the slaveACK_I1IAcknowledgment input slave signals a normal cycle terminationERR_I1ISlave signals abnormal cycle terminationRTY_I1ISlave signals that the interface is not ready and that the master should retry the operationCAB_O1OIndicates to the slave that consecutive address block transfer is in progressTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 8: PCI target units XE "IO ports:WISHBONE interface: PCI target unit" WISHBONE interface (master)
PortWidthDirectionDescriptionADDR_I32IAddress inputSDATA_I32IData inputSDATA_O32OData outputSEL_I4IWE_O asserted indicates valid bytes on MDATA_I bus
WE_O deasserted indicates which bytes must be supplied on MDATA_O bus.WE_I1IWrite enable indicates a Write cycle when asserted high and a Read cycle when asserted lowCYC_I1IEncapsulates a valid transfer cycleSTB_I1IIndicates a valid transfer to the slaveACK_O1OAcknowledgment output slave signals a normal cycle terminationERR_O1OSlave signals abnormal cycle terminationRTY_O1OSlave signals that the interface is not ready and that the master should retry the operationCAB_I1IMaster signals consecutive address block transfer, which is in progress when 1Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 9: WISHBONE slave units XE "IO ports:WISHBONE interface:WISHBONE slave unit" WISHBONE interface (slave)
PortWidthDirectionDescriptionCLK_I1IClock input (application side clock)RST_I1IReset input (application side reset)RST_O1OUsed for propagating RST# from PCI bus to application side of the bridge; also used for initiating software resetINTA_O(*)1OInterrupt outputINTA_I(*)1IInterrupt input(*) These two signals will never be used at the same time. Guest Implementation of the core will signal interrupts to the PCI bus, so only INTA_I is used. Host Bridge Implementation will signal interrupts to the WISHBONE bus, so INTA_O is used.
Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 10: WISHBONE common control and system I/Os XE "IO ports:WISHBONE interface:common control and system I/Os"
Waveforms
6.1 Wishbone Slave Unit
This section describes basic waveforms of various accesses to the cores configuration space and mapped PCI address space. Waveforms supplied have only informational purpose at this time.
6.1.1 WISHBONE Configuration Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 1: WISHBONE XE "waveforms:WISHBONE slave unit:configuration read cycle" configuration Read cycle
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 2: WISHBONE Configuration Write cycle XE "configuration write cycles" XE "waveforms:WISHBONE slave unit:configuration write cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 3: WISHBONE configuration RMW XE "write cycles:read modify writes (RMW)" cycle XE "waveforms:WISHBONE slave unit:configuration read modify write cycle"
Wishbone masters will most commonly use Single Read XE "read cycles:single reads" cycles for accessing the cores configuration space as shown in REF _Ref513875698 \* MERGEFORMAT Figure 6 1. A Write cycle to the cores register space by the WISHBONE master is shown in REF _Ref513874421 \* MERGEFORMAT Figure 6 2. Writes to unimplemented configuration space have no effect while Read cycles return all 0s. RMW cycles to the cores configuration space are also accepted, as shown in REF _Ref513876813 \* MERGEFORMAT Figure 6 3, and are most commonly used for interrupt handling since a RMW cycle is defined as atomic (indivisible) operation in the WISHBONE Bus Specification. XE "configuration cycles:WISHBONE, waveforms" \r "ConfigurationCyclesWISHBONE"
6.1.2 WISHBONE to PCI Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 4: WISHBONE access to PCI address space XE "waveforms:WISHBONE slave unit:access to PCI address space"
REF _Ref513878541 \* MERGEFORMAT Figure 6 4 shows how the WISHBONE master perceives cycles intended for PCI address space traveling through the WISHBONE slave unit of the core. The first cycle in the figure initiated by the WISHBONE master is a Block Write XE "write cycles:block writes" cycle. The WISHBONE slave module accepts Write cycles until WBW_FIFO is full. Subsequent Write cycles in this block cycle are terminated with Retry XE "termination signals:retry" (RTY_O asserted on ADDRn, DATAn, SELn transfer). The second cycle in the figure is a Read cycle. Read cycles from PCI address space are retried immediately (RTY_O asserted on first ADDR_Del, SEL_Del transfer). Address, byte enable, and CAB_I information is latched by the WISHBONE slave unit on the first rising edge of CLK_I where STB_I is asserted. The third cycle is a Write cycle to the PCI address space and is retried, too. In this case, the WISHBONE slave unit signals a Retry XE "termination signals:retry" if one of the following possibilities occurs:
WBW_FIFO is still full from previous transfers.
A delayed Read XE "read cycles:delayed reads" cycle latched in a previous transfer has not completed on the PCI bus yet.
A Delayed Read XE "read cycles:delayed reads" completion is present in the PCI target unit and has been completed on the PCI bus yet.
In the 4th cycle, the WISHBONE master retries a Read request initiated and latched by the WISHBONE slave module in the 2nd cycle. Since the PCI master module has already performed a Read cycle on the PCI bus and stored data in WBR_FIFO, the WISHBONE slave module takes data from the FIFO and delivers it on the WISHBONE bus. The WISHBONE slave module can supply data for the master as long as WBR_FIFO contains any data and Read addresses are serial and DWORD aligned.
6.1.3 PCI Cycles
The WISHBONE slave unit incorporates a PCI master module that is capable of initiating various types of PCI address space accesses.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 5: PCI Single Read XE "read cycles:single reads" cycle XE "waveforms:WISHBONE slave unit:single read cycle, PCI"
REF _Ref513881598 \* MERGEFORMAT Figure 6 5 shows a Single Read XE "read cycles:single reads" cycle on the PCI bus performed by the PCI master module. On the first clock edge, the PCI master module samples its GNT# signal asserted and claims the bus cycle by asserting FRAME# on the next rising edge of the clock. The 2nd clock cycle is also an address phase, so address and bus command information is provided on ADDR and C/BE# lines respectively. At the end of an address phase, the master module de-asserts FRAME# and asserts IRDY#, indicating its wish to perform a single data phase only. A device with medium decoding has been assumed for a diagram, so nothing happens on the 3rd rising edge of clock. On the 4th clock, the target device claims access by asserting DEVSEL#. This clock cycle is used as Turnaround cycle (target starting to drive AD lines) inserted by delaying assertion of TRDY#. On the 5th clock, actual data transfer occurs, indicated by TRDY# and IRDY# being asserted at the same time. Immediately afterwards, the master module de-asserts IRDY#, indicating the end of transfer.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 6: PCI Single Write XE "write cycles:single writes" XE "waveforms:WISHBONE slave unit:single writes, PCI"
REF _Ref513885186 \* MERGEFORMAT Figure 6 6 shows a Single Write XE "write cycles:single writes" cycle on the PCI bus performed by the PCI master module. On the first clock edge, the PCI master module samples its GNT# signal asserted and claims the bus cycle by asserting FRAME# on the next rising edge of the clock. The 2nd clock cycle is also an address phase, thus address and bus command information is provided on ADDR and C/BE# lines respectively. At the end of an address phase, the master module de-asserts FRAME# and asserts IRDY#, indicating its wish to perform a single data phase only. By asserting IRDY#, Write data and byte enables must be driven on AD and C/BE# lines respectively. A device with medium decoding has been assumed for a diagram, so nothing happens on the 3rd rising edge of the clock. On the 4th clock, the target device claims access by asserting DEVSEL#. On this clock, actual data transfer occurs also, indicated by TRDY# and IRDY# being asserted at the same time. Immediately afterwards, the master module de-asserts IRDY#, indicating the end of transfer.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 7: PCI Burst Read XE "read cycles:burst reads" Cycle XE "waveforms:WISHBONE slave unit:burst read cycle, PCI"
REF _Ref513886106 \* MERGEFORMAT Figure 6 7 shows how the PCI master module performs Burst Read transactions. The mechanism for claiming the bus is the same as in previous diagrams. The main difference lies with the fact that FRAME# stays asserted till the last data transfer. A medium decode target device is assumed for the diagram that inserts a Turnaround cycle on clock 4. The target also inserts one WS after each data phase. Byte enables do not change during bursts. They are always 0000. The last data phase is phase 3, which is indicated by FRAME# de-asserted and IRDY# asserted at the same clock edge. Immediately after the master module latched data from the bus (clock edge when TRDY# is asserted), it de-asserts IRDY# to indicate an end of the transfer.
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 8: PCI Burst Write XE "write cycles:burst writes" cycle XE "waveforms:WISHBONE slave unit:burst write cycle, PCI"
REF _Ref513887067 \* MERGEFORMAT Figure 6 8 shows PCI Burst Write XE "write cycles:burst writes" cycles performed by the PCI master module. The mechanism for claiming the bus is the same as in the previous diagrams. FRAME# stays asserted till the last data transfer. A medium decode target device is assumed for a diagram that claims access and latches the first data beat on clock 4. The target also inserts one WS after each data phase. The last data phase is phase 3, which is indicated by FRAME# de-asserted and IRDY# asserted at the same clock edge. Immediately after the target latched data from the bus (clock edge when TRDY# is asserted), the master module de-asserts IRDY# to indicate an end of the transfer.
6.1.4 PCI Terminations
6.1.4.1 Master Initiated Terminations
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 9: Master Abort XE "waveforms:WISHBONE slave unit:master abort termination, PCI" XE "termination signals:master abort" termination
The PCI master module terminates the transaction with Master Abort XE "termination signals:master abort" , as shown in REF _Ref513951759 \h \* MERGEFORMAT Figure 6 9. What happens? The master initiates a transaction with the address phase and waits for the target to respond by asserting DEVSEL#. The master is only required to wait for the assertion of DEVSEL# for 4 clocks. If DEVSEL# will not have been asserted by the 4th clock (subtractive decode devices), the master de-asserts FRAME# and must hold IRDY# asserted for an additional clock cycle indicating the end of the transaction.
If Error Reporting is enabled and the transaction is a Posted Write XE "write cycles:posted writes" cycle, then address, bus command, data, and byte enables are stored in corresponding registers (see chapter REF _Ref513955180 \r \* MERGEFORMAT 0) and the WISHBONE slave unit locks out all, but the configuration space accesses until the proper error status bit will be cleared. The current transaction is discarded (pulled out of WBW_FIFO) while any other Posted Write XE "write cycles:posted writes" cycles are not influenced by Error XE "termination signals:error" .
If the transaction is a Read cycle, the termination is signaled to the WISHBONE master with an error on the WISHBONE bus when it retries a Read request.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 10: Timeout termination XE "termination signals:timeout termination " XE "waveforms:WISHBONE slave unit:timeout termination"
The Timeout termination is specified in the PCI Local Bus Specification. It must be implemented in the PCI master module. Timeout termination is not an abnormal termination; it is simply a means of assuring other masters access to the PCI bus within a reasonable span of time. The master is supposed to complete the transaction by the time the latency timer expires and its GNT# has been removed by the PCI arbiter. In other words, when the master latency timer expires, the PCI master module must sample its GNT# on every rising edge of clock. If it samples it in de-asserted mode, it must complete the transaction as soon as possible. As shown in REF _Ref513957411 \* MERGEFORMAT Figure 6 10, the latency timer of the master is assumed to expire and its grant to be removed by data phase N-1. The master module samples GNT# de-asserted, thus it completes an access on the next clock cycle by de-asserting FRAME#.
Timeout terminations are not signaled to the WISHBONE bus since the PCI master module can resume transaction the next time it gains bus mastership.
Timeout detection is implemented with a counter and the Master Latency Timer register in the PCI configuration space. The counter is enabled when the PCI master module asserts FRAME# and is cleared and suspended as soon as FRAME# is de-asserted.
6.1.4.2 Target Terminations Handled by PCI Master Module
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 11: Target Abort XE "waveforms:WISHBONE slave unit:target abort, PCI" XE "termination signals:target abort"
A target signals Target Abort XE "termination signals:target abort" to the master when it is and will be unable to complete the access initiated by the master. In this case, the master should not attempt to retry accesses terminated with Target Abort XE "termination signals:target abort" .
Posted Write XE "write cycles:posted writes" cycles terminated with Target Abort XE "termination signals:target abort" are discarded. If Error Reporting is enabled, the WISHBONE slave unit reports an error and locks out any non-configuration space accesses until the corresponding error status bit is cleared.
The Target Abort XE "termination signals:target abort" termination during Read cycles is signaled to the WISHBONE master when retrying the request. Access to the address that resulted in Target Abort XE "termination signals:target abort" is terminated with an error on the WISHBONE bus. If the WISHBONE master never accesses the address that resulted in Target Abort XE "termination signals:target abort" , termination will not be signaled in any way (Target Abort XE "termination signals:target abort" can be signaled because the PCI master module reads over address space boundaries of a specific target during a pre-fetched Read cycle in order that the WISHBONE master will never perform a Read cycle to that address).
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 12: Target Retry XE "waveforms:WISHBONE slave unit:target retry, PCI" XE "termination signals:retry"
A target signals a Retry XE "termination signals:retry" to the master when it is not ready to process the request. No data is transferred during Retry XE "termination signals:retry" . Nevertheless, the PCI master must still terminate normally by de-asserting FRAME# and keeping IRDY# asserted for one PCI clock cycle to indicate the last data phase. The master must relinquish the PCI bus for at least two cycles after it received a Target Retry XE "termination signals:target retry" by de-asserting its REQ# line. It must also retry the same request at a later time.
Target Retry XE "termination signals:target retry" is not signaled on the WISHBONE bus. The PCI master module retries the transaction transparently on the PCI bus.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 13: Target Disconnect XE "termination signals:target disconnect without data" without data XE "waveforms:WISHBONE slave unit:target disconnect without data, PCI"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 14: Target Disconnect XE "termination signals:target disconnect with data" with data XE "waveforms:WISHBONE slave unit:target disconnect with data, PCI"
A target signals Target Disconnect XE "termination signals:target disconnect" to the master when it is not capable of receiving or supplying any more data from/to the master. Data must be transferred with (Disconnect XE "termination signals:disconnect with data" with Data) or before (Disconnect XE "termination signals:disconnect without data" without Data) the target signals Target Disconnect XE "termination signals:target disconnect" . The master must terminate the transaction normally by de-asserting FRAME# and keeping IRDY# asserted for one clock cycle. If the target signals Target Disconnect XE "termination signals:target disconnect with data" with data on the last data phase (FRAME# de-asserted, IRDY#, TRDY#, and STOP# asserted), the termination is treated as a normal master termination. (e.g. STOP# is a Logical Dont Care for a master when FRAME# is de-asserted and IRDY# and TRDY# are asserted).
Target Disconnect XE "termination signals:target disconnect" is not an abnormal termination and will not be signaled to the WISHBONE master in any way. XE "WISHBONE:slave unit:waveforms" \r "WaveformsWISHBONE" XE "termination cycles:PCI" \r "TerminationCyclesPCI"
6.2 PCI Target Unit
This section describes basic waveforms of various accesses to core configuration space and mapped WISHBONE address space. Waveforms supplied have only informational value at this time.
6.1.2 PCI Configuration Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 15: PCI Configuration Read cycle XE "waveforms:PCI target unit:configuration read cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 16: PCI Configuration Write cycle XE "configuration write cycles" XE "waveforms:PCI target unit:configuration write cycle" XE "waveforms:PCI target unit:target read cycle"
PCI initiators will most commonly use Single Read XE "read cycles:single reads" cycles for accessing the core configuration space as shown in REF _Ref514563187 \h \* MERGEFORMAT Figure 6 15. A Write cycle to the register space of the core by the PCI initiator is shown in REF _Ref514563200 \h \* MERGEFORMAT Figure 6 16. Write cycles to unimplemented configuration space have no effect, while Read cycles return all 0s. XE "configuration cycles:PCI, waveforms" \r "ConfigurationCyclesPCI"
6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles
The following figures show how the PCI initiator sees cycles intended for the WISHBONE address space, traveling through the PCI target unit of the core. The first cycle in REF _Ref514567413 \* MERGEFORMAT Figure 6 17, started by the PCI initiator, is a Delayed Read command. The PCI target module accepts the Read command. Subsequent Reads in this cycle are terminated with Retry XE "termination signals:retry" . The next figure shows the previous transaction transferred to the WISHBONE bus. The second cycle in the first figure is a Read from the PCI master.
For reference: There are also burst accesses from the PCI through the PCI target module (Read and Write) on REF _Ref514567463 \* MERGEFORMAT Figure 6 19 and REF _Ref514564864 \* MERGEFORMAT Figure 6 20. Last follows a diagram of a Write transfer on the WISHBONE bus initiated by the PCI initiator.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 17: PCI Target Read cycle XE "waveforms:PCI target unit:target read cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 18: PCI to WISHBONE Read cycle XE "waveforms:PCI target unit:read cycle to WISHBONE"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 19: PCI Initiator to Target Burst Read XE "read cycles:burst reads" cycle XE "waveforms:PCI target unit:burst read cycle, initiator to target"
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 20: PCI Initiator to Target Burst Write cycle XE "waveforms:PCI target unit:burst write cycles, initiator to target"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 21: WISHBONE Write transfer caused by PCI to WISHBONE Write XE "waveforms:PCI target unit:write transfer, WISHBONE" cycle
6.2.3 WISHBONE Terminations
Terminations on the WISHBONE bus are always performed by WISHBONE slaves. Chapters REF _Ref527758515 \h 3.3.3 PCI to WISHBONE Write Cycles and REF _Ref527758530 \h 3.3.4 PCI to WISHBONE Read Cycles describe the causes of Retry XE "termination signals:retry" or Error XE "termination signals:error" on the WISHBONE bus.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 22: Retry XE "termination signals:retry" on WISHBONE bus XE "waveforms:PCI target unit:retry on WISHBONE bus" caused by PCI to WISHBONE transfer
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 23: Error XE "termination signals:error" on WISHBONE bus XE "waveforms:PCI target unit:error on WISHBONE bus" caused by PCI to WISHBONE transfer XE "PCI target unit:waveforms" \r "WaveformsPCI" XE "termination cycles:WISHBONE" \r "TerminationCyclesWISHBONE"
A
Core HW Configuration
This section describessummarizes parameters that are set by the usersystem designer of the core and define itscores configuration, the user (e.g. programmer) must know. The usersystem designer must set the parameters before actually using the core in simulation or synthesis. For details read PCI IP Core design document.
A.1 HW Configuration Parameters
Configuration parameters XE "configuration parameters" are grouped into one file, which can be edited by the system designer, depending on the needs of the application (see chapters 2.4 and 2.5 of the PCI IP Core Design document). Only parameters useful for the user of the core are summarized here. The system designer should mark which parameters are defined (or the value of the parameter).
ParameterDefined value / Defined (yes, no)DescriptionHOST / GUESTThese two defines are mutually exclusive. Core will be implemented or simulated with HOST or GUEST bridge features enabled (see chapter 3.1).WBW_ADDR_LENGTHWBR_ADDR_LENGTHPCIW_ADDR_LENGTHPCIR_ADDR_LENGTHNumbers defined here define each one of four Fifos size. Size is calculated as 2^^ADDR_LENGTH. Note that Fifos control logic is such, that one location in RAM is always empty, so usable Fifo size is (2^^ADDR_LENGTH) 1. Any value equal to or larger than 3 is valid here the only restriction is the size of RAMs instantiated for Fifo storage.ADDR_TRAN_IMPLIf defined, address translation functionality is added to decoders for both, PCI and WISHBONE accesses. Address translation implementation is useful when application uses fixed address map, while PCI address map is configurable. PCI_NUM_OF_DEC_ADDR_LINESNumber defined here is used for controlling implementation of PCI images decoders. It defines how many MSB address lines are used for decoding PCI Target accesses and therefore defines what minimum image size can be. Maximum number allowed is 20 ( 4KB minimum image size ) and minimum is 1 ( 2GB minimum image size this value implies that more than two images cannot be enabled at the same time ). NO_CNF_IMAGEIf defined, it prevents Read-Only configuration image to be implemented. Read-Only Configuration space access can be provided through PCI image 0 for HOST implementation of the Core, and through WB image 0 for GUEST implementation. If NO_CNF_IMAGE is defined, then this image is not implemented (some additional space is saved).PCI_IMAGE0 *This define only has meaning when HOST and NO_CNF_IMAGE are defined also. This enables usage of additional PCI Target image 0 (PCI_IMAGE0) for accessing WISHBONE bus address space from PCI address space. Otherwise, PCI_IMAGE0 does not needs to be defined, since it is always used for accessing Configuration space.PCI_IMAGE2 *PCI_IMAGE3 *PCI_IMAGE4 *PCI_IMAGE5 *If whichever defined, then that PCI Target image is implemented.PCI_AM0 ***PCI_AM1PCI_AM2 **PCI_AM3 **PCI_AM4 **PCI_AM5 **Numbers defined here are initial ( reset ) values of PCI address masks registers. These are very important if the Core is implemented as GUEST, since configuration is done via PCI Target state machine. If the designer wants an implemented PCI Target image to be detected by device independent software at system power-up, he has to set initial masks to enabled state MS bit has to be 1. Other bits can have a value of 1 or zero, depending on what size of an image has to be presented to the software. The masks can be set inactive also, but device independent software wont detect implemented PCI Target images and therefore not configure them. Device specific software will then have to jump in to configure images with inactive initial masks defined, which also means that it will probably have to rebuild PCI address space map.PCI_BA0_MEM_IO ***PCI_BA1_MEM_IOPCI_BA2_MEM_IO **PCI_BA3_MEM_IO **PCI_BA4_MEM_IO **PCI_BA5_MEM_IO **Numbers defined here are initial ( reset ) values of PCI Base Address registers bits 0. If the Core is configured as HOST, this initial values can later be changed by writing appropriate value to appropriate PCI Base Address register. If the core is GUEST, than this values are hardwired, because device independent software must know in advance where to map each PCI Base Address.WB_NUM_OF_DEC_ADDR_LINESNumber defined here is used for controlling implementation of WISHBONE images decoders. It defines how many MSB address lines are used for decoding WISHBONE Slave accesses and therefore defines what minimum image size can be. Maximum number allowed is 20 (4KB minimum image size) and minimum is 1 (2GB minimum image size this value implies that more than two images cannot be enabled at the same time). WB_IMAGE2WB_IMAGE3WB_IMAGE4WB_IMAGE5If whichever defined, then that WB Slave image is implemented.WB_CONFIGURATION_BASENumber defined here is a 20 bit value for WISHBONE configuration image address. Those bits are compared to 20 MS bits of WB Slave address to decode Configuration accesses from WB bus. This is constant value and cannot be changed after the Core is implemented, since WB bus does not provide any special mechanism for device configuration.WB_RTY_CNT_MAXNumber defined here is used to prevent deadlock in WB Master state machine for maximum counting value of RTY terminations on WB bus, before ACK or ERR terminations. The last two terminations reset the counter. This counter is also used, when no WB device responds (e.g. if accessing to unused memory locations). In that case internal set_retry signal is set every 8 WB clock periods and counter counts to maximum value defined.PCI33 / PCI66These two defines are mutually exclusive. They are used for simulation purposes ( PCI clock speed ) and to set 66MHz Capable bit in PCI Device Status register, if PCI66 is defined. There are no other features dependent on those defines.HEADER_VENDOR_IDEach PCI bus compatible hardware vendor gets its 16 bit hexadecimal ID from PCI SIG organization. It should be specified in this define. This value shows up in Vendor ID register of PCI Type0 Configuration Header.HEADER_DEVICE_IDDevice ID is vendor specific, 16 bit hexadecimal value. It shows up in Device ID register of PCI Type0 Configuration Header.HEADER_REVISION_IDRevision ID is vendor specific, 8 bit hexadecimal value, that shows up in Revision ID register of PCI Type0 Configuration Header.* ( PCI image 1 is always implemented, without any exceptions
** ( This value is significant only if appropriate PCI image is implemented
*** ( This value is significant only if PCI image 0 is implemented to access WB bus
Table STYLEREF 1 \s 6 SEQ Table \* ARABIC \s 1 1: User Useful HARDWARE Configuration Parameters
INDEX \e " " \c "2" \z "1033" address translation logic
address mask register, setting rule 10
address range 10
architecture 11
registers 10
architecture
address translation logic 1011
clocks 8
FIFO 89
PCI bridge, general overview 3
PCI target unit 68, 25
WISHBONE slave unit 46, 19
clocks 8, 9
compliances
PCI interface 3
WISHBONE 3
configuration cycles 14, 1518
access to configuration space 15
field values 1617
generating 16
PCI, waveforms 74
registers 5557
WISHBONE, waveforms 6566
configuration parameters 78
configuration space 1218
access for guest bus bridges 14
access for host bus bridges 13
access to configuration cycles 15
access, general 12
definition 12
header
class code 44
device ID 43
header type 43
registers 4447
revision ID 43
vendor ID 43
interrupt acknowledge cycles 18
configuration write cycles 66, 74
decoder 4
device identification See configuration space header
encoding 21, 24, 28, 29, 31
expansion bus bridges See guest bus bridges
features, PCI IP core 12
field values, configuration cycles 1617
FIFO 89
architechture 9
architecture 8
PCI read FIFO 7, 26
PCI write FIFO 7, 26
register lines 8
WISHBONE read FIFO 5, 6, 19
WISHBONE write FIFO 5, 6, 19
First in First out 89. See also FIFO
identification See configuration space header
interrupt acknowledge cycles
generating 18
register 57
interrupts, generating and reporting 3334
IO ports
PCI interface
address and data pins 61
arbitration pins 62
error reporting pins 62
interface control pins, optional 63
interface control pins, required 62
interrupt pins, optional 62
system pins 62
WISHBONE interface
common control and system I/Os 64
PCI target unit 63
WISHBONE slave unit 64
operation
configuration space 1218
interrupts 3334
parity 33
transaction ordering 3233
WISHBONE slave unit 1825
parity 33
PCI bridge, introduction
architecture 3
function 1
PCI target unit 3
WISHBONE slave unit 3
PCI target unit 3
address range, example 27
address space access
I/O mapped 28
memory mapped 29
address space, non-prefetchable 31
address translation, example 28
architecture 68, 25
basic functionality 25
configuration space header 4347
encoding 28, 29, 31
error reporting mechanism 30
error reporting registers 5355
function 6
images mapped to I/O space 31
images mapped to memory space 30
images, configurable 26
images, selecting 6
read FIFO 7, 26
target module 7, 26
termination signals 24, 32
waveforms 7477
WISHBONE master module 8, 26
write cycles to WISHBONE 2830
write FIFO 26
pins
optional 6263
required 6162
read cycles
block reads 23, 31
burst reads 23, 24, 31, 32, 69, 76
delayed reads 5, 22, 23, 24, 29, 30, 31, 33, 67
single reads 12, 14, 25, 31, 66, 68, 74
WISHBONE to PCI 2123
registers
interrupt, control & status 60
list of 3538
PCI target unit, configuration space header 4347
PCI target unit, control & status 51
reporting 57
WISHBONE slave unit, control & status 42
termination cycles
PCI 7073
WISHBONE 77
termination signals
disconnect 25, 29
disconnect with data 24, 31, 73
disconnect with/without data 29, 32
disconnect without data 24, 73
error 22, 23, 30, 31, 32, 52, 53, 54, 55, 70, 77
master abort 18, 22, 25, 45, 52, 70
retry 22, 24, 25, 29, 31, 32, 33, 52, 54, 67, 72, 75, 77
system error 45
target abort 22, 24, 25, 28, 29, 32, 45, 52, 71, 72
target disconnect 22, 24, 73
target disconnect with data 14, 15, 28, 73
target disconnect without data 73
target retry 72
timeout termination 71
transaction ordering 3233
waveforms
PCI target unit
burst read cycle, initiator to target 76
burst write cycles, initiator to target 76
configuration read cycle 74
configuration write cycle 74
error on WISHBONE bus 77
read cycle to WISHBONE 75
retry on WISHBONE bus 77
target read cycle 74, 75
write transfer, WISHBONE 76
WISHBONE slave unit
access to PCI address space 67
burst read cycle, PCI 69
burst write cycle, PCI 69
configuration read cycle 65
configuration read modify write cycle 66
configuration write cycle 66
master abort termination, PCI 70
single read cycle, PCI 68
single writes, PCI 68
target abort, PCI 71
target disconnect with data, PCI 73
target disconnect without data, PCI 73
target retry, PCI 72
timeout termination 71
WISHBONE
bus agents 4
slave module
read FIFO 6
slave unit
address range, example 20
address space, non-prefetchable 23
address translation, example 21
architecture 46
decoder 4
encoding 21, 24
error reporting mechanism 2223
error reporting registers 5153
function 4
images mapped to I/O space 23
images mapped to memory space 23
images, configurable 4, 20
operation 1825
PCI master module 6, 19
read cycles to PCI 23, 25
read FIFO 5, 19
slave module 5, 19
termination signals 32
waveforms 6573
write cycles to PCI 2123
write FIFO 5, 6, 19
write cycles
block writes 21, 22, 28, 30, 67
burst writes 29, 30, 69
PCI to WISHBONE 2830
posted writes 5, 6, 21, 22, 28, 30, 33, 51, 70, 72
read modify writes (RMW) 14, 21, 66
single writes 12, 14, 21, 22, 28, 30, 68
WISHBONE to PCI 2123
Note: Because the host bus bridge normally generates configuration commands, and the PCI local bus specification does not require a host bus bridge to respond to configuration cycles, it is most likely that this feature will never be used.
INCLUDEPICTURE "http://www.opencores.org/logos/jng3.gif" \* MERGEFORMATINET OpenCores PCI IP Core Specification DATE \@ "d.M.yyyy" 28.1.2002
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.6 PAGE iv
INCLUDEPICTURE "http://www.opencores.org/logos/jng3.gif" \* MERGEFORMATINET OpenCores PCI IP Core Specification DATE \@ "d.M.yyyy" 28.1.2002
EMBED Word.Picture.8
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N F \ T I] d > c c H " " " " " "
PCI IP Core
Specification
Authors: Miha Dolenc & Tadej Markovic
mihad@opencores.org
tadej@opencores.org
Rev. 0.6
TIME \@ "MMMM d, yyyy" January 28, 2002
Revision History
Rev.DateAuthorDescription0.05/1/01Miha Dolenc
Tadej MarkovicFirst Draft0.15/8/01Miha Dolenc
Tadej MarkovicWaveforms added for WISHBONE slave0.25/15/01Miha Dolenc
Tadej MarkovicDetailed description of FIFO added, Operation of PCI target unit added, Waveforms added for PCI target0.35/22/01Miha Dolenc
Tadej MarkovicFIFO structure changed0.410/13/01Jeanne WiegelmannFirst review0.510/20/01Miha Dolenc
Tadej MarkovicUpdated register descriptions and Configuration Space access0.601/28/02Miha Dolenc
Tadej MarkovicUpdated descriptions and added Software obligations
List of Contents
TOC \o "2-3" \h \z \t "Headeing 1 Name;1;Index;1;Appendix Name;1;Heading 1 appendix;1" HYPERLINK \l "_Toc156141" Introduction PAGEREF _Toc156141 \h 1
HYPERLINK \l "_Toc156142" 1.1 What is a PCI Bridge? PAGEREF _Toc156142 \h 1
HYPERLINK \l "_Toc156143" 1.2 PCI IP Core Introduction PAGEREF _Toc156143 \h 1
HYPERLINK \l "_Toc156144" 1.3 PCI IP Core Features PAGEREF _Toc156144 \h 1
HYPERLINK \l "_Toc156145" Architecture PAGEREF _Toc156145 \h 3
HYPERLINK \l "_Toc156146" 2.1 Overview PAGEREF _Toc156146 \h 3
HYPERLINK \l "_Toc156147" 2.2 WISHBONE Slave Unit PAGEREF _Toc156147 \h 4
HYPERLINK \l "_Toc156148" 2.2.1 WISHBONE Slave Unit Architecture PAGEREF _Toc156148 \h 5
HYPERLINK \l "_Toc156149" 2.3 PCI Target Unit PAGEREF _Toc156149 \h 6
HYPERLINK \l "_Toc156150" 2.3.1 PCI Target Unit Architecture PAGEREF _Toc156150 \h 6
HYPERLINK \l "_Toc156151" 2.4 Clocks PAGEREF _Toc156151 \h 8
HYPERLINK \l "_Toc156152" 2.5 FIFO PAGEREF _Toc156152 \h 8
HYPERLINK \l "_Toc156153" 2.6 Address Translation Logic PAGEREF _Toc156153 \h 10
HYPERLINK \l "_Toc156154" 2.6.1 Description of Address Translation Logic PAGEREF _Toc156154 \h 10
HYPERLINK \l "_Toc156155" Operation PAGEREF _Toc156155 \h 12
HYPERLINK \l "_Toc156156" 3.1 Configuration Space PAGEREF _Toc156156 \h 12
HYPERLINK \l "_Toc156157" 3.1.1 Configuration Space Access for Host Bus Bridges PAGEREF _Toc156157 \h 13
HYPERLINK \l "_Toc156158" 3.1.2 Configuration Space Access for Guest Bridges PAGEREF _Toc156158 \h 14
HYPERLINK \l "_Toc156159" 3.1.3 Configuration Cycles PAGEREF _Toc156159 \h 15
HYPERLINK \l "_Toc156160" 3.1.4 Generating Configuration Cycles PAGEREF _Toc156160 \h 16
HYPERLINK \l "_Toc156161" 3.1.5 Generating Interrupt Acknowledge Cycles PAGEREF _Toc156161 \h 18
HYPERLINK \l "_Toc156162" 3.2 WISHBONE Slave Unit PAGEREF _Toc156162 \h 18
HYPERLINK \l "_Toc156163" 3.2.1 WISHBONE Slave Unit Functionality PAGEREF _Toc156163 \h 19
HYPERLINK \l "_Toc156164" 3.2.2 Addressing and Images of the WISHBONE Slave Unit PAGEREF _Toc156164 \h 20
HYPERLINK \l "_Toc156165" 3.2.3 WISHBONE to PCI Write Cycles PAGEREF _Toc156165 \h 21
HYPERLINK \l "_Toc156166" 3.2.4 WISHBONE to PCI Read Cycles PAGEREF _Toc156166 \h 23
HYPERLINK \l "_Toc156167" 3.3 PCI Target Unit PAGEREF _Toc156167 \h 25
HYPERLINK \l "_Toc156168" 3.3.1 PCI Target Unit Functionality PAGEREF _Toc156168 \h 25
HYPERLINK \l "_Toc156169" 3.3.2 Addressing and Images of the PCI Target Unit PAGEREF _Toc156169 \h 26
HYPERLINK \l "_Toc156170" 3.3.3 PCI to WISHBONE Write Cycles PAGEREF _Toc156170 \h 28
HYPERLINK \l "_Toc156171" 3.3.4 PCI to WISHBONE Read Cycles PAGEREF _Toc156171 \h 30
HYPERLINK \l "_Toc156172" 3.4 Transaction Ordering PAGEREF _Toc156172 \h 32
HYPERLINK \l "_Toc156173" 3.5 Parity PAGEREF _Toc156173 \h 33
HYPERLINK \l "_Toc156174" 3.6 Interrupts PAGEREF _Toc156174 \h 33
HYPERLINK \l "_Toc156175" Registers PAGEREF _Toc156175 \h 35
HYPERLINK \l "_Toc156176" 4.1 Register List and Description PAGEREF _Toc156176 \h 35
HYPERLINK \l "_Toc156177" 4.1.1 WISHBONE Slave Unit Control & Status PAGEREF _Toc156177 \h 38
HYPERLINK \l "_Toc156178" 4.1.2 PCI Target Unit Control & Status PAGEREF _Toc156178 \h 42
HYPERLINK \l "_Toc156179" 4.1.3 Reporting Registers PAGEREF _Toc156179 \h 51
HYPERLINK \l "_Toc156180" 4.1.4 Interrupt Control & Status Registers PAGEREF _Toc156180 \h 57
HYPERLINK \l "_Toc156181" 4.2 Software obligations PAGEREF _Toc156181 \h 60
HYPERLINK \l "_Toc156182" IO Ports PAGEREF _Toc156182 \h 61
HYPERLINK \l "_Toc156183" 5.1 PCI Interface PAGEREF _Toc156183 \h 61
HYPERLINK \l "_Toc156184" 5.1.1 Required PCI Interface Pins PAGEREF _Toc156184 \h 61
HYPERLINK \l "_Toc156185" 5.1.2 Implemented Optional PCI Interface Pins PAGEREF _Toc156185 \h 62
HYPERLINK \l "_Toc156186" 5.2 WISHBONE Interface PAGEREF _Toc156186 \h 63
HYPERLINK \l "_Toc156187" Waveforms PAGEREF _Toc156187 \h 65
HYPERLINK \l "_Toc156188" 6.1 Wishbone Slave Unit PAGEREF _Toc156188 \h 65
HYPERLINK \l "_Toc156189" 6.1.1 WISHBONE Configuration Accesses PAGEREF _Toc156189 \h 65
HYPERLINK \l "_Toc156190" 6.1.2 WISHBONE to PCI Accesses PAGEREF _Toc156190 \h 67
HYPERLINK \l "_Toc156191" 6.1.3 PCI Cycles PAGEREF _Toc156191 \h 67
HYPERLINK \l "_Toc156192" 6.1.4 PCI Terminations PAGEREF _Toc156192 \h 70
HYPERLINK \l "_Toc156193" 6.2 PCI Target Unit PAGEREF _Toc156193 \h 74
HYPERLINK \l "_Toc156194" 6.1.2 PCI Configuration Accesses PAGEREF _Toc156194 \h 74
HYPERLINK \l "_Toc156195" 6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles PAGEREF _Toc156195 \h 75
HYPERLINK \l "_Toc156196" 6.2.3 WISHBONE Terminations PAGEREF _Toc156196 \h 77
HYPERLINK \l "_Toc156197" Core HW Configuration PAGEREF _Toc156197 \h 78
HYPERLINK \l "_Toc156198" A.1 HW Configuration Parameters PAGEREF _Toc156198 \h 78
HYPERLINK \l "_Toc156199" Index PAGEREF _Toc156199 \h 82
TOC \o "3-3" \h \z \t "Heading 2,2,Headeing 1 Name,1,Index,1,Appendix,1" HYPERLINK \l "_Toc530197944" Introduction PAGEREF _Toc530197944 \h 1
HYPERLINK \l "_Toc530197945" 1.1 What is a PCI Bridge? PAGEREF _Toc530197945 \h 1
HYPERLINK \l "_Toc530197946" 1.2 PCI IP Core Introduction PAGEREF _Toc530197946 \h 1
HYPERLINK \l "_Toc530197947" 1.3 PCI IP Core Features PAGEREF _Toc530197947 \h 1
HYPERLINK \l "_Toc530197948" Architecture PAGEREF _Toc530197948 \h 3
HYPERLINK \l "_Toc530197949" 2.1 Overview PAGEREF _Toc530197949 \h 3
HYPERLINK \l "_Toc530197950" 2.2 WISHBONE Slave Unit PAGEREF _Toc530197950 \h 4
HYPERLINK \l "_Toc530197951" 2.2.1 WISHBONE Slave Unit Architecture PAGEREF _Toc530197951 \h 5
HYPERLINK \l "_Toc530197952" 2.3 PCI Target Unit PAGEREF _Toc530197952 \h 6
HYPERLINK \l "_Toc530197953" 2.3.1 PCI Target Unit Architecture PAGEREF _Toc530197953 \h 6
HYPERLINK \l "_Toc530197954" 2.4 Clocks PAGEREF _Toc530197954 \h 8
HYPERLINK \l "_Toc530197955" 2.5 FIFO PAGEREF _Toc530197955 \h 8
HYPERLINK \l "_Toc530197956" 2.6 Address Translation Logic PAGEREF _Toc530197956 \h 10
HYPERLINK \l "_Toc530197957" 2.6.1 Description of Address Translation Logic PAGEREF _Toc530197957 \h 10
HYPERLINK \l "_Toc530197958" Operation PAGEREF _Toc530197958 \h 12
HYPERLINK \l "_Toc530197959" 3.1 Configuration Space PAGEREF _Toc530197959 \h 12
HYPERLINK \l "_Toc530197960" 3.1.1 Configuration Space Access for Host Bus Bridges PAGEREF _Toc530197960 \h 13
HYPERLINK \l "_Toc530197961" 3.1.2 Configuration Space Access for Guest Bridges PAGEREF _Toc530197961 \h 14
HYPERLINK \l "_Toc530197962" 3.1.3 Configuration Cycles PAGEREF _Toc530197962 \h 15
HYPERLINK \l "_Toc530197963" 3.1.4 Generating Configuration Cycles PAGEREF _Toc530197963 \h 16
HYPERLINK \l "_Toc530197964" 3.1.5 Generating Interrupt Acknowledge Cycles PAGEREF _Toc530197964 \h 18
HYPERLINK \l "_Toc530197965" 3.2 WISHBONE Slave Unit PAGEREF _Toc530197965 \h 18
HYPERLINK \l "_Toc530197966" 3.2.1 WISHBONE Slave Unit Functionality PAGEREF _Toc530197966 \h 19
HYPERLINK \l "_Toc530197967" 3.2.2 Addressing and Images of the WISHBONE Slave Unit PAGEREF _Toc530197967 \h 20
HYPERLINK \l "_Toc530197968" 3.2.3 WISHBONE to PCI Write Cycles PAGEREF _Toc530197968 \h 21
HYPERLINK \l "_Toc530197969" 3.2.4 WISHBONE to PCI Read Cycles PAGEREF _Toc530197969 \h 23
HYPERLINK \l "_Toc530197970" 3.3 PCI Target Unit PAGEREF _Toc530197970 \h 25
HYPERLINK \l "_Toc530197971" 3.3.1 PCI Target Unit Functionality PAGEREF _Toc530197971 \h 25
HYPERLINK \l "_Toc530197972" 3.3.2 Addressing and Images of the PCI Target Unit PAGEREF _Toc530197972 \h 26
HYPERLINK \l "_Toc530197973" 3.3.3 PCI to WISHBONE Write Cycles PAGEREF _Toc530197973 \h 27
HYPERLINK \l "_Toc530197974" 3.3.3.4 PCI to WISHBONE Read Cycles PAGEREF _Toc530197974 \h 30
HYPERLINK \l "_Toc530197975" 3.4 Transaction Ordering PAGEREF _Toc530197975 \h 32
HYPERLINK \l "_Toc530197976" 3.5 Parity PAGEREF _Toc530197976 \h 33
HYPERLINK \l "_Toc530197977" 3.6 Interrupts PAGEREF _Toc530197977 \h 33
HYPERLINK \l "_Toc530197978" Registers PAGEREF _Toc530197978 \h 34
HYPERLINK \l "_Toc530197979" 4.1 Register List and Description PAGEREF _Toc530197979 \h 34
HYPERLINK \l "_Toc530197980" 4.1.1 WISHBONE Slave Unit Control & Status PAGEREF _Toc530197980 \h 37
HYPERLINK \l "_Toc530197981" 4.1.2 PCI Target Unit Control & Status PAGEREF _Toc530197981 \h 41
HYPERLINK \l "_Toc530197982" 4.1.3 Reporting Registers PAGEREF _Toc530197982 \h 50
HYPERLINK \l "_Toc530197983" 4.1.4 Interrupt Control & Status Registers PAGEREF _Toc530197983 \h 56
HYPERLINK \l "_Toc530197984" IO Ports PAGEREF _Toc530197984 \h 59
HYPERLINK \l "_Toc530197985" 5.1 PCI Interface PAGEREF _Toc530197985 \h 59
HYPERLINK \l "_Toc530197986" 5.1.1 Required PCI Interface Pins PAGEREF _Toc530197986 \h 59
HYPERLINK \l "_Toc530197987" 5.1.2 Implemented Optional PCI Interface Pins PAGEREF _Toc530197987 \h 60
HYPERLINK \l "_Toc530197988" 5.2 WISHBONE Interface PAGEREF _Toc530197988 \h 61
HYPERLINK \l "_Toc530197989" Waveforms PAGEREF _Toc530197989 \h 63
HYPERLINK \l "_Toc530197990" 6.1 Wishbone Slave Unit PAGEREF _Toc530197990 \h 63
HYPERLINK \l "_Toc530197991" 6.1.1 WISHBONE Configuration Accesses PAGEREF _Toc530197991 \h 63
HYPERLINK \l "_Toc530197992" 6.1.2 WISHBONE to PCI Accesses PAGEREF _Toc530197992 \h 65
HYPERLINK \l "_Toc530197993" 6.1.3 PCI Cycles PAGEREF _Toc530197993 \h 65
HYPERLINK \l "_Toc530197994" 6.1.4 PCI Terminations PAGEREF _Toc530197994 \h 68
HYPERLINK \l "_Toc530197995" 6.2 PCI Target Unit PAGEREF _Toc530197995 \h 72
HYPERLINK \l "_Toc530197996" 6.1.2 PCI Configuration Accesses PAGEREF _Toc530197996 \h 72
HYPERLINK \l "_Toc530197997" 6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles PAGEREF _Toc530197997 \h 73
HYPERLINK \l "_Toc530197998" 6.2.3 WISHBONE Terminations PAGEREF _Toc530197998 \h 75
HYPERLINK \l "_Toc530197999" Appendix A PAGEREF _Toc530197999 \h 76
HYPERLINK \l "_Toc530198000" A.1 HW Configuration Parameters PAGEREF _Toc530198000 \h 76
HYPERLINK \l "_Toc530198001" Index PAGEREF _Toc530198001 \h 77
List of Tables
TOC \h \z \t "Caption,1" HYPERLINK \l "_Toc530198002" Table 3 1: Value on AD[31:11] PCI bus lines during address phase of configuration cycle Type 0 PAGEREF _Toc530198002 \h 17
HYPERLINK \l "_Toc530198003" Table 3 2: Valid ADDR_O(1:0) and SEL_O(3:0) combinations for I/O mapped address space access PAGEREF _Toc530198003 \h 22
HYPERLINK \l "_Toc530198004" Table 3 3: Bus command encoding for Read cycles through PCI master module PAGEREF _Toc530198004 \h 24
HYPERLINK \l "_Toc530198005" Table 3 4: Valid AD(1:0) and BE# (3:0) combinations for I/O mapped address space accesses PAGEREF _Toc530198005 \h 28
HYPERLINK \l "_Toc530198006" Table 3 5: Burst Ordering combinations for memory mapped address space accesses PAGEREF _Toc530198006 \h 29
HYPERLINK \l "_Toc530198007" Table 3 6: Bus command encoding for Read cycles through PCI target module PAGEREF _Toc530198007 \h 31
HYPERLINK \l "_Toc530198008" Table 4 1: List of registers PAGEREF _Toc530198008 \h 38
HYPERLINK \l "_Toc530198009" Table 4 2: WISHBONE configuration space Base Address register PAGEREF _Toc530198009 \h 38
HYPERLINK \l "_Toc530198010" Table 4 3: WISHBONE Image Control register PAGEREF _Toc530198010 \h 39
HYPERLINK \l "_Toc530198011" Table 4 4: WISHBONE Image Control register bit descriptions PAGEREF _Toc530198011 \h 40
HYPERLINK \l "_Toc530198012" Table 4 5: WISHBONE Base Address register PAGEREF _Toc530198012 \h 40
HYPERLINK \l "_Toc530198013" Table 4 6: WISHBONE Base Address register bit descriptions PAGEREF _Toc530198013 \h 40
HYPERLINK \l "_Toc530198014" Table 4 7: WISHBONE Address Mask register PAGEREF _Toc530198014 \h 41
HYPERLINK \l "_Toc530198015" Table 4 8: WISHBONE Address Mask register bit descriptions PAGEREF _Toc530198015 \h 41
HYPERLINK \l "_Toc530198016" Table 4 9: WISHBONE Translation Address register PAGEREF _Toc530198016 \h 42
HYPERLINK \l "_Toc530198017" Table 4 10: WISHBONE Translation Address register bit descriptions PAGEREF _Toc530198017 \h 42
HYPERLINK \l "_Toc530198018" Table 4 11: Command register of PCI configuration header PAGEREF _Toc530198018 \h 45
HYPERLINK \l "_Toc530198019" Table 4 12: Status register of PCI configuration header PAGEREF _Toc530198019 \h 46
HYPERLINK \l "_Toc530198020" Table 4 13: Base Address register of PCI configuration header for memory mapped space PAGEREF _Toc530198020 \h 47
HYPERLINK \l "_Toc530198021" Table 4 14: Base Address register of PCI configuration header for I/O mapped space PAGEREF _Toc530198021 \h 47
HYPERLINK \l "_Toc530198022" Table 4 15: PCI Image0 Base Address register PAGEREF _Toc530198022 \h 47
HYPERLINK \l "_Toc530198023" Table 4 16: PCI Image Control Register PAGEREF _Toc530198023 \h 48
HYPERLINK \l "_Toc530198024" Table 4 17: PCI Image Control Register bit descriptions PAGEREF _Toc530198024 \h 48
HYPERLINK \l "_Toc530198025" Table 4 18: PCI Base Address register PAGEREF _Toc530198025 \h 49
HYPERLINK \l "_Toc530198026" Table 4 19: PCI Base Address register bit descriptions PAGEREF _Toc530198026 \h 49
HYPERLINK \l "_Toc530198027" Table 4 20: PCI Address Mask register PAGEREF _Toc530198027 \h 50
HYPERLINK \l "_Toc530198028" Table 4 21: PCI Address Mask register bit descriptions PAGEREF _Toc530198028 \h 50
HYPERLINK \l "_Toc530198029" Table 4 22: PCI Translation Address register PAGEREF _Toc530198029 \h 51
HYPERLINK \l "_Toc530198030" Table 4 23: PCI Translation Address register bit descriptions PAGEREF _Toc530198030 \h 51
HYPERLINK \l "_Toc530198031" Table 4 24: WISHBONE Error Control and Status register PAGEREF _Toc530198031 \h 52
HYPERLINK \l "_Toc530198032" Table 4 25: WISHBONE Error Control and Status register bit descriptions PAGEREF _Toc530198032 \h 53
HYPERLINK \l "_Toc530198033" Table 4 26: WISHBONE Erroneous Address register PAGEREF _Toc530198033 \h 53
HYPERLINK \l "_Toc530198034" Table 4 27: WISHBONE Erroneous Data register PAGEREF _Toc530198034 \h 53
HYPERLINK \l "_Toc530198035" Table 4 28: PCI Error Control and Status register PAGEREF _Toc530198035 \h 53
HYPERLINK \l "_Toc530198036" Table 4 29: PCI Error Control and Status register Bit Descriptions PAGEREF _Toc530198036 \h 55
HYPERLINK \l "_Toc530198037" Table 4 30: PCI Erroneous Address register PAGEREF _Toc530198037 \h 55
HYPERLINK \l "_Toc530198038" Table 4 31: PCI Erroneous Data Register PAGEREF _Toc530198038 \h 55
HYPERLINK \l "_Toc530198039" Table 4 32: Configuration Address register PAGEREF _Toc530198039 \h 55
HYPERLINK \l "_Toc530198040" Table 4 33: Configuration Address register bit descriptions PAGEREF _Toc530198040 \h 56
HYPERLINK \l "_Toc530198041" Table 4 34: Configuration Data Register PAGEREF _Toc530198041 \h 57
HYPERLINK \l "_Toc530198042" Table 4 35: Interrupt Acknowledge register PAGEREF _Toc530198042 \h 57
HYPERLINK \l "_Toc530198043" Table 4 36: Interrupt Control register PAGEREF _Toc530198043 \h 57
HYPERLINK \l "_Toc530198044" Table 4 37: Interrupt Control Register bit descriptions PAGEREF _Toc530198044 \h 58
HYPERLINK \l "_Toc530198045" Table 4 38: Interrupt Status register PAGEREF _Toc530198045 \h 59
HYPERLINK \l "_Toc530198046" Table 4 39: Interrupt Status register bit descriptions PAGEREF _Toc530198046 \h 60
HYPERLINK \l "_Toc530198047" Table 5 1: PCI address and data pins PAGEREF _Toc530198047 \h 61
HYPERLINK \l "_Toc530198048" Table 5 2: PCI interface control pins PAGEREF _Toc530198048 \h 62
HYPERLINK \l "_Toc530198049" Table 5 3: PCI error reporting pins PAGEREF _Toc530198049 \h 62
HYPERLINK \l "_Toc530198050" Table 5 4: PCI arbitration pins (INITIATOR only) PAGEREF _Toc530198050 \h 62
HYPERLINK \l "_Toc530198051" Table 5 5: PCI system pins PAGEREF _Toc530198051 \h 62
HYPERLINK \l "_Toc530198052" Table 5 6: PCI interrupt pin PAGEREF _Toc530198052 \h 62
HYPERLINK \l "_Toc530198053" Table 5 7: PCI interface control pins PAGEREF _Toc530198053 \h 63
HYPERLINK \l "_Toc530198054" Table 5 8: PCI target units WISHBONE interface (master) PAGEREF _Toc530198054 \h 63
HYPERLINK \l "_Toc530198055" Table 5 9: WISHBONE slave units WISHBONE interface (slave) PAGEREF _Toc530198055 \h 64
HYPERLINK \l "_Toc530198056" Table 5 10: WISHBONE common control and system I/Os PAGEREF _Toc530198056 \h 64
List of Figures & Examples
TOC \h \z \t "Caption 1,1" HYPERLINK \l "_Toc530198057" Figure 2 1: PCI bridge core architecture PAGEREF _Toc530198057 \h 4
HYPERLINK \l "_Toc530198058" Figure 2 2: WISHBONE slave unit architecture PAGEREF _Toc530198058 \h 5
HYPERLINK \l "_Toc530198059" Figure 2 3: PCI target unit architecture overview PAGEREF _Toc530198059 \h 7
HYPERLINK \l "_Toc530198060" Figure 2 4: Detailed Description of FIFO Register Lines PAGEREF _Toc530198060 \h 8
HYPERLINK \l "_Toc530198061" Figure 2 5: FIFO Architecture PAGEREF _Toc530198061 \h 9
HYPERLINK \l "_Toc530198062" Figure 2 6: Address Translation Logic PAGEREF _Toc530198062 \h 11
HYPERLINK \l "_Toc530198063" Figure 3 1: PCI Bridge Configuration Space PAGEREF _Toc530198063 \h 13
HYPERLINK \l "_Toc530198064" Figure 3 2: Configuration space access for Host Bus Bridges PAGEREF _Toc530198064 \h 14
HYPERLINK \l "_Toc530198065" Figure 3 3: Configuration space access for Guest Bridges PAGEREF _Toc530198065 \h 15
HYPERLINK \l "_Toc530198066" Figure 3 4: WISHBONE Slave Unit Architecture Overview PAGEREF _Toc530198066 \h 19
HYPERLINK \l "_Toc530198067" Example 3 1: Address range of WISHBONE slave image PAGEREF _Toc530198067 \h 20
HYPERLINK \l "_Toc530198068" Example 3 2: Address translation PAGEREF _Toc530198068 \h 21
HYPERLINK \l "_Toc530198069" Figure 3 5: PCI target unit architecture overview PAGEREF _Toc530198069 \h 25
HYPERLINK \l "_Toc530198070" Example 3 3: Address range of WISHBONE slave image PAGEREF _Toc530198070 \h 27
HYPERLINK \l "_Toc530198071" Example 3 4: Address translation PAGEREF _Toc530198071 \h 28
HYPERLINK \l "_Toc530198072" Figure 4 1: WISHBONE configuration space Base Address register layout PAGEREF _Toc530198072 \h 39
HYPERLINK \l "_Toc530198073" Figure 4 2: WISHBONE Image Control register layout PAGEREF _Toc530198073 \h 39
HYPERLINK \l "_Toc530198074" Figure 4 3: WISHBONE Base Address register layout PAGEREF _Toc530198074 \h 40
HYPERLINK \l "_Toc530198075" Figure 4 4: WISHBONE Address Mask register layout PAGEREF _Toc530198075 \h 41
HYPERLINK \l "_Toc530198076" Figure 4 5: WISHBONE Translation Address register layout PAGEREF _Toc530198076 \h 42
HYPERLINK \l "_Toc530198077" Figure 4 6: PCI Configuration Space Header (Header type 00h) PAGEREF _Toc530198077 \h 43
HYPERLINK \l "_Toc530198078" Figure 4 7: PCI Image0 Base Address register layout Image0 used for accessing the PCI Configuration Space Header (type 00h) PAGEREF _Toc530198078 \h 48
HYPERLINK \l "_Toc530198079" Figure 4 8: PCI Image Control register layout PAGEREF _Toc530198079 \h 48
HYPERLINK \l "_Toc530198080" Figure 4 9: PCI Base Address Register Layout PAGEREF _Toc530198080 \h 49
HYPERLINK \l "_Toc530198081" Figure 4 10: PCI Address Mask register layout PAGEREF _Toc530198081 \h 50
HYPERLINK \l "_Toc530198082" Figure 4 11: PCI Translation Address register layout PAGEREF _Toc530198082 \h 51
HYPERLINK \l "_Toc530198083" Figure 4 12: WISHBONE Error Control and Status register layout PAGEREF _Toc530198083 \h 52
HYPERLINK \l "_Toc530198084" Figure 4 13: PCI Error Control and Status register layout PAGEREF _Toc530198084 \h 54
HYPERLINK \l "_Toc530198085" Figure 4 14: Configuration Address register layout PAGEREF _Toc530198085 \h 56
HYPERLINK \l "_Toc530198086" Figure 4 15: Interrupt Control register layout PAGEREF _Toc530198086 \h 57
HYPERLINK \l "_Toc530198087" Figure 4 16: Interrupt Status register layout PAGEREF _Toc530198087 \h 59
HYPERLINK \l "_Toc530198088" Figure 6 1: WISHBONE configuration Read cycle PAGEREF _Toc530198088 \h 65
HYPERLINK \l "_Toc530198089" Figure 6 2: WISHBONE Configuration Write cycle PAGEREF _Toc530198089 \h 66
HYPERLINK \l "_Toc530198090" Figure 6 3: WISHBONE configuration RMW cycle PAGEREF _Toc530198090 \h 66
HYPERLINK \l "_Toc530198091" Figure 6 4: WISHBONE access to PCI address space PAGEREF _Toc530198091 \h 67
HYPERLINK \l "_Toc530198092" Figure 6 5: PCI Single Read cycle PAGEREF _Toc530198092 \h 68
HYPERLINK \l "_Toc530198093" Figure 6 6: PCI Single Write PAGEREF _Toc530198093 \h 68
HYPERLINK \l "_Toc530198094" Figure 6 7: PCI Burst Read Cycle PAGEREF _Toc530198094 \h 69
HYPERLINK \l "_Toc530198095" Figure 6 8: PCI Burst Write cycle PAGEREF _Toc530198095 \h 69
HYPERLINK \l "_Toc530198096" Figure 6 9: Master Abort termination PAGEREF _Toc530198096 \h 70
HYPERLINK \l "_Toc530198097" Figure 6 10: Timeout termination PAGEREF _Toc530198097 \h 71
HYPERLINK \l "_Toc530198098" Figure 6 11: Target Abort PAGEREF _Toc530198098 \h 71
HYPERLINK \l "_Toc530198099" Figure 6 12: Target Retry PAGEREF _Toc530198099 \h 72
HYPERLINK \l "_Toc530198100" Figure 6 13: Target Disconnect without data PAGEREF _Toc530198100 \h 73
HYPERLINK \l "_Toc530198101" Figure 6 14: Target Disconnect with data PAGEREF _Toc530198101 \h 73
HYPERLINK \l "_Toc530198102" Figure 6 15: PCI Configuration Read cycle PAGEREF _Toc530198102 \h 74
HYPERLINK \l "_Toc530198103" Figure 6 16: PCI Configuration Write cycle PAGEREF _Toc530198103 \h 74
HYPERLINK \l "_Toc530198104" Figure 6 17: PCI Target Read cycle PAGEREF _Toc530198104 \h 75
HYPERLINK \l "_Toc530198105" Figure 6 18: PCI to WISHBONE Read cycle PAGEREF _Toc530198105 \h 75
HYPERLINK \l "_Toc530198106" Figure 6 19: PCI Initiator to Target Burst Read cycle PAGEREF _Toc530198106 \h 76
HYPERLINK \l "_Toc530198107" Figure 6 20: PCI Initiator to Target Burst Write cycle PAGEREF _Toc530198107 \h 76
HYPERLINK \l "_Toc530198108" Figure 6 21: WISHBONE Write transfer caused by PCI to WISHBONE Write cycle PAGEREF _Toc530198108 \h 76
HYPERLINK \l "_Toc530198109" Figure 6 22: Retry on WISHBONE bus caused by PCI to WISHBONE transfer PAGEREF _Toc530198109 \h 77
HYPERLINK \l "_Toc530198110" Figure 6 23: Error on WISHBONE bus caused by PCI to WISHBONE transfer PAGEREF _Toc530198110 \h 77
Introduction
1.1 What is a PCI Bridge?
PCI bridges XE "PCI bridge, introduction:function" are used in applications and devices that want to utilize resources provided on a PCI local bus. Systems that have multiple buses must to enable communication between them provide an interface that connects the internal buses to the PCI local bus. PCI bridges provide such an interface.
1.2 PCI IP Core Introduction
The PCI IP core (PCI bridge) provides an interface between the WISHBONE SoC bus and the PCI local bus. It consists of two independent units, one handling transactions originating on the PCI bus, the other one handling transactions originating on the WISHBONE bus.
The core has been designed to offer as much flexibility as possible to all kinds of applications.
1.3 PCI IP Core Features
The following lists the main features of the PCI IP core:
32-bit PCI interface
Fully PCI 2.2 compliant (with 66 MHz PCI specification)
Separated initiator and target functional blocks
Supported initiator commands and functions:
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
I/O Read, I/O Write
Configuration Read, Configuration Write
Bus Parking
Interrupt Acknowledge
Host Bridging
Supported target commands and functions:
Type 0 Configuration Space Header
(Type 0 is used to configure agents on the same bus segment)
(Type 1 is used to configure across PCI-to-PCI bridges) Parity Generation (PAR), Parity Error Detection (PERR# and SERR#)
Memory Read, Memory Write
Memory Read Multiple (MRM)
Memory Read Line (MRL)
Memory Write and Invalidate (MWI)
I/O Read, I/O Write
Configuration Read, Configuration Write
Target Abort, Target Retry, Target Disconnect
Fast Back-to-Back Capable Target response
Full Command/Status registers
WISHBONE SoC Interconnection Rev. B compliant interface on processor side (master with Target PCI and slave with Initiator PCI interface)
Configurable on-chip FIFOs XE "features, PCI IP core" \r "features"
Architecture
2.1 Overview
The PCI bridge consists of two units: the PCI target unit XE "PCI target unit" XE "PCI bridge, introduction:PCI target unit" and the WISHBONE slave unit XE "PCI bridge, introduction:WISHBONE slave unit" . Each holds its own set of functions to support bridging operations from WISHBONE to PCI and from PCI to WISHBONE. The WISHBONE slave unit acts as a slave on the WISHBONE side of the bridge and initiates transactions as a master on the PCI bus. The PCI target unit acts as a target on the PCI side of the bridge and as a master on its WISHBONE side. Both units operate independently of each other. The PCI target unit implements the target interface on the PCI bus and the master interface on the WISHBONE bus, the WISHBONE slave unit implements the slave interface on the WISHBONE bus and the master interface on the PCI bus.
The PCI interface XE "compliances:PCI interface" is PCI Specification 2.2 compliant, whereas the WISHBONE XE "compliances:WISHBONE" is SoC Interconnection Specification Rev. B compliant. The WISHBONE implementation carries out 32-bit bus operations and does not support other bus widths.
Following figure gives an overview of the PCI bridge core architecture XE "PCI bridge, introduction:architecture" XE "architecture:PCI bridge, general overview" .
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 1: PCI bridge core architecture
2.2 WISHBONE Slave Unit
The WISHBONE bus agents XE "WISHBONE:bus agents" can access the PCI bus through the WISHBONE slave unit XE "WISHBONE:slave unit:function" . One to five configurable images XE "WISHBONE:slave unit:images, configurable" can be used to access the PCI address space.
Each image consists of:
Base address register
Address mask register
Translation address register
Image control register
Decoder
The Base address, stored in the Base Address register, is masked with a value stored in the Address Mask register. The decoder XE "decoder" XE "WISHBONE:slave unit:decoder" compares the WISHBONE bus address with the masked base address to identify valid WISHBONE cycles. If needed, each valid address can be translated to a different value before accessing the PCI bus. The value for an address to be presented on the PCI bus is stored in the Address Translation register. The Image Control register is used to control the behavior of an image.
Each image can be configured to access memory or I/O address space on the PCI bus.
Write cycles through the WB slave unit are processed as Posted Writes XE "write cycles:posted writes" and Read cycles as delayed read XE "read cycles:delayed reads" s. Reads can also be pre-fetched if the image accessed is configured properly. The only exception to that rule is Configuration Write, which is initiated by a special mechanism and therefore described separately in subsequent chapters.
The WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" (WBW_FIFO) is used to post writes performed on the WISHBONE bus; the WISHBONE XE "WISHBONE:slave unit:read FIFO" Read FIFO XE "FIFO:WISHBONE read FIFO" (WBR_FIFO) accumulates pre-fetched reads. The WISHBONE slave unit connects to WISHBONE masters by acting as a slave.
This section describes the architecture of a WISHBONE slave unit and is divided into subsections.
2.2.1 WISHBONE Slave Unit Architecture
The WISHBONE slave unit consists of a few functional parts allowing the WISHBONE master to perform Read/Write access to the PCI bus. The following sections provide detailed descriptions.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 2: WISHBONE slave unit architecture
2.2.1.1 WISHBONE Slave Module
The WISHBONE slave module XE "WISHBONE:slave unit:slave module" , which includes one to six image units for address translation from the WISHBONE bus, is a 32-bit WISHBONE slave interface as defined in WISHBONE Specification Rev. 1B. It handles Read/Write cycles to images of PCI address space and configuration space accesses.
2.2.1.2 WBW_FIFO
The WISHBONE slave module uses WBW_FIFO (WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" ) for posting memory and I/O Write cycles performed by the WISHBONE master. Parameterized depth provides the option to define the WBW_FIFO with regard to application specific needs for posting more or less Write cycles.
The WISHBONE bus determines the speed of Write cycles to the WBW_FIFO, whereas the PCI bus regulates the speed of Write cycles from the WBW_FIFO.
2.2.1.3 WBR_FIFO
The WISHBONE slave module uses WBR_FIFO (WISHBONE Read FIFO XE "FIFO:WISHBONE read FIFO" XE "WISHBONE:slave module:read FIFO" ) for storing data read XE "WISHBONE:slave unit:PCI master module" from PCI targets.
The PCI bus determines the speed of Read cycles to the WBR_FIFO, and the WISHBONE bus regulates the speed of Read cycles from the WBR_FIFO.
2.2.1.4 PCI Master Module
The PCI master module uses information provided by the WISHBONE slave module to perform PCI bus cycles. It is a 32-bit/66MHz (33MHz in FPGA), PCI Local Bus Specification Rev. 2.2 compliant initiator interface. XE "WISHBONE:slave unit:architecture" \r "SlaveUnitWishboneArchitecture" XE "architecture:WISHBONE slave unit" \r "SlaveUnitWishboneArchitecture"
2.3 PCI Target Unit
PCI agents can access the WISHBONE bus through the PCI target unit XE "PCI target unit:function" of the bridge, which provides twoone to six images of the WISHBONE side memory space. Each image is selected XE "PCI target unit:images, selecting" by an address provided during the address phase on the PCI bus. It is compared to the base address masked with a mask value stored in PCI Configuration registers and can be mapped into the memory or I/O space. An address can also be translated to a value stored in the Translation Address register if the image is properly configured.
Write cycles through the PCI target unit are handled as Posted Writes XE "write cycles:posted writes" . Read cycles and can be pre-fetched.
The PCIW_FIFO stores Posted Write XE "write cycles:posted writes" cycles; the PCIR_FIFO saves pre-fetched Read cycles.
2.3.1 PCI Target Unit Architecture
This part describes the architecture of the PCI target unit. The following sections provide detailed descriptions.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 3: PCI target unit architecture overview
The PCI target unit consists of a few functional parts allowing PCI initiators to perform Read/Write accesses to the WISHBONE bus.
The PCI target module is a 32-bit/66MHz (33MHz in FPGA), PCI Local Bus Specification Rev. 2.2 compliant target interface that includes two to six image units for address translation from the PCI bus. Therefore, it handles Read/Write cycles to images of WISHBONE address space and configuration space accesses.
2.3.1.1 PCI Target Module
The PCI target module XE "PCI target unit:target module" uses PCIW_FIFO (PCI Write FIFO XE "FIFO:PCI write FIFO" ) for posting memory and I/O Write cycles performed by the PCI initiator. Parameterized depth provides the option to define the PCIW_FIFO with regard to application specific needs for posting more or less Write cycles.
The PCI bus determines the speed of Write cycles to the PCIW_FIFO, whereas the WISHBONE bus regulates the speed of Write cycles from the PCIW_FIFO.
2.3.1.2 PCIR_FIFO
The WISHBONE master module uses PCIR_FIFO (PCI Read FIFO XE "FIFO:PCI read FIFO" XE "PCI target unit:read FIFO" XE "PCI target unit:read FIFO" ) for storing data read from WISHBONE slaves.
The WISHBONE bus determines the speed of Read cycles to PCIR_FIFO, and the PCI bus regulates the speed of Read cycles from the PCIR_FIFO.
2.3.1.3 WISHBONE Master Module
The WISHBONE master module XE "PCI target unit:WISHBONE master module" is a 32-bit WISHBONE master interface as defined in WISHBONE Specification Rev. 1B. Through its WISHBONE master module, the core sends requests to the WISHBONE bus. Chapter REF _Ref527740890 \h 5.2 WISHBONE Interface, provides detailed information on the WISHBONE interface of the core. XE "PCI target unit:architecture" \r "TargetUnitPCI" XE "architecture:PCI target unit" \r "TargetUnitPCI"
2.4 Clocks
The PCI core has two clock XE "architecture:clocks" XE "clocks" domains, one from the PCI bus, the other one from the WISHBONE bus. With its interconnection logic, the FIFO XE "FIFO:architecture" adjusts the different bus clocks. There is no difference between all four FIFOs, because it is not decisive which bus operates on higher frequency.
2.5 FIFO
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 4: Detailed Description of FIFO XE "FIFO:register lines" Register Lines
The FIFO is structured by more than one line. The number of FIFO lines, which is configurable, determines the depth number (the Design Document and Implementation Notes discuss in detail how FIFO depth is defined). REF _Ref514001600 \h \* MERGEFORMAT Figure 2 4 describes the structure of one FIFO line, which consists of 4 control bits (the Design Document describes in detail how they are usede.g. one bit is used to sign the last data of the burst transfer etc.), 4 command or byte enable bits (coding will be described in detail in the Design Document), and 32 address or data bits.
FIFOs are implemented as circular data buffers between WISHBONE and PCI interfaces ( REF _Ref514006520 \h \* MERGEFORMAT Figure 2 5) and adapt to different bus speeds with their interconnection logic. The input bus clock XE "clocks" , which is also connected to FIFO registers, writes data to the input side of the FIFO. The input pointer (input counter), which has the same clock frequency as the input bus side, stores the value of the input offset address of the first free FIFO line.
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 5: FIFO XE "FIFO:architechture" Architecture
The output pointer (output counter) stores the output offset address value of the first FIFO line from which data is to be read. It has the same clock XE "clocks" frequency as the output bus side that reads the data.
The comparator between both pointers (counters) validates if any data is waiting in the FIFO to be read (the Design Document describes in detail the exact counter/comparator operation). Another comparator is between the counter, which has the value of an input pointer incremented to one, and the output pointer. When both variables are equal, the FIFO is full. XE "FIFO" \r "FIFO" XE "First in First out" \t "See also FIFO" XE "First in First out" \r "FIFO" XE "architecture:FIFO" \r "FIFO"
2.6 Address Translation Logic
WISHBONE slave unit and PCI target unit incorporate several address space images. Each image must have address translation logic ( REF _Ref514007812 \h \* MERGEFORMAT Figure 2 6) including its own set of 32-bit registers XE "address translation logic:registers" :
Base Address register [31:0]
Address Mask register [31:0]
Translation Address register [31:0]
Image Control register [31:0]
2.6.1 Description of Address Translation Logic
For a description of the address translation logic, see REF _Ref514007812 \h \* MERGEFORMAT Figure 2 6. All AND blocks and OR blocks are bit-oriented operators that stand for logic operations between bits of the same weight (e.g. logic function between bit[n-2] of bus A and bit[n-2] of bus B).
The base address is written into the Base Address register. The Address Mask register, which also defines the size of an image, decides how many most significant bits are masked and replaced by translation address bits. There is a rule how to set the Address Mask register XE "address translation logic:address mask register, setting rule" : Address bits that can be masked must start with the MS bit (bit[31]) and continue to the twelfth bit (bit[11]). All bits allowed to be masked define the smallest size of 4KB that can be assigned. No zeros must be between mask bits; otherwise this image will have two base addresses but only one Base Address registera situation that does not comply with the PCI Specification.
To find out if an address falls into the correct address range XE "address translation logic:address range" , the masked bits of input address and base address must be compared (the number of masked bits defines the unchanging address of the current address range and thereby the size of this image).
Figure STYLEREF 1 \s 2 SEQ Figure \* ARABIC \s 1 6: Address Translation Logic XE "address translation logic:architecture" XE "architecture:address translation logic" \r "AddressTranslationLogic"
Operation
3.1 Configuration Space
Depending on core implementation, either the PCI or the WISHBONE agents have full access to configuration space XE "configuration space:access, general" . If the core is implemented as a host bus bridge, the WISHBONE slave unit has exclusive access to this space, whereas the PCI target unit has read-only access (this image can be canceled or changed to normal PCI to WB image). If the core is implemented as a guest (expansion bus bridge), exclusive access to configuration space lies with the PCI target unit and the WISHBONE slave unit has read-only access (this image can also be canceled).
Configuration space XE "configuration space:definition" has a configurable block size and is divided into two partsone intended for Configuration, Control, and Status registers of the WB slave unit, the other one for PCI Target Unit registers. If the core is implemented as a host bus bridge, accessing specific registers in the configuration space from the WISHBONE bus can generate PCI configuration cycles; otherwise, another agent on the PCI bus must perform these cycles. Configuration space is accessible only with Single Read XE "read cycles:single reads" and Single Write XE "write cycles:single writes" cycles (e.g. it cannot be accessed with bursts from the PCI side).
All registers in the configuration space of a core are 32-bits wide with 8-bit granularity. All accesses must be DWORD aligned (e.g. two LS bits of address must be 00). The PCI standard defines special encoding for those two bits used for PCI bus memory access. If any of them are non-zero, the WISHBONE slave module signals a bus error, while PCI target module stops burst after one data is transferred. To access individual bytes, the BE# signals for PCI bus access and the SEL_O signals for WISHBONE bus access must carry an appropriate value.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 1: PCI Bridge Configuration Space
3.1.1 Configuration Space Access for Host Bus Bridges
The cores host bus bridge XE "configuration space:access for host bus bridges" implementation provides two types of access to configuration space: Read/Write access for the WISHBONE slave unit and read-only access for the PCI target unit (unless all 6 PCI Target images 0 areis canceled or used to access the WISHBONE busin which case other PCI device can not read configuration space. See also REF _Ref528224024 \h 3.3.2 Addressing and Images of the PCI Target Unit and REF _Ref528223128 \h 4.1 Register List and Description). Thus, the WISHBONE master takes full responsibility for configuring core registers and any other PCI devices residing on the PCI bus. The WISHBONE side configuration space base address is predefined and cannot be changed once the core has been implemented (the Design Document describes in detail how and where the base address is defined.).
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 2: Configuration space access for Host Bus Bridges
The WISHBONE master can access configuration space either by Single Read XE "read cycles:single reads" , Single Write XE "write cycles:single writes" , or Read Modify Write XE "write cycles:read modify writes (RMW)" (RMW) cycles. If the WISHBONE master attempts a Write cycle to non-implemented space, the cycle is acknowledged by the WISHBONE slave module while Read cycles to non-implemented space return all 0s.
The PCI side configuration space base address must be set by the WISHBONE master. The WISHBONE master must perform a Write cycle to the PCI side configuration space Base Address register to enable read-only access to PCI agents. The PCI target module provides read-only access to configuration space from the PCI bus, supporting Memory Read and Memory Write commands, but ignoring all other commands. The Memory Write command has no effect on Configuration registers. During the first data phase, the PCI target module signals Target Disconnect XE "termination signals:target disconnect with data" with Data to the initiator. Read cycles to non-implemented regions of configuration space return all 0s, whereas Write cycles have no effect.
3.1.2 Configuration Space Access for Guest Bridges
The implementation of the core as a guest bridge XE "configuration space:access for guest bus bridges" (more commonly referred to as expansion bus bridge XE "expansion bus bridges" \t "See guest bus bridges" ) provides two types of configuration space access: Read/Write access for the PCI target unit and read-only access for the WISHBONE slave unit (unless WB slave image 0 is canceled). Other PCI agents take full responsibility for configuring core registers and any other PCI devices residing on the PCI bus. An agent on the PCI bus (most commonly the host bus bridge) sets the PCI side configuration space base address by performing a Type 0 configuration cycle and writing the base address to the PCI configuration space, as stated in the PCI Local Bus Specification Rev. 2.2. The PCI side configuration space Base Address register 0 holds the same value as the first Base Address register in the PCI configuration space Header at offset 0x10. This enables device-independent software to map the bridge configuration space anywhere into the memory address space. After the base address has been set by a Type 0 configuration cycle XE "configuration cycles" and the bridge is in a normal mode of operation, the PCI agent can re-map configuration space anywhere within the memory space by writing to the PCI side configuration space Base Address register 0.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 3: Configuration space access for Guest Bridges
Configuration space access can be provided to the PCI initiator as Memory Read or Memory Write. In case the PCI initiator requests configuration space access by using a different bus command, the PCI target module does not respond. If the PCI initiator attempts an access (Read or Write) to non-implemented space, the initial data phase is terminated by signaling Target Disconnect XE "termination signals:target disconnect with data" with Data XE "termination signals:target disconnect with data" . Write cycles have no effect on non-implemented configuration space, but Read cycles return all 0s.
The WISHBONE slave module provides read-only access to configuration space from the WISHBONE bus. The WISHBONE side configuration space base address is predefined and cannot be changed (the Design Document describes in detail how and where a base address is defined). The WISHBONE slave module accepts Read or Write transfers to configuration space. Write cycles to configuration space have no effect on Configuration Space registers. When the WISHBONE master attempts to access a non-implemented region, Write cycles are acknowledged with no effect on configuration space, but Read cycles return all 0s.
3.1.3 Configuration Cycles
Configuration cycles XE "configuration cycles:access to configuration space" XE "configuration space:access to configuration cycles" are another way of accessing the configuration space of the core. Only the lower 256 bytes of configuration space are available for Read/Write access with Type 0 configuration cycles for guest (expansion bus) implementation of the core. The host bus bridge implementation provides the Configuration Read operation only. Configuration Write cycles are accepted and acknowledged but have no effect on Configuration registers.
Addressing in configuration cycles is different from normal Read and Write cycles on a PCI bus (For more information, see PCI Local Bus Specification Rev 2.2, chapter 3.1.1, Command Definition).
Only Type 00h predefined header portion has been implemented in the lower 256 bytes of the configuration space (in this document also called PCI configuration space). For its organization, see PCI Local Bus Specification Rev 2.2, chapter 6.1.
3.1.4 Generating Configuration Cycles
The host bus bridge implementation of the core provides a mechanism for generating XE "configuration cycles:generating configuration cycles on a PCI bus by accessing the CNF_ADDR and CNF_DATA register.
Step 1: The WISHBONE master must write the appropriate data to the CNF_ADDR register, which holds information about register offset, function, device, and bus number. The TYPE bit in this register defines a type of configuration cycle that is generated on the PCI bus (0 = Type 0, 1 = Type 1). The Offset field in the CNF_ADDR register identifies a register offset to or from which the WISHBONE master wishes to write or read. The Function field is set to the function number of multifunctional devices being a target of configuration cycles. The Device field, which identifies the address line that drives high for generating the IDSEL signal for a Type 0 configuration cycle, is set to the device number on the PCI bus. The Bus field is set to the bus number the targeted device resides on.
Step 2: To actually begin a configuration cycle on the PCI bus, the WISHBONE master must access the CNF_DATA register. Accesses to CNF_DATA are treated as Single Delayed transactions. The WISHBONE masters access to this register is retried. If it is a Read cycle, the PCI master module arbitrates for the PCI bus, performs the Configuration Read command with byte enables provided by the WISHBONE master (signals SEL_O(3..0)), and provides data on the WISHBONE interface when the WISHBONE master retries the transaction. In case of a Write access, the PCI master module arbitrates for the PCI bus, performs a Write cycle with provided byte enables (signals SEL_O(3..0)), and acknowledges the transaction when retried by the WISHBONE master.
Driving of PCI bus AD lines during the configuration cycle address phase depends on the TYPE of the configuration cycle. If the WISHBONE master sets the TYPE bit of CNF_ADDR to 1 (indicating Type 1 configuration cycle), the value of lines on the PCI bus is driven with contents of the CNF_ADDR register (AD[31..0] <= CNF_ADDR[31..0]) during address phase. If the TYPE bit indicates TYPE 0 configuration cycle, then AD[31..11] lines on the PCI bus are driven according to the following table (driving depends on the Device field in the CNF_ADDR register):
DEVICE field valueValue on AD[31..11] lines during address phase of configuration cycle0000 00000 0000 0000 0000 0000 10000 10000 0000 0000 0000 0001 00001 00000 0000 0000 0000 0010 00001 10000 0000 0000 0000 0100 00010 00000 0000 0000 0000 1000 00010 10000 0000 0000 0001 0000 00011 00000 0000 0000 0010 0000 00011 10000 0000 0000 0100 0000 00100 00000 0000 0000 1000 0000 00100 10000 0000 0001 0000 0000 00101 00000 0000 0010 0000 0000 00101 10000 0000 0100 0000 0000 00110 00000 0000 1000 0000 0000 00110 10000 0001 0000 0000 0000 00111 00000 0010 0000 0000 0000 00111 10000 0100 0000 0000 0000 01000 00000 1000 0000 0000 0000 01000 10001 0000 0000 0000 0000 01001 00010 0000 0000 0000 0000 01001 10100 0000 0000 0000 0000 01010 01000 0000 0000 0000 0000 01010 10000 0000 0000 0000 0000 01011 00000 0000 0000 0000 0000 01011 10000 0000 0000 0000 0000 01100 00000 0000 0000 0000 0000 01100 10000 0000 0000 0000 0000 01101 00000 0000 0000 0000 0000 01101 10000 0000 0000 0000 0000 01110 00000 0000 0000 0000 0000 01110 10000 0000 0000 0000 0000 01111 00000 0000 0000 0000 0000 01111 10000 0000 0000 0000 0000 0Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 1: Value XE "field values, configuration cycles" \r "FieldValues" on AD[31:11] PCI bus lines during address phase of configuration cycle Type 0 XE "configuration cycles:field values" \r "FieldValues"
Specified driving of PCI bus lines AD[31..11] provides a mechanism for tying IDSEL signals of target devices directly to AD lines. This way, device 0 is connected with its IDSEL signal to AD[11], device number 1 to AD[12], until device 20 connects to AD[31]. A total of 21 targets can be accessed with configuration cycles through the PCI bridge. Combinations of Device field values of CNF_ADDR register 10101 through 11111 are valid and terminate Master Abort XE "termination signals:master abort" on the PCI bus since none of the targets can respond to the cycle without its IDSEL signal being asserted. Configuration Write data is discarded while Read cycles return all 1s on the WISHBONE bus. The transaction is acknowledged as specified in PCI Specification Rev. 2.2.
Other AD lines on the PCI bus are driven during the address phase of the Type 0 configuration cycle with data stored in the CNF_ADDR register, as described in PCI Specification Rev. 2.2. XE "configuration cycles" \r "ConfigurationCycles"
3.1.5 Generating Interrupt Acknowledge Cycles
A special mechanism provides the generation of Interrupt Acknowledge cycles XE "interrupt acknowledge cycles:generating" XE "configuration space:interrupt acknowledge cycles" on the PCI bus. The WISHBONE master must perform a Read cycle to the INT_ACK register. This Read cycle is treated as Single Delayed transaction retried until the PCI master module arbitrates for the PCI bus and fetches the data requested. Address and byte enables on the PCI bus are exact copies of ADR_O(31..0) and SEL(3..0). The address has no meaning during an interrupt acknowledge cycle while byte enables indicate the size of the interrupt vector returned.
Read cycles of this register from the PCI bus have no effect and return all 0s. Write cycles from the WISHBONE or PCI side are accepted but have no effect. XE "operation:configuration space" \r "ConfigurationSpace" XE "configuration space" \r "ConfigurationSpace"
3.2 WISHBONE Slave Unit
The WISHBONE slave unit connects to WISHBONE masters acting as a slave. This section describes its basic functionality. It is divided into subsections, each of them describing what the WISHBONE master needs to do to initiate WISHBONE to PCI transactions.
3.2.1 WISHBONE Slave Unit Functionality
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 4: WISHBONE Slave Unit Architecture XE "architecture:WISHBONE slave unit" Overview
The WISHBONE slave unit consists of a few functional parts allowing the WISHBONE master to perform Read/Write accesses to the PCI bus.
3.2.1.1 WISHBONE Slave Module
The WISHBONE slave module XE "WISHBONE:slave unit:slave module" is a 32-bit WISHBONE slave interface as defined in WISHBONE Specification Rev. 1B. It handles Read/Write cycles to images of PCI address space and configuration space accesses.
3.2.1.2 WBW_FIFO
The WISHBONE slave module uses WBW_FIFO (WISHBONE Write FIFO XE "FIFO:WISHBONE write FIFO" XE "WISHBONE:slave unit:write FIFO" ) for posting Memory and I/O Write cycles performed by the WISHBONE master. WBW_FIFO also performs a different bus clock adaptation.
3.2.1.3 WBR_FIFO
The WISHBONE slave module uses WBR_FIFO (WISHBONE Read FIFO XE "FIFO:WISHBONE read FIFO" XE "WISHBONE:slave unit:read FIFO" ) for storing data read from PCI targets. WBR_FIFO also performs a different bus clock adaptation.
3.2.1.4 PCI Master Module
The PCI master module XE "WISHBONE:slave unit:PCI master module" is a 32-bit/66MHz, PCI Local Bus Specification Rev. 2.2 compliant initiator interface. The core requests the PCI bus through its PCI master module and performs bus operations as described in the following subsections. Chapter REF _Ref527745161 \h 5.1 PCI Interface provides a detailed overview of the PCI interface of the core.
3.2.2 Addressing and Images of the WISHBONE Slave Unit
As mentioned before, the WISHBONE slave unit incorporates 1 to 5 configurable WISHBONE address space images XE "WISHBONE:slave unit:images, configurable" (the Design Document and Implementation Notes discuss in detail how the number of images is defined) and one image used for configuration space accesses from the WISHBONE bus with a fixed base address. This fixed base address points to the starting address of the configuration space. The base address for WISHBONE configuration space points to the 0x0 offset address of the whole configuration space and is different from the first Base Address register in the PCI header that is also used for the same configuration space, but different bus (PCI).
The behavior of each image is controlled by its WISHBONE Base Address (W_BA1 W_BA5), WISHBONE Translation Address (W_TA1 W_TA5), WISHBONE Image Control (W_IMG_CTRL1 W_IMG_CTRL5) and WISHBONE Address Mask (W_AM1 W_AM5) registers. Statuses, errors, and interrupts for each image are recorded in the Status registers of an image described later in this document. The WISHBONE slave module claims the cycle initiated by the master on the WISHBONE bus if one of the WISHBONE images is selected and enabled. An image is enabled if the IMG_EN bit of its W_AM register is set to 1. An image is selected when the address provided during the initial cycle on the WISHBONE bus falls into the memory range of that image. The range is determined by values of W_BA and W_AM registers. Each image can represent 4KB to 2GB of PCI address space. Whether an image is mapped to memory or I/O space is determined by the address space-mapping bit (ASM) of the images P_Bax register. If this bit is 0, the image maps to memory space, otherwise to I/0 space.
How to specify a 1MB image of PCI address space with an address range of 0x10100000 - 0x101FFFFF?
The software must write a value of 0x10100XX0 to the images Base Address register (the LSB of this register is set to 0 to indicate a memory space mapping). This way, the base address is set at 0x10100000. Twelve LS bits are marked as Dont Cares. The minimum block size is 4KB. Then, the software writes a value of 0xFFF00XXX into the W_AM register of the corresponding image. The IMG_EN bit is the MS bit and set to a value of 1 (it is also used for address masking i.e. how we limit a maximum image size to 2GB). Each bit in the W_AM register corresponds to one address line if a bit is 1, this address line is used for address comparison, and otherwise it is not. A value of 0xFFF00000 in the W_AM register means that ADDR_O(31..20) signals are compared to W_BA[31..20] values. If values match, the image is selected. In this case, ADDR_O(19..0) lines define an offset in an address range of 1MB.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 1: Address range XE "WISHBONE:slave unit:address range, example" of WISHBONE slave image
If enabled for a selected image (AT_EN bit of W_IMG_CTRLx is 1), address translation is performed between WISHBONE and PCI address by replacing the masked part of a WISHBONE address with the corresponding bits from the W_AT register. This provides very flexible address mapping.
Lets assume that base address and address mask are set as described in the previous example. We want a WISHBONE address range of 0x10100000 0x101FFFFF to be mapped elsewhere on the PCI bus, e.g. 0x01000000 0x010FFFFF. To achieve this, we need a translation of addresses coming from the WISHBONE master and set the AT_EN bit of the corresponding W_IMG_CTRL register to a value of 1 and of the corresponding W_AT register to a value of 0x01000XXX. The W_AM register is already set, so address translation replaces ADDR_O(31..20) provided by the WISHBONE master with a value of 0x010 set in the W_AT register for accesses on the PCI bus. This way, a PCI address range of 0x01000000 0x010FFFFF is accessible on the WISHBONE bus within a range of 0x10100000 0x101FFFFF.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 2: Address translation XE "WISHBONE:slave unit:address translation, example"
3.2.3 WISHBONE to PCI Write Cycles
This section gives a detailed description of Write accesses, assuming that the WISHBONE XE "WISHBONE:slave unit:write cycles to PCI" slave unit has decoded an address to fall within a range of one of its enabled images.
The WISHBONE slave module is capable of handling Single XE "write cycles:single writes" and Block Write transfers XE "write cycles:block writes" through one of its WISHBONE slave images. Read Modify Write XE "write cycles:read modify writes (RMW)" (RMF) cycles are not supported.
Note:
Serial block transfers (bursts) are still under discussion because the WISHBONE Bus Specification does not provide a mechanism to identify them. Until serial block transfers are specified, Block Write XE "write cycles:block writes" cycles will be handled as Single Write cycles XE "write cycles:single writes" . Proposal: It might be good to use an internal signal hardwired to a value indicating non-burst transfers. The definition of bursts in the WISHBONE Specification can be used to indicate whether a block transfer is serial or not. All Write cycles from the WISHBONE master to the PCI bus are handled as Posted Writes XE "write cycles:posted writes" and are acknowledged on the WISHBONE bus immediately after receiving a request (before they are finished on the PCI bus) and stored in WBW_FIFO. Each image can be mapped to I/O or memory space, which is determined by a value of the address space-mapping bit (ASM) the W_BAx register of the corresponding image. If an image maps to I/O space, serial block transfers are not possible and the WISHBONE master receives an error signal. Normal block transfers are possible to I/O and memory space since every data beat in a block is treated as Single Posted Write XE "write cycles:posted writes" cycle.
A Write cycle to an address range occupied by an image that is mapped into memory space must be DWORD-aligned (e.g. ADDR_O(1:0) must be 00), otherwise an error terminates the cycle on the WISHBONE bus.
A Write cycle to an address range occupied by an image that is mapped into I/O space must be byte-aligned. The following table describes valid SEL_O(3:0) encoding XE "WISHBONE:slave unit:encoding" XE "encoding" for different values on ADDR_O(1:0).
Value on ADDR_O(1:0) linesValid SEL_O(3:0) encoding00SEL_O(0) must be active01SEL_O(1) must be asserted, SEL_O(0) cannot be asserted10SEL_O(2) must be asserted, SEL_O(1:0) cant be asserted11SEL_O(3) must be asserted, SEL_O(2:0) cannot be assertedTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 2: Valid ADDR_O(1:0) and SEL_O(3:0) combinations for I/O mapped address space access
All other combinations are invalid. An invalid access is terminated with Error XE "termination signals:error" on the WISHBONE bus.
In some cases, Write cycles initiated by the WISHBONE master cannot be accepted and are terminated with Retry XE "termination signals:retry" :
WBW_FIFO is full or does not have enough space left to accommodate another transfer.
An uncompleted Delayed Read XE "read cycles:delayed reads" request is still pending in a WISHBONE slave unit (Write cycles cannot be posted until a Read cycle finishes on the PCI bus).
The PCI master module requests a PCI bus after a complete transaction has been stored in the WISHBONE slave unit WBW_FIFO. After the PCI bus has been granted to the PCI master module, it initiates a transaction on the PCI bus. The module uses Memory Write or I/O Write PCI bus commands, depending on the value of the address space-mapping bit (0 = memory, 1 = I/O) of the image W_BAx register. In case the WISHBONE master posted a serial Block Write XE "write cycles:block writes" cycle, the PCI master module performs a burst of the same length to the PCI target. Single Posted Write XE "write cycles:posted writes" cycles or non-serial Block Write XE "write cycles:block writes" cycles are completed as Single Write XE "write cycles:single writes" cycles on the PCI bus. If the PCI bus arbiter revokes mastership from the PCI master module (#GNT is deasserted), it finishes the current cycle and releases the PCI bus for which it afterwards has to re-arbitrate in order to continue any Posted Write XE "write cycles:posted writes" cycles left in a WBW_FIFO. The core handles Retry XE "termination signals:retry" and Target Disconnect XE "termination signals:target disconnect" terminations by retrying the transaction until it completes or some other termination is signaled.
Because all Write cycles are posted to and are therefore immediately acknowledged by the WISHBONE master, there is an alternate way of communicating errors signaled on the PCI bus when Posted Write XE "write cycles:posted writes" cycles have already been written to their final destination: Error Reporting registers provide an Error Reporting mechanism. Error Reporting must be enabled by the errors enable (ERR_EN) bit of the WISHBONE Error Control and Status (W_ERR_CS) register. When enabled, errors can generate interrupts if the error interrupt enable (EINT_EN) bit of the W_ERR_CS register is 1. Each of the Error Reporting registers stores a part of information about the Posted Write XE "write cycles:posted writes" transaction on the PCI that was terminated with an error.
A value of 1 in the error signaled bit (ERR_SIG) of the W_ERR_CS register indicates that an error has been recorded. The Field Bus Command (BC) of this register stores a bus command used for an access that has been terminated with Error XE "termination signals:error" , while field Byte Enables (BE) stores the value of byte enables during the transfer. The error source bit (ES) indicates the source of an error (1 = Master (Master Abort XE "termination signals:master abort" ), 0 = Target (Target Abort XE "termination signals:target abort" )).
W_ERR_ADDR stores a 32-bit address that the PCI master module tried to access when the error occurred.
W_ERR_DATA stores 32 bits of data used in a transfer that was terminated with an error.
Error XE "termination signals:error" terminated write transactions are discarded while other posted transactions proceed normally. XE "WISHBONE:slave unit:write cycles to PCI" \r "WriteCyclesToPCI" XE "write cycles:WISHBONE to PCI" \r "WriteCyclesToPCI" XE "WISHBONE:slave unit:error reporting mechanism" \r "ErrorReportingWISHBONE"
3.2.4 WISHBONE to PCI Read Cycles
Read cycles initiated by the WISHBONE XE "WISHBONE:slave unit:read cycles to PCI" master are handled as Single Delayed Read XE "read cycles:delayed reads" cycles. Multiple Delayed Read XE "read cycles:delayed reads" cycles are not supported. Delayed transactions must be completed on the PCI bus before they can be completed on the WISHBONE bus. The section on addressing and images has described how the WISHBONE slave unit decodes addresses to know if it is a slave for a current cycle. Handling of Read transactions is encoded in the Image Control register (W_IMG_CTRLx). There are a few options how to define the behavior of the WISHBONE slave unit during Read transactions for images mapped to memory space XE "WISHBONE:slave unit:images mapped to memory space" :
The PREF_EN bit indicates that the address range of an image is prefetchable, which means that the bridge core can pre-fetch data from the target and store it in WBR_FIFO. This method increases the system performance since a Delayed Read XE "read cycles:delayed reads" transaction only knows the starting address of the transfer.
The MRL_EN bit indicates that the PCI master module is free to use the Memory Read Line bus command for Burst Read XE "read cycles:burst reads" cycles.
When both PREF_EN and MRL_EN bits are set, the bridge will use the Memory Read multiple bus command on the PCI bus.
Images mapped to I/O space XE "WISHBONE:slave unit:images mapped to I/O space" handle any Read transaction as single Delayed Read XE "read cycles:delayed reads" cycle (not as Burst Read cycle). If the WISHBONE master attempts to perform a serial Block Read XE "read cycles:block reads" cycle from an I/O space mapped image, the cycle is terminated with an error by the WISHBONE slave module.
The bridge core performs pre-fetched Read cycles only through images mapped to memory space. Prefetchable address space is assumed only when the PREF_EN bit or MRL_EN bit of the corresponding W_IMG_CTRLx register is set, and the WISHBONE master signals a serial Block Read XE "read cycles:block reads" cycle.
Non-prefetchable address space XE "WISHBONE:slave unit:address space, non-prefetchable" is assumed for the following conditions:
Accesses to I/O mapped address space are always non-prefetched.
The WISHBONE master performs a Single or Block Read XE "read cycles:block reads" cycle, or the PREF_EN bit is cleared.
When the WISHBONE slave unit latches address and SEL(3:0) data of a Read request, the PCI master module requests mastership for the PCI bus. When mastership is granted, the PCI master module initiates a PCI Read transaction. The bus command used for the transaction depends on various parameters described in the following table:
Address space mapping of imageCycle initiated by WISHBONE masterPREF_EN bit valueMRL_EN bit valueBus command usedI/OSingle or Block ReadXXI/O Read MemorySingle or Block ReadXX
Memory Read
Serial Block Read00Memory Read01Memory Read Line10Memory Read11Memory Read MultipleTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 3: Bus command encoding XE "encoding" XE "WISHBONE:slave unit:encoding" for Read cycles through PCI master module
Read cycles to address space that is not prefechable are performed in one data phase on the PCI bus. Only those byte enables are active on the PCI bus, as SEL(3:0) data were active during the Read request. After the first data phase, the PCI master module releases the PCI bus.
All Delayed Read XE "read cycles:delayed reads" s from address space marked as prefetchable are performed in Burst Read XE "read cycles:burst reads" cycles. Here are all byte enables active on the PCI bus, since PCI bridge can not determine, which bytes are significant for a WB device, that initiated the transaction (SEL(3:0) data were active during the Read request only for first data phase). The PCI master module reads data from the target and puts it into WBR_FIFO. The PCI master module finishes a Burst Read XE "read cycles:burst reads" cycle and releases the PCI bus if any of the following conditions is met:
WBR_FIFO is full.
The target issues Target Disconnect XE "termination signals:target disconnect" .
The mastership of the PCI bus is revoked by the PCI arbiter (#GNT is de-asserted).
When the WISHBONE master retries this Read transaction, data is ready and the WISHBONE slave module pulls data out of the WBR_FIFO and provides it on the WISHBONE bus.
Any data left in WBR_FIFO after the WISHBONE master ends a Read cycle is flushed immediately.
So far, WISHBONE to PCI Read cycles have been described as if always completed successfully, but it is common for PCI bus targets or masters to generate error terminations. Terminations from the PCI bus must be propagated to the WISHBONE bus to let the WISHBONE master know what happened to the transaction it initiated.
The PCI target is capable to operate the following terminations XE "PCI target unit:termination signals" :
Retry XE "termination signals:retry"
Disconnect XE "termination signals:disconnect with data" with data
Disconnect XE "termination signals:disconnect without data" without data
Target Abort XE "termination signals:target abort"
The Retry XE "termination signals:retry" termination is not propagated back to the WISHBONE bus. The bridge core simply retries the transaction.
Disconnect XE "termination signals:disconnect" is a valid termination for Single Read XE "read cycles:single reads" cycles. The PCI master module does not retry these transactions but stores data for Single Read XE "read cycles:single reads" cycles and waits for the WISHBONE master to fetch it.
Target Abort XE "termination signals:target abort" is an error signaled to the WISHBONE master. Retrying the transaction, it receives a bus error termination (the WISHBONE slave module asserts ERR_I).
Master Abort XE "termination signals:master abort" is an error termination. The WISHBONE master receives an error when a transaction ends with Master Abort XE "termination signals:master abort" on the PCI bus. The only exception to this rule is a Configuration Read cycle, which returns all 0s. XE "operation:WISHBONE slave unit" \r "SlaveUnitWishboneOperation" XE "WISHBONE:slave unit:operation" \r "SlaveUnitWishboneOperation" XE "WISHBONE:slave unit:read cycles to PCI" XE "read cycles:WISHBONE to PCI" \r "WriteCyclesToPCI"
Block Read length can be of Cache Line size or WBR_FIFO depth. It is the WBR_FIFO depth if Memory Read Multiple bus command is performed on the PCI bus (see REF _Ref71325 \h Table 3 3, when this command is performed). But there is NO Block Read if Cache Line size is set to 1 or it is set to unsupported value (valid Cache Line sizes are multiples of 4 - see chapter 4.1.2).
3.3 PCI Target Unit
The PCI target unit connects to PCI initiators acting as a target. This section describes the basic functionality XE "PCI target unit:basic functionality" of the PCI target unit and is divided into subsections, each of them defining what a PCI initiator needs to do to initiate PCI to WISHBONE transactions.
3.3.1 PCI Target Unit Functionality
This part gives a functional overview of the PCI target unit. Detailed description is provided in the following sections.
Figure STYLEREF 1 \s 3 SEQ Figure \* ARABIC \s 1 5: PCI target unit architecture overview XE "architecture:PCI target unit" XE "PCI target unit:architecture"
The PCI target unit consists of several functional parts allowing PCI initiators to perform Read/Write access to the WISHBONE bus.
3.3.1.1 PCI Target Module
The PCI target module XE "PCI target unit:target module" is a 32-bit/66MHz (33MHz for FPGA implementation) PCI Local Bus Specification Rev. 2.2 compliant target interface. It handles Read/Write cycles to images of WISHBONE address space and configuration space accesses.
3.3.1.2 PCIW_FIFO
The PCI target module uses PCIW_FIFO (PCI Write FIFO XE "FIFO:PCI write FIFO" XE "PCI target unit:write FIFO" ) for posting Memory and I/O Write cycles performed by the PCI initiator. PCIW_FIFO also performs a different bus clock adaptation.
3.3.1.3 PCIR_FIFO
The WISHBONE master module uses PCIR_FIFO (PCI Read FIFO XE "FIFO:PCI read FIFO" XE "PCI target unit:read FIFO" ) for storing data read from WISHBONE slaves. PCIR_FIFO performs a different bus clock adaptation.
3.3.1.4 WISHBONE Master Module
The WISHBONE master module XE "PCI target unit:WISHBONE master module" is a 32-bit WISHBONE master interface as defined in WISHBONE Specification Rev. 1B. The core requests the WISHBONE bus through its WISHBONE master module. Chapter REF _Ref527749431 \h 5.2 WISHBONE Interface, describes in detail the WISHBONE interface of the core.
3.3.2 Addressing and Images of the PCI Target Unit
As mentioned above, the PCI target unit incorporates 1 to 5 configurable PCI address space images XE "PCI target unit:images, configurable" (The Design Document and Implementation Notes discuss in detail how to define the number of images) and one special image used for configuration space accesses from the PCI bus with a configurable base address. In host bridge implementations, this special image can be configured to provide access to normal address space or can be canceled therefore configuration space would not be accessible (see also REF _Ref528223750 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528223783 \h 4.1 Register List and Description).
The behavior of each image is controlled by its PCI Base Address (P_BA0 P_BA5), PCI Translation Address (P_TA0 P_TA5), PCI Image Control (P_IMG_CTRL0 P_IMG_CTRL5), and PCI Address Mask (P_AM0 P_AM5) registers. Status, errors, and interrupts for each image are recorded in the Status registers described later in this document. The PCI target module claims the cycle started by the initiator on the PCI bus if one of the PCI images is selected and enabled. An image is enabled if the IMG_EN bit of its P_AM register is set to 1. An image is selected when the address provided during the initial cycle on the PCI bus is placed within the memory range of that image. The range is determined with values of P_BA and P_AM registers. Each image can represent 4KB to 2GB of the WISHBONE address space.
Each image can be mapped to memory or I/O space, determined by the address space-mapping bit (ASM) of the images P_BAx register (bit 0). If the ASM bit is 0, the image maps to memory space, and otherwise to I/O space. For host bridge implementations, the predefined values can later be changed by writing an appropriate value, but for guest bridge implementations, the predefined values are fixed (hardwired), because device independent software must know in advance where to map each PCI Base Address.
How to specify a 1MB image of WISHBONE address space with an address range of 0x10100000 0x101FFFFF?
Software must write a value of 0x10100XX0 to the Base Address register of an image (the LSB of this register is set to 0 to indicate memory space mapping). This way, the base address is set at 0x10100000. Twelve LS bits are marked as Dont Cares. The minimum block size is 4KB.Software writes a value of 0xFFF00XXX into the P_AM register of the corresponding image. The MS bit is the IMG_EN bit, which is set to a value of 1. It is also used for address masking, i.e. how we limit a maximum image size to 2GB. Each bit in the P_AM register corresponds to one address line. If the bit is 1, then this address line is used in address comparison, and otherwise it is not. A value of 0xFFF00000 in the P_AM register means that ADDR_O(31..20) signals are compared with a P_BA[31..20] value. If values match, the image is selected. In this case, ADDR_O(19..0) lines define an offset in an address range of 1MB.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 3: Address range XE "PCI target unit:address range, example" of WISHBONE slave image
If address translation is enabled for a selected image (AT_EN bit of P_IMG_CTRLx is 1), it is performed between PCI and WISHBONE address. Address translation is done by replacing the masked part of the PCI address with the corresponding bits from the P_AT register. This provides very flexible address mapping (off course address translation must be implemented).
Lets assume that base address and address mask are set as described in previous example. We want a PCI address range of 0x10100000 0x101FFFFF to be mapped elsewhere on the WISHBONE bus, e.g. at 0x01000000 0x010FFFFF. To achieve this, we need a translation of addresses coming from the PCI initiator. The AT_EN bit of the corresponding IMG_CTRL register is set to a value of 1 and of the corresponding P_AT register to a value of 0x01000XXX, respectively. The P_AM register is already set, so address translation replaces AD(31..20) provided by the PCI initiator with a 0x010 value set in the P_AT register for accesses on the WISHBONE bus. This way, we have a WISHBONE address range of 0x01000000 0x010FFFFF, accessible on the PCI bus in a range of 0x10100000 0x101FFFFF.Example STYLEREF 1 \s 3 SEQ Example \* ARABIC \s 1 4: Address translation XE "PCI target unit:address translation, example"
3.3.3 PCI to WISHBONE Write Cycles
The previous section described how a PCI target unit knows if it is the target of a current cycle initiated by a PCI initiator. In this section, Write accesses are described in detail, assuming that a PCI target unit decodes an address to fall within a range of one of its enabled images.
The PCI target module is capable of handling Single XE "write cycles:single writes" and Burst Write transfers through one of its PCI target images.
Note:
Serial block transfers (bursts on the WISHBONE bus) are still under discussion because the WISHBONE Bus Specification does not provide a mechanism to identify them. Until serial block transfers will be specified, all bursts from the PCI bus are handled as Block Write XE "write cycles:block writes" cycles.
All Write cycles from the PCI master to the WISHBONE bus are handled as Posted Writes XE "write cycles:posted writes" . Due to this, the Read Modify Write command is not supported on the WISHBONE bus. Write cycles are claimed on the PCI bus immediately after receiving a request and are stored in PCIW_FIFO. Each image can be mapped to I/O or memory space that is determined by a value of the address space-mapping bit (ASM) in the P_BAx register of the corresponding image (for guest bridges ASM bit is fixed, for host bridges ASM bit can be changed, see chapter 3.3.2).
If an image maps to I/O space, all 32 AD lines are used for full byte address decoding, and AD(1:0) lines indicate the least significant valid byte for the transaction. The byte enable lines BE#(3:0) indicate the size of the transfer within the DWORD. They must be consistent with AD(1:0) as seen in REF _Ref514473566 \h \* MERGEFORMAT Table 3 5. All other combinations are invalid. Invalid access is terminated with Target Abort XE "termination signals:target abort" on the PCI bus.
All PCI bursts to I/O space are treated as Single Posted Write XE "write cycles:posted writes" s; therefore, Burst transfers are broken into single transfers. Their data phase is terminated with Target Disconnect XE "termination signals:target disconnect with data" with Data. The PCI initiator then attempts to perform the next access with the data following the first transfer. This is repeated until the burst transfer has finished.
Value on AD(1:0) linesStarting ByteValid BE#(3:0) encoding XE "PCI target unit:encoding" XE "encoding" 00Byte 0xxx001Byte 1xx0110Byte 2x01111Byte 30111Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 4: Valid AD(1:0) and BE# (3:0) combinations for I/O mapped address space accesses XE "PCI target unit:address space access:I/O mapped"
If an image maps to memory space, 30 AD lines (the AD(31:2) bus) provide a DWORD-aligned address. The AD(1:0) lines are not part of the address decoded, but they indicate the order in which the PCI initiator requests data to be transferred, as seen in REF _Ref514473566 \h \* MERGEFORMAT Table 3 5. The Linear Incrementing Burst mode is fully supported, while the Cache-line Wrap mode is broken into single transfers whose data phase is terminated with Target Disconnect XE "termination signals:target disconnect with data" with Data. The PCI initiator then attempts to perform the next access with the data following the first transfer. This is repeated until the Cache-line Wrap mode burst transfer has finished.
Value on AD(1:0) linesBurst Ordering encoding XE "PCI target unit:encoding" XE "encoding" 00Linear Incrementing01Reserved (disconnect after first data phase)10Cache-line Wrap mode11Reserved (disconnect after first data phase)Table STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 5: Burst Ordering combinations for memory mapped address space accesses XE "PCI target unit:address space access:memory mapped"
All other combinations are reserved (because of an earlier version of the PCI Specification). Therefore, accesses must be terminated with Disconnect XE "termination signals:disconnect" after the first data phase, but requested memory address space is not affected. There are additional reasons for the PCI target to terminate a current bus-cycle.
When the PCI target unit is unable to respond within its subsequent latency requirement, it terminates a transfer with Disconnect XE "termination signals:disconnect with/without data" with/without Data while data is being transferred, or immediately afterwards, on the initial data phase. This applies to the following conditions:
The target is not capable of doing a burst (as mentioned above).
The target is temporarily unable to continue bursting when PCIW_FIFO is already fulfilled with the current Burst Write XE "write cycles:burst writes" .
The PCI target unit abnormally terminates a transfer with Target Abort XE "termination signals:target abort" when it detects a fatal error of the following kind (otherwise it would not be able to complete the requested transfer):
The master initiates a non-valid combination of AD(1:0) and BE#(3:0) when accessing I/O mapped image space (as mentioned above).
When it is busy and temporarily unable to process the transaction, the PCI target unit terminates a transfer with Retry XE "termination signals:retry" before any data is transferred. This applies to the following situations:
An internal resource conflict emerges when PCIW_FIFO is full or cannot provide enough space to accommodate another burst transfer.
The target is locked by another master when an uncompleted Delayed Read XE "read cycles:delayed reads" request is still pending in a PCI target unit (Write cycles cannot be posted until a Read cycle finishes on the WISHBONE bus).
The target is locked by WBU, when there is still a WB to PCI delayed read pending or processing.
All PCI bus transfer terminations described above are PCI target terminations, but masters may also terminate transactions.
Regardless whether image mapping occurs to MEMORY or I/O space, the PCI initiator or target can insert wait cycles into the current Write transfer.
The PCI target module must perform address decoding every time the PCI initiator induces a Write transfer in order to determine if this transfer is related to it. The WISHBONE master module initiates a transaction on the WISHBONE bus after a complete transaction has been stored in the PCIW_FIFO unit of the PCI target. The module uses Single Write XE "write cycles:single writes" or Block Write XE "write cycles:block writes" transfers, depending on the value of the control bit in the PCIW_FIFO line that indicates a burst from the PCI bus. Block Write XE "write cycles:block writes" cycles on the WISHBONE bus have the same length as bursts from the PCI. If a burst on the PCI bus was cut because of smaller PCIW_FIFO depth, the block size is as large as the size of the burst written into the PCIW_FIFO. When a PCI initiator completes a Burst Write XE "write cycles:burst writes" cycle with the next access, it is treated as a new burst transfer written to PCIW_FIFO.
Because all Write cycles are posted and therefore immediately claimed by the PCI Target module and stored to the PCIW_FIFO, there is an alternate way of communicating errors signaled on a WISHBONE bus when Posted Write XE "write cycles:posted writes" cycles actually have been written to their final destinationthe mechanism of Error Reporting, which is provided through Error XE "termination signals:error" Reporting registers. The error enable bit (ERR_EN) of the PCI Error XE "termination signals:error" Control and Status register (P_ERR_CS) must enable this mechanism. If Error XE "termination signals:error" Reporting is enabled, errors can generate interrupts when the error interrupt enable bit (EINT_EN) of the P_ERR_CS register is 1. Each Error XE "termination signals:error" Reporting register stores part of the information about the Posted Write XE "write cycles:posted writes" transaction on the WISHBONE bus that was terminated with an error.
A value of 1 in the error signaled bit (ERR_SIG) of the P_ERR_CS register indicates that an error has been recorded. The Field Bus Command (BC) of this register stores the bus command used on the PCI bus for the access that terminated with an error on the WISHBONE bus while the field Byte Enables (BE) stores the value of byte enables (SEL_O(3:0) lines) during the transfer.
P_ERR_ADDR stores the 32-bit address the WISHBONE master module tried to access when the error occurred.
P_ERR_DATA stores the 32 bits of data used in the transfer on the WISHBONE bus that terminated with an error.
Only the Write transaction that generated an error is discarded, any subsequent transactions are processed normally. XE "PCI target unit:write cycles to WISHBONE" \r "WriteCyclesToWISHBONE" XE "write cycles:PCI to WISHBONE" \r "WriteCyclesToWISHBONE" XE "PCI target unit:error reporting mechanism" \r "ErrorReportingPCI"
3.3.3.4 PCI to WISHBONE Read Cycles
Read cycles induced by the PCI initiator are handled as Single Delayed Read XE "read cycles:delayed reads" cycles. This explains why the Read Modify Write command on the WISHBONE bus as well as Multiple Delayed Read XE "read cycles:delayed reads" cycles are not supported. Delayed transactions must be completed on the WISHBONE bus before they can complete on the PCI bus.
Above, the section on addressing and images described how the PCI target unit decodes an address to find out if it is the target for a current cycle. Handling Read transactions is encoded in the PCI Image Control register (P_IMG_CTRLx). To define the PCI target units behavior towards images mapped to memory space XE "PCI target unit:images mapped to memory space" during Read transactions, several options exist:
The PREF_EN bit indicates that the address range of the PCI memory image is prefetchable, which means that the bridge core can pre-fetch data from the slave and store it in WBR_FIFO. This method increases system performance since the Delayed Read XE "read cycles:delayed reads" transaction has information on starting address of the transfer only. Read below REF _Ref68697 \h Table 3 6 for valid byte enables information.
Images mapped to I/O space XE "PCI target unit:images mapped to I/O space" handle any Read transaction as Single Delayed Read XE "read cycles:delayed reads" cycle (no bursts). If the PCI initiator attempts a Burst Read XE "read cycles:burst reads" cycle from an image mapped to I/O space, the cycle is terminated with Disconnect XE "termination signals:disconnect with data" with Data; thus the initiator can continue reading the rest of the data (by disconnecting the bursts).
The bridge core performs pre-fetched Reads only through images mapped to memory space. Prefetchable address space is assumed for the following conditions:
The PREF_EN bit of the corresponding P_IMG_CTRLx register is set (see REF _Ref68697 \h Table 3 6).
Non-prefetchable address space XE "PCI target unit:address space, non-prefetchable" is assumed for the following conditions:
Accesses to I/O mapped address space are always non-prefetched.
The PCI initiator performs a Single Read XE "read cycles:single reads" cycle, and the PREF_EN bit is cleared.
The following table shows PCI bus Read commands that are considered single or block transfers regarding the PREF_EN bit.
Address space mapping of imageBus command initiated by PCI initiatorPREF_EN bit valueUsed cycle by WISHBONE masterI/OI/O ReadXSingle ReadMemoryMemory Read0Single ReadMemory Read1Block ReadMemory Read LineXBlock ReadMemory Read MultipleXBlock ReadTable STYLEREF 1 \s 3 SEQ Table \* ARABIC \s 1 6: Bus command encoding XE "encoding" XE "PCI target unit:encoding" for Read cycles through PCI target module
Non-prefetchable address spaceSingle Read cycles are performed in one data phase on the WISHBONE bus. Only those byte enables (SEL(3:0)) are active on the WB bus, as PCI byte enables were active during the Read request. After the first data phase, the WISHBONE master module releases the WISHBONE bus.
All Delayed Read XE "read cycles:delayed reads" cycles from memory address space marked as prefetchable (and MRL and MRM commands) are performed as Block Read XE "read cycles:block reads" cycles. Here are all byte enables active on the WB bus, since PCI bridge can not determine, which bytes are significant for a PCI device, that initiated the transaction (PCI byte enables were active during the Read request only for first data phase). The WISHBONE master module reads data from the WISHBONE slave and puts it into PCIR_FIFO. It finishes a Block Read XE "read cycles:block reads" cycle and releases the WISHBONE bus if any of the following conditions occurs:
PCIR_FIFO is full.
The WISHBONE slave issues Error XE "termination signals:error" or Retry XE "termination signals:retry" .
When the PCI initiator retries this Read transaction, data is ready and the PCI target module pulls out data from PCIR_FIFO and provides it on the PCI bus. When PCIR_FIFO is empty or the PCI initiator issues the Read cycle of an address that is not one DWORD higher than the previous address within the same block transfer, the PCI target module latches information about a new Read request and terminates the cycle with Retry XE "termination signals:retry" .
Any data left in PCIR_FIFO is flushed immediately.
Until now, PCI TO WISHBONE reads have been described as though all of them are completed successfully, but it is common for WISHBONE bus slaves or masters to generate error terminations. Terminations from the WISHBONE bus must be propagated to the PCI bus in to let the PCI initiator know what happened with the initiated transaction.
Following terminations XE "WISHBONE:slave unit:termination signals" are possible through WISHBONE slaves:
Retry XE "termination signals:retry" , which is not propagated back to the PCI bus. The bridge core simply retries the transaction.
Error XE "termination signals:error" is a termination signaled to the PCI initiator. Retrying the transaction, the PCI initiator receives Target Abort XE "termination signals:target abort" .
There are additional reasons for the PCI target to terminate a current bus cycle.
The PCI target unit terminates XE "PCI target unit:termination signals" a transfer with Disconnect XE "termination signals:disconnect with/without data" with/without Data while data is being transferred, or immediately afterwards, on the initial data phase, when it is unable to respond within its subsequent latency requirement:
The target is not capable of doing a burst (reading from I/O mapped space, as mentioned above).
The target is temporarily unable to continue bursting when PCIR_FIFO is cleared of the current Burst Read XE "read cycles:burst reads" cycle.
The PCI target unit abnormally terminates a transfer with Target Abort XE "termination signals:target abort" (otherwise it will never be able to complete the requested transfer) if the master initiates a non-valid combination of AD(1:0) and BE#(3:0) when accessing the I/O mapped image space.
The PCI target unit terminates a transfer with Retry XE "termination signals:retry" before any data is transferred when it is busy and temporarily unable to process the transaction. An internal resource conflict emerges when PCIR_FIFO is empty.
All PCI bus transfer terminations described above are PCI target terminations, but masters may also terminate transactions.
Regardless whether image mapping occurs to MEMORY or I/O space, the PCI initiator or target can insert Wait cycles into the current Write transfer.
On the other side of the PCI target module, the side of the WISHBONE master unit, the WISHBONE slave can also insert Wait cycles.
Block Read length can be of Cache Line size or PCIR_FIFO depth. It is the PCIR_FIFO depth if Memory Read Multiple bus command was performed on the PCI bus (see REF _Ref68697 \h Table 3 6, for all read command). But there is NO Block Read if Cache Line size is set to 1 or it is set to unsupported value (valid Cache Line sizes are multiples of 4 - see chapter 4.1.2).
3.4 Transaction Ordering
In order to satisfy PCI transaction ordering XE "transaction ordering" rules, the following functionality is implemented:
When the WISHBONE slave unit receives a Read request and no other Delayed Read XE "read cycles:delayed reads" request is pending or waiting to be retried by the WISHBONE master, it latches address and byte enable information and terminates the cycle with Retry XE "termination signals:retry" .
After receiving a Read request, the WISHBONE slave unit locks out any non-configuration space access. (All requests to the WISHBONE slave unit are terminated with Retry XE "termination signals:retry" .)
Posted Write XE "write cycles:posted writes" cycles from WBW_FIFO are processed until WBW_FIFO is empty.
The PCI master module completes a Read cycle on the PCI bus.
When a Read cycle is complete (e.g. when it becomes a Delayed Read XE "read cycles:delayed reads" completion), Posted Write XE "write cycles:posted writes" cycles are accepted again in WBW_FIFO.
The PCI target module retries all non-configuration space accesses from the PCI bus.
All Posted Write XE "write cycles:posted writes" cycles from PCIW_FIFO are completed on the WISHBONE bus until PCIW_FIFO is empty.
The WISHBONE slave unit allows a Read cycle to be completed on the WISHBONE bus.
If the Read cycle not complete, WISHBONE slave and PCI target unit allow the posting of Write cycles. XE "operation:transaction ordering" \r "TransactionOrdering" XE "transaction ordering" \r "TransactionOrdering"
3.5 Parity
Parity monitoring and generation is required by all PCI agents according to the PCI Local Bus Specification. The PCI master module monitors a PAR signal during Read cycles and drives it during Write cycles. The PAR signal provides even parity through C/BE# [3:0] and AD [31:0] lines during address and data phase. If the PCI master performs a Write cycle, the target is responsible for monitoring PAR and asserting PERR# if an error is detected. During Read cycles, the PCI master module monitors PAR and asserts PERR# if an error is detected. If a master detects a parity error during a Read transaction or samples the PERR# signal asserted during a Write transaction, it must set the parity error detected bit in its configuration space Status register.
If the parity error response bit is set, the PCI master module must signal a parity error by asserting the PERR# signal during Read transactions.
When the PERR_INT_EN bit is set, the core signals an interrupt request in an additional response to parity errors, as recommended by the PCI Bus Specification. Parity error detection has no influence on the PCI master moduleit continues the transaction until finished or until terminated by the target. XE "operation:parity" \r "Parity" XE "parity" \r "Parity"
3.6 Interrupts
The PCI IP core is capable of generating interrupts in response to different events. Interrupt Control and Interrupt Status registers control these interrupts. If the core is implemented as a guest bridge, interrupts are reported on the PCI bus through assertion of the INTA# pin; if it is implemented as a host, they are reported on the WISHBONE bus through assertion of the INTA_O pin. The Interrupt Control register is used for enabling/disabling interrupts originating from different sources. The interrupt Status register is used to determine the source of an interrupt and to clear interrupt requests. See chapter 4.1.4 what must be enabled to cause appropriate interrupts and which are implemented.
The software must locate and clear the source of an interrupt request before clearing status bits in a bridge core. When a reported error caused an interrupt, error must be cleared before interrupt. XE "operation:interrupts" \r "Interrupts" XE "interrupts, generating and reporting" \r "Interrupts"
Registers
This section describes all Control and Status registers inside the PCI core, also called configuration space. It consists of the PCI Configuration Space Header (Type 00h) and device specific Configuration Space registers. The Width field specifies the number of bits in the register, Access specifies the valid access types, R/W stands for Read and Write access, and R for Read Only access.
4.1 Register List and Description
NameAddressWidthAccessDescriptionPCI Configuration Space0x000 0x0FFPCI Specification Rev. 2.2 configuration spaceP_IMG_CTRL0*0x10032R/WPCI Image0 Control registerP_BA0*0x010 and 0x10432R/WPCI Image0 Base Address registerP_AM0*0x10832R/WPCI Image0 Address Mask registerP_TA0*0x10C32R/WPCI Image0 Translation Address registerP_IMG_CTRL10x11032R/WPCI Image1 Control registerP_BA10x014 and 0x11432R/WPCI Image1 Base Address registerP_AM10x11832R/WPCI Image1 Address Mask registerP_TA10x11C32R/WPCI Image1 Translation Address registerP_IMG_CTRL20x12032R/WPCI Image2 Control registerP_BA20x018 and 0x12432R/WPCI Image2 Base Address registerP_AM20x12832R/WPCI Image2 Address Mask registerP_TA20x12C32R/WPCI Image2 Translation Address registerP_IMG_CTRL30x13032R/WPCI Image3 Control registerP_BA30x01C and 0x13432R/WPCI Image3 Base Address registerP_AM30x13832R/WPCI Image3 Address Mask registerP_TA30x13C32R/WPCI Image3 Translation Address registerP_IMG_CTRL40x14032R/WPCI Image4 Control registerP_BA40x020 and 0x14432R/WPCI Image4 Base Address registerP_AM40x14832R/WPCI Image4 Address Mask registerP_TA40x14C32R/WPCI Image4 Translation Address registerP_IMG_CTRL50x15032R/WPCI Image5 Control registerP_BA50x024 and 0x15432R/WPCI Image5 Base Address registerP_AM50x15832R/WPCI Image5 Address Mask registerP_TA50x15C32R/WPCI Image5 Translation Address registerP_ERR_CS0x16032R/WPCI Error Control and Status registerP_ERR_ADDR0x16432RPCI Erroneous Address registerP_ERR_DATA0x16832RPCI Erroneous Data registerWB_CONF_SPC_BAR (Base for WISHBONE bus)0x18032RWISHBONE Configuration Space Base AddressW_IMG_CTRL10x18432R/WWISHBONE Image1 Control registerW_BA10x18832R/WWISHBONE Image1 Base Address registerW_AM10x18C32R/WWISHBONE Image1 Address Mask registerW_TA10x19032R/WWISHBONE Image1 Translation Address registerW_IMG_CTRL20x19432R/WWISHBONE Image2 Control registerW_BA20x19832R/WWISHBONE Image2 Base Address registerW_AM20x19C32R/WWISHBONE Image2 Address Mask registerW_TA20x1A032R/WWISHBONE Image2 Translation Address registerW_IMG_CTRL30x1A432R/WWISHBONE Image3 Control registerW_BA30x1A832R/WWISHBONE Image3 Base Address registerW_AM30x1AC32R/WWISHBONE Image3 Address Mask registerW_TA30x1B032R/WWISHBONE Image3 Translation Address registerW_IMG_CTRL40x1B432R/WWISHBONE Image4 Control registerW_BA40x1B832R/WWISHBONE Image4 Base Address registerW_AM40x1BC32R/WWISHBONE Image4 Address Mask registerW_TA40x1C032R/WWISHBONE Image4 Translation Address registerW_IMG_CTRL50x1C432R/WWISHBONE Image5 Control registerW_BA50x1C832R/WWISHBONE Image5 Base Address registerW_AM50x1CC32R/WWISHBONE Image5 Address Mask registerW_TA50x1D032R/WWISHBONE Image5 Translation Address registerW_ERR_CS0x1D432R/WWISHBONE Error Control and Status registerW_ERR_ADDR0x1D832RWISHBONE Erroneous Address registerW_ERR_DATA0x1DC32RWISHBONE Erroneous Data registerCNF_ADDR0x1E032R/WConfiguration Cycle Generation Address registerCNF_DATA0x1E432R/WConfiguration Cycle Generation Data registerINT_ACK0x1E832RInterrupt Acknowledge registerICR0x1EC32R/WInterrupt Control registerISR0x1F032R/WInterrupt Status register* ( All 4 PCI Image0 Control and Address registers are implemented when the PCI bridge is implemented as HOST and all 6 images arePCI Image0 is used to access WB bus or none of all 4 PCI Image0 Control and Address registers are implemented if the PCI bridge is implemented as HOST and PCI Image0 is canceled. Otherwise only the PCI Image0 Base Address register (P_BA0) is implemented on the same offset address and is used for access to the entire Configuration Space (see also REF _Ref528224091 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528224105 \h 3.3.2 Addressing and Images of the PCI Target Unit).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 1: List of registers XE "registers:list of" \r "ListRegisters"
4.1.1 WISHBONE Slave Unit Control & Status
The registers of the WISHBONE slave unit start at offset 0x180 from the base address. The base address is pre-defined during the design phase for WISHBONE bus accesses; the base address for the PCI bus is defined with a configuration cycle for Guest Implementation or with writing to this register by the WISHBONE master for Host Implementation (see also chapter 3.1, Configuration Space).
4.1.1.1 WISHBONE Configuration Space BAR
Bit #AccessResetDescription32R*This register stores the base address to access core registers from the WISHBONE bus. It is read only.* ( Value at reset is defined before implementation in parameter file
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 2: WISHBONE configuration space Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 1: WISHBONE configuration space Base Address register layout
The register is read only. Bits 31 12 define the WISHBONE configuration space base address. Bits 11 0 are always 0 because the minimum image size is 4KB.
4.1.1.2 WISHBONE Image Control and Address Registers
Five configurable WISHBONE slave images can be implemented. Each of these images implements its own set of registers. Image Control and Address registers are the same for all five images.
Image Control registers: W_IMG_CTRL1 - W_IMG_CTRL5
Bit #AccessResetDescription32RW0x00000000The register value controls the WISHBONE slave unit behavior when an image is selected and enabled.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 3: WISHBONE Image Control register
Register layout:
31 240x0023 160x0015 80x007 432100x00AT_ENPREF_ENMRL_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 2: WISHBONE Image Control register layout
Bit descriptions:
Bit #AccessDescription31 3N/ANot used2Address Translation EnableIf this bit is set, address translation for the corresponding image is enabled.1Prefetch enableThis bit marks address space occupied by an image as prefetchable.0Memory Read Line EnableWhen the WISHBONE master performs block read cycles, this bit enables the usage of memory access optimizing commands. If the prefetch-enable bit is also set, read will be performed using Memory Read Multiple command, otherwise the Memory Read Line command will be used.
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 4: WISHBONE Image Control register bit descriptions
Base Address registers: W_BA1- W_BA5
WidthAccessResetDescription32RW0x00000000This register value holds the WISHBONE bus base address of an image.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 5: WISHBONE Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 432100x0000ASMFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 3: WISHBONE Base Address register layout
Bit descriptions:
Bit #AccessDescription31 12Base AddressImage base address. How many bits from this field are compared with ADDR_I(31:0) is defined in the Address Mask register.11-1N/ABecause the minimum block size is 4KB, this field is reserved.0Address Space MappingThis bit defines to which address space an image maps on the PCI bus.
0 Memory space mapping
1 I/O space mappingTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 6: WISHBONE Base Address register bit descriptions
Address Mask registers: W_AM1 W_AM5
WidthAccessResetDescription32RW0x00000000This register value represents an address mask. If the corresponding bit is 1, the address line in the same position is compared with the value in the Base Address register. If the bit is 0, the corresponding address line is not compared with the value in the BA register.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 7: WISHBONE Address Mask register
Register layout:
3130 24IMG_ENAM23 16AM15 1211 8AM0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 4: WISHBONE Address Mask register layout
Bit descriptions:
Bit #AccessDescription31Image Enable & Address Mask (31)This bit must be set to enable an image. If 0, the corresponding image is not enabled. This bit is also used in Address Masking, i.e. how a limit of 2GB per image is implemented (at least ADDR_I(31)) must be compared with BA for each image.30 12Address MaskThe remainder of the Address Mask. If bit(x) of the address mask is 1, ADDR_I(x) is compared with the BA(x) bit in the Base Address register; otherwise it is not. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never compared with the BA register value).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 8: WISHBONE Address Mask register bit descriptions
Translation Address registers: W_TA1 W_TA5
WidthAccessResetDescription32RW0x00000000If address translation is enabled, compared address lines from the WISHBONE bus (specified with AM value) are replaced by corresponding values in this register for PCI bus accesses. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 9: WISHBONE Translation Address register
Register layout:
31 24TA23 16TA15 1211 8TA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 5: WISHBONE Translation Address register layout
Bit descriptions:
Bit #AccessDescription31 12Translation AddressThis register value is used when address translation is enabled. Each value on ADDR_I lines not masked by AM register setting is replaced by the corresponding bit value of the Translation Address register for PCI bus accesses. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never replaced).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 10: WISHBONE Translation Address register bit descriptions XE "registers:WISHBONE slave unit, control & status"
4.1.2 PCI Target Unit Control & Status
Guest bridge implementation always provides R/W access to Configuration space by configuring the Base Address 0 register. Other PCI agents are responsible for this by performing a Type 0 configuration cycle. Host bridge implementation can provide read-only access to Configuration Space or choosecan be set not to do that at all. This way, all six PCI Base Addresses can be used for accessing the WISHBONE address space (see PCI IP Core Design document and chapter A.1, which images are implemented in current design).
Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 6: PCI Configuration Space Header (Header type 00h)
All PCI-compliant devices must support Vendor ID, Device ID, Command, Status, Revision ID, Class Code, and Header Type. The Header Type is type 00h, which defines the header XE "device identification" \t "See configuration space header" XE "identification" \t "See configuration space header" structure of REF _Ref514551570 \* MERGEFORMAT Figure 4 6.
The configuration space header used for device identification includes the following:
Vendor ID XE "configuration space:header:vendor ID" : This field identifies the manufacturer of the device. To ensure uniqueness, the PCI SIG allocates valid vendor identifiers. 0FFFFh is an invalid value for the Vendor ID.
Device ID XE "configuration space:header:device ID" : This field identifies the particular device. It is allocated by the vendor.
Revision ID XE "configuration space:header:revision ID" : This register specifies a device specific revision identifier whose value is chosen by the vendor. An acceptable value is zero. This field should be viewed as a vendor-defined extension to the Device ID.
Header Type XE "configuration space:header:header type" : This byte identifies the layout of the second part of the predefined header (beginning at byte 10h in configuration space) and also whether or not the device contains multiple functions. Bit 7 in this register is used to identify a multi-functional device. If the bit is 0, the device is single-functional. If the bit is 1, it has multiple functions. Bits 6 through 0 identify the layout of the second part of the predefined header.
Class Code XE "configuration space:header:class code" : The Class Code register is read only. It is used to identify the generic function of the device and, in some cases, a specific register-level programming interface (see the PCI 2.2 Specification for detailed description).
The Command register serves device control functions. When 0, the device is logically disconnected from the bus (except for configuration accesses). The following table shows bit descriptions.
Bit #ImplementedDescription15 10Reserved9NOFast Back-to-Back Enable. This optional Read/Write bit controls whether or not a master can do fast back-to-back transactions to different devices. A value of 1 indicates that the master is allowed to generate fast back-to-back transactions to different agents. A value of 0 means that fast back-to-back transactions are allowed only to the same agent. The state after RST# is 0.8 " S E R R # e n a b l e . A v a l u e o f 0 d i s a b l e s t h e S E R R # d r i v e r , a v a l u e o f 1 e n a b l e s i t . T h e s t a t e o f t h i s b i t a f t e r R S T # i s 0 . A d d r e s s p a r i t y e r r o r s a r e r e p o r t e d o n l y i f t h i s b i t a n d b i t 6 a r e 1 . 7 N O S t e p p i n g c o n t r o l . T h i s b i t i s u s e d t o c o n t r o l w h e t h e r o r n o t a d e v i c e d o e s a d d r e s s / d a t a s t e p p i n g . D e v i c e s t h a t n e v e r d o s t e p p i n g m u s t h a r d w i r e t h i s b i t t o 0 . 6 " P a r i t y E r r o r R e s p o n s e . T h i s b i t c o n t r o l s t h e d e v i c e s r e s p o n s e t o p a r i t y e r r o r s . I f s e t , t h e d e v i c e m u s t t a k e i t s n o r m a l a c t i o n w h e n a p a r i t y e r r o r i s d e t ected. If the bit is 0, the device sets its detected parity error status bit (bit 15 in the Status register) when an error is detected but does not assert PERR# and continues normal operation. The state after RST# is 0. 5NOVGA Palette Snoop. This bit controls how VGA compatible devices and graphics devices handle access to the VGA Palette registers. When this bit is 1, palette snooping is enabled (i.e. the device does not respond to Palette Register Write cycles and snoops the data). 4NOMemory Write and Invalidate. This is an enable bit for using the Memory Write and Invalidate command. When this bit is 1, masters may generate the command. When it is 0, Memory Write must be used instead. The state after RST# is 0.3NOSpecial cycles. Controls a devices action on Special Cycle operations. A value of 0 causes the device to ignore all Special Cycle operations. A value of 1 allows the device to monitor Special Cycle operations. The state after RST# is 0.2 " B u s m a s t e r . T h i s b i t c o n t r o l s t h e d e v i c e s a b i l i t y t o a c t a s a m a s t e r o n t h e P C I b u s . A v a l u e o f 0 d i s a b l e s t h e d e v i c e f r o m g e n e r a t i n g P C I a c c e s s e s . A v a l u e o f 1 a l l o w s t h e d e v i c e t o b e h a v e a s a b u s m a s t e r . T h e s t a t e a f t e r R S T # i s 0 . 1 " M e m o r y s p a c e . T h i s b i t c o n t r o l s t h e r e s p o n s e t o m e m o r y s p a c e a c c e s s . A v a l u e o f 0 d i s a b l e s t h e d e v i c e r e s p o n s e . A v a l u e o f 1 a l l o w s r e s p o n d i n g t o m e m o r y s p a c e a c c e s s . T h e s t a t e a f t e r R S T # i s 0 . 0 " I / O s p a c e . T h i s b i t c o n t r o l s t h e r e s p o n s e t o I / O s p a c e a c c e s s . A v a l u e o f 0 disables the device response. A value of 1 allows the device to respond to I/O space access. The state after RST# is 0.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 11: Command register of PCI configuration header
The Status register notes the device status. Reserved bits are read only and return 0 after reading. A 1 bit is reset whenever a 1 is written to a corresponding bit location. The following table provides a description of the corresponding bits.
Bit descriptions:
Bit #ImplementedD e s c r i p t i o n 1 5 " D e t e c t e d P a r i t y E r r o r . T h e d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t d e t e c t s a p a r i t y e r r o r , e v e n i f p a r i t y e r r o r h a n d l i n g i s d i s a b l e d ( a s c o n t r o l l e d b y b i t 6 i n t h e C o m m a n d r e g i s t e r ) . 1 4 " S i g n a l e d S y s t e m E r r o r X E " t e r m i n a t i o n s i g n a l s : s y s t e m e r r o r " . T h i s b i t m u s t b e s e t w h e n e v e r t h e d e v i c e a s s e r t s S E R R # . 1 3 " R e c e i v e d M a s t e r A b o r t X E " t e r m i n a t i o n s i g n a l s : m a s t e r a b o r t " . A m a s t e r d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t s t r a n s a c t i o n ( e x c e p t f o r s p e c i a l c y c l e s ) i s t e r m i n a t e d w i t h M a s t e r A b o r t X E " t e r m i n a t i o n s i g n a l s : m a s t e r a b o r t " . A l l m a s t e r d e v i c e s m u s t i m p l e m e n t t h i s b i t . 1 2 " R e c e i v e d T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . A m a s t e r d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t s t r a n s a c t i o n i s t e r m i n a t e d w i t h T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . 1 1 " S i g n a l e d T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . A t a r g e t d e v i c e m u s t s e t t h i s b i t w h e n e v e r i t t e r m i n a t e s a t r a n s a c t i o n w i t h T a r g e t A b o r t X E " t e r m i n a t i o n s i g n a l s : t a r g e t a b o r t " . 1 0 9 " D E V S E L t i m i n g : 0 0 f a s t ; 0 1 m e d i u m ; 1 0 s l o w . T h e s e b i t s a r e r e a d - o n l y a n d m u s t i n d i c a t e t h e s l o w e s t t i m e t h a t a d e v i c e n e e d s t o a s s e r t D E V S E L # f o r a n y b u s c o m m a n d , e x c e p t C o n f i g u r a t i o n R e a d a n d C o n f i g u r a t i o n W r i t e . 8 " M a s t e r D a t a P a r i t y E r r o r . T h i s b i t i s i m p lemented by bus masters only. It is set when three conditions are met: 1) The bus agent asserted PERR# itself (on a Read cycle) or observed PERR# asserted (on a Write cycle). 2) The agent setting the bit acted as the bus master for the operation during which the error occurred. 3) The parity error response bit (Command register) is set.7 " F a s t B a c k - t o - B a c k C a p a b l e . T h i s o p t i o n a l r e a d o n l y b i t i n d i c a t e s w h e t h e r o r n o t t h e t a r g e t i s c a p a b l e o f a c c e p t i n g f a s t b a c k - t o - b a c k t r a n s a c t i o n s w h e n t h e t r a n s a c t i o n s d o n o t r e f e r t o t h e s a m e a g e n t . 6 R e s e r v e d 5 " 6 6 M H z c a p a b l e . T h i s o p t i o n a l r e a d only bit indicates whether or not this device is capable of running at 66 MHz. A value of 1 indicates that the device is 66 MHz capable.4NOList of compatibilities. A value of zero indicates that no new capabilities linked list is available. A value of one indicates that the value read at offset 34h is a pointer in configuration space to a linked list of new capabilities.3 0-ReservedTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 12: Status register of PCI configuration header
The following descriptions include only miscellaneous (device independent), already implemented registers:
The Cache Line Size register specifies the size of burst reads, except for a Memory Read Multiple command, which size is Read_FIFO depth. Valid values for this register are multiples of 4 (including 1). In invalid value is written (including 0), then the value of 1 is assumed by both WBU and PCIU and no burst reads are performed.
The Latency Timer register specifies the timer value in units of PCI bus clocks. After RST#, the register value is 0.
The Interrupt Line register tells to which input of the system interrupt controller(s) the devices interrupt pin is connected (the Design Document describes in detail how it is implemented).
The Interrupt Pin register tells which interrupt pin the device uses. A value of 1 corresponds to INTA# and so on. The values from 05h to FFh are reserved.
There are 6 Base Address registers, in Configuration space Header. This registers are the same and also accessed in the PCI part of the Configuration space. and eEach one of them consists of a 28-bit base address for MEMORY mapping or a 30-bit base address for I/O mapping. Here are only up to 20 MSBits implemented. Other bits are control bits and described in the following table.
Bit descriptions:
Bit #Description31 4Base address (only the upper 20 bits are valid)3Prefetchable2 1Type: 00 32-bit address space; 01 reserved; 10 64-bit address space; 11 reserved0Memory space indicator = 0 (always for MEMORY mapped space)!!!Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 13: Base Address register of PCI configuration header for memory mapped space
Bit descriptions:
Bit #Description31 2Base address (only the upper 20 bits are valid)1Reserved0I/O space indicator = 1 (always for I/O mapped space)Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 14: Base Address register of PCI configuration header for I/O mapped space
XE "PCI target unit:configuration space header" \r "ConfigurationSpaceHeader" XE "registers:PCI target unit, configuration space header" \r "ConfigurationSpaceHeader" XE "configuration space:header:registers" \r "ConfigurationSpaceHeaderRegisters"
4.1.2.2 PCI Image Control and Address Registers
There are six possible configurable PCI target images. Each of these images implements its own set of registers.
The only exception is the set of 4 PCI Image0 Control and Address registers, which is implemented only when the PCI bridge is implemented as HOST and all 6 imagesImage0 is used to access WB bus are used (see REF _Ref527975562 \h Table 4 16, REF _Ref527975503 \h Table 4 18, REF _Ref527975513 \h Table 4 20 and REF _Ref527975518 \h Table 4 22). Otherwise, there are five possible configurable PCI target images (PCI image1 PCI image5), and only the PCI Image0 Base Address register (P_BA0) is implemented for the PCI image0 on the same offset address and is used for access to the entire Configuration Space (see REF _Ref527976313 \h Table 4 15 and REF _Ref527976348 \h Figure 4 7). The other 3 registers are not implemented and therefore cannot be written to (see also REF _Ref528224163 \h 3.1.1 Configuration Space Access for Host Bus Bridges and REF _Ref528224176 \h 3.3.2 Addressing and Images of the PCI Target Unit).
Base Address Registers: P_BA0
WidthAccessResetDescription32RW0x00000000This register stores the base address for accessing core registers from the PCI bus.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 15: PCI Image0 Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 7: PCI Image0 Base Address register layout Image0 used for accessing the PCI Configuration Space Header (type 00h)
Image Control registers: P_IMG_CTRL0 (P_IMG_CTRL1) P_IMG_CTRL5
WidthAccessResetDescription32RW0x00000000The register value controls the PCI target unit behavior when an image is selected and enabled.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 16: PCI Image Control Register
Register layout:
31 240x0023 160x0015 80x007 432100x00AT_ENPREF_EN0Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 8: PCI Image Control register layout
Bit descriptions:
Bit #NameDescription31 3N/ANot used2Address Translation EnableIf this bit is set, address translation for the corresponding image is enabled.1Pre-fetch enableThis bit marks address space occupied by an image as prefetchable.0N/ANot usedTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 17: PCI Image Control Register bit descriptions
Base Address Registers: P_BA0 (P_BA1) - P_BA5
WidthAccessResetDescription32RW0x00000000The register value holds the PCI bus base address of an image.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 18: PCI Base Address register
Register layout:
31 24BA23 16BA15 1211 8BA0x07 432100x0000ASMFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 9: PCI Base Address Register Layout
Bit descriptions:
Bit #NameDescription31 12Base AddressImage base address. The Address Mask register defines how many bits from this field are compared with ADDR_I(31:0).11-1N/ABecause the minimum block size is 4KB, this field is reserved.0Address Space MappingThis bit defines to which address space an image maps on the PCI bus.
Predefined value can be changed later for HOST bridges.
Predefined value can NOT be changed for GUEST bridges (see chapter 3.3.2 Addressing and Images of the PCI Target Unit).
0 Memory space mapping
1 I/O space mappingTable STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 19: PCI Base Address register bit descriptions
Address Mask registers: P_AM0 (P_AM1) P_AM5
WidthAccessResetDescription32RW0x00000000The register value represents the address mask. If the corresponding bit is 1, the address line in the same position is compared with a value in the Base Address register. If the bit is 0, the corresponding address line is not compared with a value in the BA register.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 20: PCI Address Mask register
Register layout:
3130 24IMG_ENAM23 16AM15 1211 8AM0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 10: PCI Address Mask register layout
Bit descriptions:
Bit #NameDescription31Image Enable & Address Mask(31)This bit must be set for an image to be enabled. If the bit is 0, the corresponding image is not enabled. This bit is also used in Address Masking, i.e. how a limit of 2GB per image is implemented (at least ADDR_I(31) must be compared with BA for each image).30 12Address MaskThis is the remainder of the Address Mask. If bit(x) of the address mask is 1, then ADDR_I(x) is compared with the BA(x) bit in the Base Address Register; otherwise it is not.11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never compared with the BA register value).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 21: PCI Address Mask register bit descriptions
Translation Address registers: P_TA0 (P_TA1) P_TA5
WidthAccessResetDescription32RW0x00000000If address translation is enabled, compared address lines from the PCI bus (specified with AM value) are replaced by corresponding values in this register for WISHBONE bus accesses. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 22: PCI Translation Address register
Register layout:
31 24TA23 16TA15 1211 8TA0x07 00x00Figure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 11: PCI Translation Address register layout
Bits descriptions:
Bit #NameDescription31 12Translation AddressThis register value is used when address translation is enabled. Each value on ADDR_I lines that is not masked by AM register setting is replaced. by the corresponding bit value of the Translation Address register for WISHBONE bus accesses. 11-0N/ABecause the minimum block size is 4KB, this field is always 0x000 (the twelve lower address lines are never replaced).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 23: PCI Translation Address register bit descriptions XE "registers:PCI target unit, control & status"
4.1.3 Reporting Registers
Error Reporting registers are provided because of Posted Write XE "write cycles:posted writes" cycles, which are always acknowledged on the WISHBONE bus before they actually complete on the PCI bus, and vice-versa, so errors detected on PCI or WISHBONE buses cannot be reported back to WISHBONE master or PCI initiator using the standard bus protocol.
4.1.3.1 WISHBONE Slave Unit Error Reporting Registers
WISHBONE Error Control and Status register: W_ERR_CS
WidthAccessResetDescription32RW0x00000000Part of this register is used for controlling the Error Reporting mechanism, another part for reporting statuses and additional information about an error that occurred during the completion of a Posted Write cycle on the PCI bus. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 24: WISHBONE Error Control and Status register
Register layout:
31 2827 24BEBC23 160x0015 121110980x00RTY_EXPESERR_SIG7 432100x0000ERR_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 12: WISHBONE Error Control and Status register layout
Bit descriptions:
Bit #NameDescription31 28Byte EnablesThe field value reports the state of BE# signals used in the Posted Write cycle that terminated with an error.27-24Bus CommandThis field value reports a bus command used for the Posted Write cycle that terminated with an error.16 11N/ANot used10Retry XE "termination signals:retry" Counter ExpiredTHIS BIT IS RESERVED FOR FUTURE USE! Its function is to report that a Posted Write cycle has been retried MAX_RETRY times.9Error XE "termination signals:error" SourceThe ES bit indicates that the master terminated the transaction with Master Abort XE "termination signals:master abort" . Software can distinguish between two kinds of Master Abort XE "termination signals:master abort" terminations the PCI module performs: If the RTY_EXP bit is cleared, Master Abort XE "termination signals:master abort" was performed because no target claimed the transaction; if the RTY_EXP is set, the target signaled too many Retry XE "termination signals:retry" terminations. See description of bit 10!
A cleared ES bit indicates that the target of the transaction signaled Target Abort XE "termination signals:target abort" .8Error XE "termination signals:error" SignaledIf set, this bit indicates that an error has been reported. While this bit is set, all WISHBONE slave unit operation is frozen. Software must clear this bit to enable transactions to resume their path through the WISHBONE slave unit. A bit is cleared by writing 1 to its location.7-1N/ANot used0Error XE "termination signals:error" EnableSetting this bit enables the Error Reporting mechanism. Clearing this bit means that Error Reporting is not performedthe transaction that caused an error is discarded, other transactions continue normally.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 25: WISHBONE Error Control and Status register bit descriptions
WISHBONE Erroneous Address Register: W_ERR_ADDR
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores the address of the transaction on the PCI bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 26: WISHBONE Erroneous Address register
WISHBONE Erroneous Data: W_ERR_DATA
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores data of the transaction on the PCI bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 27: WISHBONE Erroneous Data register XE "WISHBONE:slave unit:error reporting registers" \r "ErrorReportingRegistersWISHBONE"
4.1.3.2 PCI Target Unit Error Reporting Registers
PCI Error Control and Status register: P_ERR_CS
WidthAccessResetDescription32RW0x00000000Part of this register is used for controlling the Error Reporting mechanism, another part for reporting statuses and additional information about an error that occurred during the completion of a Posted Write cycle on the WISHBONE bus. Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 28: PCI Error Control and Status register
Register layout:
31 2827 24BEBC23 160x0015 121110980x00RTY_EXPESERR_SIG7 432100x0000ERR_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 13: PCI Error Control and Status register layout
Bit descriptions:
Bit #NameDescription31 28Byte EnablesThis field value reports the state of byte enable signals SEL_O(3:0) used in the Posted Write cycle that terminated with an error on the WB bus.27-24Bus CommandThis field value reports a bus command from the PCI bus used for a Posted Write cycle that terminated with an error on the WB bus.16 11N/ANot used10Retry XE "termination signals:retry" Counter ExpiredThis bit reports that a Posted Write cycle has been retried MAX_RETRY times or that there was no response on the WISHBONE bus for MAX_RETRY times (internal Retry XE "termination signals:retry" is generated if the WISHBONE slave does not respond for 8 cycles).9Error XE "termination signals:error" SourceThe ES bit indicates that the WISHBONE Master Module of the PCI Target Unit stopped (terminated) the write transaction. The WISHBONE slave signaled too many Retry XE "termination signals:retry" terminations. In this case, the RTY_EXP bit is also set.
A cleared ES bit indicates that the WISHBONE Master Module of the PCI Target Unit was not able to continue the write transaction because of the WISHBONE slave: If the RTY_EXP bit is cleared, the WISHBONE slave signaled an Error XE "termination signals:error" termination; if the RTY_EXP bit is set, the WISHBONE slave did not respond to the initiated transaction.8Error XE "termination signals:error" SignaledIf set, this bit indicates that an error has been reported. The bit is cleared by writing 1 to its location.7-1N/ANot used0Error XE "termination signals:error" EnableSetting this bit enables the Error Reporting mechanism. Clearing this bit means that Error Reporting will not be performed the transaction that caused an error is discarded, other transactions continue normally.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 29: PCI Error XE "termination signals:error" Control and Status register Bit Descriptions
PCI Erroneous Address Register: P _ERR_ADDR
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores the address of the transaction on the WISHBONE bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 30: PCI Erroneous Address register
PCI Erroneous Data: P_ERR_DATA
WidthAccessResetDescription32R0x00000000When Error Reporting is enabled and an error is signaled, this register stores data of the transaction on the WISHBONE bus that caused an error.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 31: PCI Erroneous Data Register XE "PCI target unit:error reporting registers" \r "ErrorReportingRegistersPCI"
4.1.3.3 Configuration Cycle Generation Registers
Two registers are provided for generating configuration cycles on the PCI bus. The WISHBONE master initiates a configuration cycle in two steps:
It writes the appropriate value in the CNF_ADDR register and
Reads cycles from or writes cycles to the CNF_DATA register to generate a Configuration Read or Write cycle respectively.
Configuration address: CNF_ADDR
WidthAccessResetDescription32RW0x00000000This register stores all information needed to drive address lines during the Address phase of a configuration cycle (e.g. it is used within a host PCI device).Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 32: Configuration Address register
Register layout:
31 24Reserved23 16BUS NUMBER15 1110 8DEVICEFUNCTION7 210OFFSET0TYPEFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 14: Configuration Address register layout
Bit descriptions:
Bit #NameDescription31 24N/AA value in this field is ignored for any kind and type of configuration cycle.23 16Bus numberThis field holds a bus number on which a target of the configuration space access resides. It is only used in Type 1 configuration cycles (TYPE bit = 1).15 11Device numberThe value in this field represents a device number. This field is driven directly to AD(15:11) lines during the Address phase for Type1 (TYPE = 1) configuration cycle and is decoded for Type0 configuration cycles (See Table XY for Device number decoding). 10 8Function numberThe value in this field is a function number for multifunctional devices.7 2Register numberThis field holds the register offset for a device addressed with configuration cycle.1N/ANot usedalways 00TypeType of configuration cycle
(0 Type 0, 1 Type 1)Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 33: Configuration Address register bit descriptions
A Read cycle from or a Write cycle to this register will perform a configuration cycle on the PCI bus using information written to the CNF_ADDR register.
Configuration data: CNF_DATA
WidthAccessResetDescription32RW0x00000000This register stores Read or Write data for configuration cycles.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 34: Configuration Data Register XE "configuration cycles:registers" \r "ConfigurationCyclesRegisters"
4.1.3.4 Interrupt Acknowledge Cycle Generation Register
A Read cycle from the INT_ACK register generates an Interrupt Acknowledge cycle XE "interrupt acknowledge cycles:register" on the PCI bus.
WidthAccessResetDescription32R0x00000000This register stores interrupt vector data returned during an Interrupt Acknowledge cycle.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 35: Interrupt Acknowledge register XE "registers:reporting"
4.1.4 Interrupt Control & Status Registers
Interrupt Control register: ICR
WidthAccessResetDescription32RW0x00000000This register is used to enable/disable the generation of interrupt requests from various sources.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 36: Interrupt Control register
Register layout:
313210SW_RST0000x0023 160x0015 80x007 5432100x0SERR_
INT_ENPERR_
INT_ENPCI_
EINT_ENWB_
EINT_ENINT_
PROP_ENFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 15: Interrupt Control register layout
Bit descriptions:
Bit #NameDescription0Interrupt Propagation EnableFor Guest bridge implementation this bit indicates that INT_I line assertion on the WISHBONE bus will generate an interrupt request on the PCI bus through an assertion of the INTA# pin.
For Host bridge implementation this bit indicates that an assertion of the INTA# pin on the PCI bus will generate an interrupt request on the WISHBONE bus through an assertion of the INT_O pin.1WISHBONE Error Interrupt EnableIf set, this bit enables interrupt request generation when an error is signaledREPORTED during the execution of Posted Write cycles through the WISHBONE slave unit. A cleared bit disables these interrupts but does not disable Error Reporting (see bits 0 and 8 of WB Error Control and Status register W_ERR_CS).**2PCI Error Interrupt EnableIf set, this bit enables interrupt request generation when an error is signaledREPORTED during the execution of Posted Write cycles through the PCI target unit. A cleared bit disables these interrupts but does not disable Error Reporting (see bits 0 and 8 of PCI Error Control and Status register P_ERR_CS).**3Parity Error Interrupt enableThis bit enables/disables the generation of interrupt requests when a parity error is detected by the PCI master module. This interrupt is meaningful on Host Bridge Implementation only.*4System Error Interrupt EnableThis bit enables/disables the generation of interrupt requests when a system error (address parity error) is detected by the PCI master module.
This interrupt is decisive on Host Bridge Implementation only.*31Software ResetSetting this bit causes software initiated reset. Host bridge implementation uses this bit to reset the PCI bus, Guest implementation uses it to reset the WISHBONE bus. * Interrupt triggering upon PERR# and SERR# detection for Guest Implementation has no meaning because Guest Implementation triggers interrupts on the PCI bus. An agent that is responsible for routing interrupts to a host processor may trigger an interrupt when one of these errors is detected.
** For reporting Error Interrupt, appropriate Error Reporting Enable bit must be SET (bit 0 of P_ERR_CS and W_ERR_CS registers) besides Error Interrupt Enable bit (see also chapters 4.1.3.1 and 4.1.3.2).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 37: Interrupt Control Register bit descriptions
Interrupt Status Register: ISR
WidthAccessResetDescription32RW0x00000000This register is used to enable/disable the generation of interrupt requests from various sources.Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 38: Interrupt Status register
Register layout:
31 240x0023 160x0015 80x007 5432100x0SERR_INTPERR_INTPCI_EINTWB_EINTINTFigure STYLEREF 1 \s 4 SEQ Figure \* ARABIC \s 1 16: Interrupt Status register layout
Bit descriptions:
Bit #NameDescription0Interrupt For Guest bridge implementation this bit indicates that an INT_I input on the WISHBONE bus has been asserted and propagated to the INTA# pin on the PCI bus. This is to say that some device on the WISHBONE bus generated an interrupt request to the host processor.
For Host Bridge Implementation this bit indicates that the INTA# pin on the PCI bus has been asserted and propagated to the INT_O pin on the WISHBONE bus. This means that some device residing on the PCI bus generated an interrupt request to the host processor.1WISHBONE Error InterruptIf set, this bit indicates an interrupt request from the Error Reporting mechanism, which detected an error during the execution of a Posted Write cycle through the WISHBONE slave unit. Only reported error causes this interrupt.**2PCI Error InterruptIf set, this bit indicates an interrupt request from the Error Reporting mechanism, which detected an error during the execution of a Posted Write cycle through the PCI target unit. Only reported error causes this interrupt.**3Parity Error InterruptThis bit indicates that an interrupt request has been generated due to a Parity Error on the PCI bus.
This interrupt has meaning only on Host Bridge Implementation.*4System Error Interrupt EnableThis bit indicates that an interrupt request has been generated due to System Error (Address Parity) on the PCI bus. This interrupt has meaning only on Host Bridge Implementation.** Interrupt triggering upon PERR# and SERR# detection for Guest Implementation has no meaning because Guest Implementation triggers interrupts on the PCI bus. In Guest Implementation, these two bits will never be set.
** For reporting Error Interrupt, appropriate Error Reporting Enable bit must be SET (bit 0 of P_ERR_CS and W_ERR_CS registers) besides Error Interrupt Enable bit (see also chapters 4.1.3.1 and 4.1.3.2).
Table STYLEREF 1 \s 4 SEQ Table \* ARABIC \s 1 39: Interrupt Status register bit descriptions
4.2 Software obligations
If bridge is implemented as GUEST, software (running on a PCI host device) should during initialization phase first set the registers in the PCI Configuration Space Header with configuration cycles (PCI Base Addresses must be mapped without interleaving and not used images must be disabled and finally PCI Master and Target Memory and/or IO spaces must be enabled). Other control and status registers and WBU registers can now be set through Image0 with memory cycles.
If bridge is implemented as HOST, software (running on a WB host device) should during initialization phase first set the PCI and WB Image registers and other status and control registers (PCI and WB Base Addresses must be mapped without interleaving and not used images must be disabled and finally PCI Master and Target Memory and/or IO spaces must be enabled).
When system is running, software MUST NOT just change any Image related registers, but must first disable appropriate Unit (WBU or PCIU or both), otherwise no one can determine what transactions were processed and where (e.g. if Translation Address is changed when the opposite side is writing through that Image).
If bridge is implemented as HOST, WB device can always access Configuration space and change WB Image related registers, since WB device is accessing Configuration space. Before changing the PCI Image relate registers, WB device must first disable PCI Target Memory and IO spaces.
If bridge is implemented as GUEST, PCI host device can always access Configuration space and change PCI Image related registers, since PCI device is accessing Configuration space. Care must be taken, if PCI host device wont to change PCI Base Address 0 (through which it is accessing Configuration space). This must be done with PCI configuration cycles. Before changing the WB Image relate registers, PCI host device must first disable PCI Master operation.
XE "registers:interrupt, control & status"
IO Ports
5.1 PCI Interface
The PCI interface contains both required and optional pins. All of them are organized in functional groups. Required pins must be implemented but there is also a description of implemented optional pins (needed for requested features).
5.1.1 Required PCI Interface Pins
PortWidthDirectionDescriptionAD32I/OMultiplexed address and data bus (little endian)C/BE#4I/OMultiplexed command and byte enable bus (This bus indicates a PCI command during address phases and Byte Enables during data phases.)PAR1I/OParity bitTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 1: PCI address and data pins XE "IO ports:PCI interface:address and data pins"
PortWidthDirectionDescriptionFRAME#1I/OStart and end of a transactionIRDY#1I/OInitiator ready (The assertion of this signal indicates that the initiator is ready to send or receive data.)DEVSEL#1I/ODevice selected (When a target recognizes its address on the bus it asserts this signal to claim the transaction.)TRDY#1I/OTarget ready (The assertion of this signal indicates that the target is ready to send or receive data.)STOP#1I/OStop (This pin is used by a target to signal various terminating conditions.)IDSEL1IIndividual device select (This signal is used for configuration and requests a unique IDSEL line per agent.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 2: PCI interface control pins XE "IO ports:PCI interface:interface control pins, required"
PortWidthDirectionDescriptionPERR#1I/OParity errorSERR#1I/OSystem errorTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 3: PCI error reporting pins XE "IO ports:PCI interface:error reporting pins"
PortWidthDirectionDescriptionREQ#1OAsserted by initiator to request bus ownershipGNT#1IAsserted by Arbiter to grant bus ownershipTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 4: PCI arbitration pins XE "IO ports:PCI interface:arbitration pins" (INITIATOR only)
PortWidthDirectionDescriptionCLK1IPCI input clock (Signals are sampled on the rising edge of the clock.)RST#1I/OAsynchronous reset (The PCI device must tri-state all signals during reset.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 5: PCI system pins XE "IO ports:PCI interface:system pins" XE "pins:required" \r "PinsRequired"
5.1.2 Implemented Optional PCI Interface Pins
PortWidthDirectionDescriptionINTA#1OAsserted by initiator to request an interrupt.Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 6: PCI interrupt pin XE "IO ports:PCI interface:interrupt pins, optional"
PortWidthDirectionDescriptionM66EN1IMode 66 MHz Enable (This signal indicates to a device whether the bus segment is operating at 66 or 33 MHz.)CLKRUN#1I/O/ZClock running (This is the central resource request permission to stop or slow down CLK. The central resource must provide the pull-up for CLKRUN#.).PME#1OPower Management Event (This signal can be used by a device to request a change in the device or system power state. The assertion and deassertion of PME# is asynchronous to CLK.)Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 7: PCI interface control pins XE "IO ports:PCI interface:interface control pins, optional" XE "pins:optional" \r "PinsOptional"
5.2 WISHBONE Interface
The SoC interface is a WISHBONE Rev. B compliant interface. The WISHBONE slave unit of the PCI IP core is connected to the WISHBONE bus as a slave while the PCI target unit connects to the WISHBONE bus as a master.
PortWidthDirectionDescriptionADDR_O32OAddress outputMDATA_I32IData inputMDATA_O32OData outputSEL_O4OWE_O asserted indicates valid bytes on the MDATA_O bus
WE_O deasserted indicates which bytes must be supplied by slave on MDATA_I busWE_O1OWrite enable indicates a Write cycle when asserted high and a Read cycle when lowCYC_O1OEncapsulates a valid transfer cycleSTB_O1OIndicates a valid transfer to the slaveACK_I1IAcknowledgment input slave signals a normal cycle terminationERR_I1ISlave signals abnormal cycle terminationRTY_I1ISlave signals that the interface is not ready and that the master should retry the operationCAB_O1OIndicates to the slave that consecutive address block transfer is in progressTable STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 8: PCI target units XE "IO ports:WISHBONE interface: PCI target unit" WISHBONE interface (master)
PortWidthDirectionDescriptionADDR_I32IAddress inputSDATA_I32IData inputSDATA_O32OData outputSEL_I4IWE_O asserted indicates valid bytes on MDATA_I bus
WE_O deasserted indicates which bytes must be supplied on MDATA_O bus.WE_I1IWrite enable indicates a Write cycle when asserted high and a Read cycle when asserted lowCYC_I1IEncapsulates a valid transfer cycleSTB_I1IIndicates a valid transfer to the slaveACK_O1OAcknowledgment output slave signals a normal cycle terminationERR_O1OSlave signals abnormal cycle terminationRTY_O1OSlave signals that the interface is not ready and that the master should retry the operationCAB_I1IMaster signals consecutive address block transfer, which is in progress when 1Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 9: WISHBONE slave units XE "IO ports:WISHBONE interface:WISHBONE slave unit" WISHBONE interface (slave)
PortWidthDirectionDescriptionCLK_I1IClock input (application side clock)RST_I1IReset input (application side reset)RST_O1OUsed for propagating RST# from PCI bus to application side of the bridge; also used for initiating software resetINTA_O(*)1OInterrupt outputINTA_I(*)1IInterrupt input(*) These two signals will never be used at the same time. Guest Implementation of the core will signal interrupts to the PCI bus, so only INTA_I is used. Host Bridge Implementation will signal interrupts to the WISHBONE bus, so INTA_O is used.
Table STYLEREF 1 \s 5 SEQ Table \* ARABIC \s 1 10: WISHBONE common control and system I/Os XE "IO ports:WISHBONE interface:common control and system I/Os"
Waveforms
6.1 Wishbone Slave Unit
This section describes basic waveforms of various accesses to the cores configuration space and mapped PCI address space. Waveforms supplied have only informational purpose at this time.
6.1.1 WISHBONE Configuration Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 1: WISHBONE XE "waveforms:WISHBONE slave unit:configuration read cycle" configuration Read cycle
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 2: WISHBONE Configuration Write cycle XE "configuration write cycles" XE "waveforms:WISHBONE slave unit:configuration write cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 3: WISHBONE configuration RMW XE "write cycles:read modify writes (RMW)" cycle XE "waveforms:WISHBONE slave unit:configuration read modify write cycle"
Wishbone masters will most commonly use Single Read XE "read cycles:single reads" cycles for accessing the cores configuration space as shown in REF _Ref513875698 \* MERGEFORMAT Figure 6 1. A Write cycle to the cores register space by the WISHBONE master is shown in REF _Ref513874421 \* MERGEFORMAT Figure 6 2. Writes to unimplemented configuration space have no effect while Read cycles return all 0s. RMW cycles to the cores configuration space are also accepted, as shown in REF _Ref513876813 \* MERGEFORMAT Figure 6 3, and are most commonly used for interrupt handling since a RMW cycle is defined as atomic (indivisible) operation in the WISHBONE Bus Specification. XE "configuration cycles:WISHBONE, waveforms" \r "ConfigurationCyclesWISHBONE"
6.1.2 WISHBONE to PCI Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 4: WISHBONE access to PCI address space XE "waveforms:WISHBONE slave unit:access to PCI address space"
REF _Ref513878541 \* MERGEFORMAT Figure 6 4 shows how the WISHBONE master perceives cycles intended for PCI address space traveling through the WISHBONE slave unit of the core. The first cycle in the figure initiated by the WISHBONE master is a Block Write XE "write cycles:block writes" cycle. The WISHBONE slave module accepts Write cycles until WBW_FIFO is full. Subsequent Write cycles in this block cycle are terminated with Retry XE "termination signals:retry" (RTY_O asserted on ADDRn, DATAn, SELn transfer). The second cycle in the figure is a Read cycle. Read cycles from PCI address space are retried immediately (RTY_O asserted on first ADDR_Del, SEL_Del transfer). Address, byte enable, and CAB_I information is latched by the WISHBONE slave unit on the first rising edge of CLK_I where STB_I is asserted. The third cycle is a Write cycle to the PCI address space and is retried, too. In this case, the WISHBONE slave unit signals a Retry XE "termination signals:retry" if one of the following possibilities occurs:
WBW_FIFO is still full from previous transfers.
A delayed Read XE "read cycles:delayed reads" cycle latched in a previous transfer has not completed on the PCI bus yet.
A Delayed Read XE "read cycles:delayed reads" completion is present in the PCI target unit and has been completed on the PCI bus yet.
In the 4th cycle, the WISHBONE master retries a Read request initiated and latched by the WISHBONE slave module in the 2nd cycle. Since the PCI master module has already performed a Read cycle on the PCI bus and stored data in WBR_FIFO, the WISHBONE slave module takes data from the FIFO and delivers it on the WISHBONE bus. The WISHBONE slave module can supply data for the master as long as WBR_FIFO contains any data and Read addresses are serial and DWORD aligned.
6.1.3 PCI Cycles
The WISHBONE slave unit incorporates a PCI master module that is capable of initiating various types of PCI address space accesses.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 5: PCI Single Read XE "read cycles:single reads" cycle XE "waveforms:WISHBONE slave unit:single read cycle, PCI"
REF _Ref513881598 \* MERGEFORMAT Figure 6 5 shows a Single Read XE "read cycles:single reads" cycle on the PCI bus performed by the PCI master module. On the first clock edge, the PCI master module samples its GNT# signal asserted and claims the bus cycle by asserting FRAME# on the next rising edge of the clock. The 2nd clock cycle is also an address phase, so address and bus command information is provided on ADDR and C/BE# lines respectively. At the end of an address phase, the master module de-asserts FRAME# and asserts IRDY#, indicating its wish to perform a single data phase only. A device with medium decoding has been assumed for a diagram, so nothing happens on the 3rd rising edge of clock. On the 4th clock, the target device claims access by asserting DEVSEL#. This clock cycle is used as Turnaround cycle (target starting to drive AD lines) inserted by delaying assertion of TRDY#. On the 5th clock, actual data transfer occurs, indicated by TRDY# and IRDY# being asserted at the same time. Immediately afterwards, the master module de-asserts IRDY#, indicating the end of transfer.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 6: PCI Single Write XE "write cycles:single writes" XE "waveforms:WISHBONE slave unit:single writes, PCI"
REF _Ref513885186 \* MERGEFORMAT Figure 6 6 shows a Single Write XE "write cycles:single writes" cycle on the PCI bus performed by the PCI master module. On the first clock edge, the PCI master module samples its GNT# signal asserted and claims the bus cycle by asserting FRAME# on the next rising edge of the clock. The 2nd clock cycle is also an address phase, thus address and bus command information is provided on ADDR and C/BE# lines respectively. At the end of an address phase, the master module de-asserts FRAME# and asserts IRDY#, indicating its wish to perform a single data phase only. By asserting IRDY#, Write data and byte enables must be driven on AD and C/BE# lines respectively. A device with medium decoding has been assumed for a diagram, so nothing happens on the 3rd rising edge of the clock. On the 4th clock, the target device claims access by asserting DEVSEL#. On this clock, actual data transfer occurs also, indicated by TRDY# and IRDY# being asserted at the same time. Immediately afterwards, the master module de-asserts IRDY#, indicating the end of transfer.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 7: PCI Burst Read XE "read cycles:burst reads" Cycle XE "waveforms:WISHBONE slave unit:burst read cycle, PCI"
REF _Ref513886106 \* MERGEFORMAT Figure 6 7 shows how the PCI master module performs Burst Read transactions. The mechanism for claiming the bus is the same as in previous diagrams. The main difference lies with the fact that FRAME# stays asserted till the last data transfer. A medium decode target device is assumed for the diagram that inserts a Turnaround cycle on clock 4. The target also inserts one WS after each data phase. Byte enables do not change during bursts. They are always 0000. The last data phase is phase 3, which is indicated by FRAME# de-asserted and IRDY# asserted at the same clock edge. Immediately after the master module latched data from the bus (clock edge when TRDY# is asserted), it de-asserts IRDY# to indicate an end of the transfer.
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 8: PCI Burst Write XE "write cycles:burst writes" cycle XE "waveforms:WISHBONE slave unit:burst write cycle, PCI"
REF _Ref513887067 \* MERGEFORMAT Figure 6 8 shows PCI Burst Write XE "write cycles:burst writes" cycles performed by the PCI master module. The mechanism for claiming the bus is the same as in the previous diagrams. FRAME# stays asserted till the last data transfer. A medium decode target device is assumed for a diagram that claims access and latches the first data beat on clock 4. The target also inserts one WS after each data phase. The last data phase is phase 3, which is indicated by FRAME# de-asserted and IRDY# asserted at the same clock edge. Immediately after the target latched data from the bus (clock edge when TRDY# is asserted), the master module de-asserts IRDY# to indicate an end of the transfer.
6.1.4 PCI Terminations
6.1.4.1 Master Initiated Terminations
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 9: Master Abort XE "waveforms:WISHBONE slave unit:master abort termination, PCI" XE "termination signals:master abort" termination
The PCI master module terminates the transaction with Master Abort XE "termination signals:master abort" , as shown in REF _Ref513951759 \h \* MERGEFORMAT Figure 6 9. What happens? The master initiates a transaction with the address phase and waits for the target to respond by asserting DEVSEL#. The master is only required to wait for the assertion of DEVSEL# for 4 clocks. If DEVSEL# will not have been asserted by the 4th clock (subtractive decode devices), the master de-asserts FRAME# and must hold IRDY# asserted for an additional clock cycle indicating the end of the transaction.
If Error Reporting is enabled and the transaction is a Posted Write XE "write cycles:posted writes" cycle, then address, bus command, data, and byte enables are stored in corresponding registers (see chapter REF _Ref513955180 \r \* MERGEFORMAT 0) and the WISHBONE slave unit locks out all, but the configuration space accesses until the proper error status bit will be cleared. The current transaction is discarded (pulled out of WBW_FIFO) while any other Posted Write XE "write cycles:posted writes" cycles are not influenced by Error XE "termination signals:error" .
If the transaction is a Read cycle, the termination is signaled to the WISHBONE master with an error on the WISHBONE bus when it retries a Read request.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 10: Timeout termination XE "termination signals:timeout termination " XE "waveforms:WISHBONE slave unit:timeout termination"
The Timeout termination is specified in the PCI Local Bus Specification. It must be implemented in the PCI master module. Timeout termination is not an abnormal termination; it is simply a means of assuring other masters access to the PCI bus within a reasonable span of time. The master is supposed to complete the transaction by the time the latency timer expires and its GNT# has been removed by the PCI arbiter. In other words, when the master latency timer expires, the PCI master module must sample its GNT# on every rising edge of clock. If it samples it in de-asserted mode, it must complete the transaction as soon as possible. As shown in REF _Ref513957411 \* MERGEFORMAT Figure 6 10, the latency timer of the master is assumed to expire and its grant to be removed by data phase N-1. The master module samples GNT# de-asserted, thus it completes an access on the next clock cycle by de-asserting FRAME#.
Timeout terminations are not signaled to the WISHBONE bus since the PCI master module can resume transaction the next time it gains bus mastership.
Timeout detection is implemented with a counter and the Master Latency Timer register in the PCI configuration space. The counter is enabled when the PCI master module asserts FRAME# and is cleared and suspended as soon as FRAME# is de-asserted.
6.1.4.2 Target Terminations Handled by PCI Master Module
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 11: Target Abort XE "waveforms:WISHBONE slave unit:target abort, PCI" XE "termination signals:target abort"
A target signals Target Abort XE "termination signals:target abort" to the master when it is and will be unable to complete the access initiated by the master. In this case, the master should not attempt to retry accesses terminated with Target Abort XE "termination signals:target abort" .
Posted Write XE "write cycles:posted writes" cycles terminated with Target Abort XE "termination signals:target abort" are discarded. If Error Reporting is enabled, the WISHBONE slave unit reports an error and locks out any non-configuration space accesses until the corresponding error status bit is cleared.
The Target Abort XE "termination signals:target abort" termination during Read cycles is signaled to the WISHBONE master when retrying the request. Access to the address that resulted in Target Abort XE "termination signals:target abort" is terminated with an error on the WISHBONE bus. If the WISHBONE master never accesses the address that resulted in Target Abort XE "termination signals:target abort" , termination will not be signaled in any way (Target Abort XE "termination signals:target abort" can be signaled because the PCI master module reads over address space boundaries of a specific target during a pre-fetched Read cycle in order that the WISHBONE master will never perform a Read cycle to that address).
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 12: Target Retry XE "waveforms:WISHBONE slave unit:target retry, PCI" XE "termination signals:retry"
A target signals a Retry XE "termination signals:retry" to the master when it is not ready to process the request. No data is transferred during Retry XE "termination signals:retry" . Nevertheless, the PCI master must still terminate normally by de-asserting FRAME# and keeping IRDY# asserted for one PCI clock cycle to indicate the last data phase. The master must relinquish the PCI bus for at least two cycles after it received a Target Retry XE "termination signals:target retry" by de-asserting its REQ# line. It must also retry the same request at a later time.
Target Retry XE "termination signals:target retry" is not signaled on the WISHBONE bus. The PCI master module retries the transaction transparently on the PCI bus.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 13: Target Disconnect XE "termination signals:target disconnect without data" without data XE "waveforms:WISHBONE slave unit:target disconnect without data, PCI"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 14: Target Disconnect XE "termination signals:target disconnect with data" with data XE "waveforms:WISHBONE slave unit:target disconnect with data, PCI"
A target signals Target Disconnect XE "termination signals:target disconnect" to the master when it is not capable of receiving or supplying any more data from/to the master. Data must be transferred with (Disconnect XE "termination signals:disconnect with data" with Data) or before (Disconnect XE "termination signals:disconnect without data" without Data) the target signals Target Disconnect XE "termination signals:target disconnect" . The master must terminate the transaction normally by de-asserting FRAME# and keeping IRDY# asserted for one clock cycle. If the target signals Target Disconnect XE "termination signals:target disconnect with data" with data on the last data phase (FRAME# de-asserted, IRDY#, TRDY#, and STOP# asserted), the termination is treated as a normal master termination. (e.g. STOP# is a Logical Dont Care for a master when FRAME# is de-asserted and IRDY# and TRDY# are asserted).
Target Disconnect XE "termination signals:target disconnect" is not an abnormal termination and will not be signaled to the WISHBONE master in any way. XE "WISHBONE:slave unit:waveforms" \r "WaveformsWISHBONE" XE "termination cycles:PCI" \r "TerminationCyclesPCI"
6.2 PCI Target Unit
This section describes basic waveforms of various accesses to core configuration space and mapped WISHBONE address space. Waveforms supplied have only informational value at this time.
6.1.2 PCI Configuration Accesses
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 15: PCI Configuration Read cycle XE "waveforms:PCI target unit:configuration read cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 16: PCI Configuration Write cycle XE "configuration write cycles" XE "waveforms:PCI target unit:configuration write cycle" XE "waveforms:PCI target unit:target read cycle"
PCI initiators will most commonly use Single Read XE "read cycles:single reads" cycles for accessing the core configuration space as shown in REF _Ref514563187 \h \* MERGEFORMAT Figure 6 15. A Write cycle to the register space of the core by the PCI initiator is shown in REF _Ref514563200 \h \* MERGEFORMAT Figure 6 16. Write cycles to unimplemented configuration space have no effect, while Read cycles return all 0s. XE "configuration cycles:PCI, waveforms" \r "ConfigurationCyclesPCI"
6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles
The following figures show how the PCI initiator sees cycles intended for the WISHBONE address space, traveling through the PCI target unit of the core. The first cycle in REF _Ref514567413 \* MERGEFORMAT Figure 6 17, started by the PCI initiator, is a Delayed Read command. The PCI target module accepts the Read command. Subsequent Reads in this cycle are terminated with Retry XE "termination signals:retry" . The next figure shows the previous transaction transferred to the WISHBONE bus. The second cycle in the first figure is a Read from the PCI master.
For reference: There are also burst accesses from the PCI through the PCI target module (Read and Write) on REF _Ref514567463 \* MERGEFORMAT Figure 6 19 and REF _Ref514564864 \* MERGEFORMAT Figure 6 20. Last follows a diagram of a Write transfer on the WISHBONE bus initiated by the PCI initiator.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 17: PCI Target Read cycle XE "waveforms:PCI target unit:target read cycle"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 18: PCI to WISHBONE Read cycle XE "waveforms:PCI target unit:read cycle to WISHBONE"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 19: PCI Initiator to Target Burst Read XE "read cycles:burst reads" cycle XE "waveforms:PCI target unit:burst read cycle, initiator to target"
EMBED Word.Picture.8
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 20: PCI Initiator to Target Burst Write cycle XE "waveforms:PCI target unit:burst write cycles, initiator to target"
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 21: WISHBONE Write transfer caused by PCI to WISHBONE Write XE "waveforms:PCI target unit:write transfer, WISHBONE" cycle
6.2.3 WISHBONE Terminations
Terminations on the WISHBONE bus are always performed by WISHBONE slaves. Chapters REF _Ref527758515 \h 3.3.3 PCI to WISHBONE Write Cycles and REF _Ref527758530 \h 3.3.4 PCI to WISHBONE Read Cycles describe the causes of Retry XE "termination signals:retry" or Error XE "termination signals:error" on the WISHBONE bus.
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 22: Retry XE "termination signals:retry" on WISHBONE bus XE "waveforms:PCI target unit:retry on WISHBONE bus" caused by PCI to WISHBONE transfer
Figure STYLEREF 1 \s 6 SEQ Figure \* ARABIC \s 1 23: Error XE "termination signals:error" on WISHBONE bus XE "waveforms:PCI target unit:error on WISHBONE bus" caused by PCI to WISHBONE transfer XE "PCI target unit:waveforms" \r "WaveformsPCI" XE "termination cycles:WISHBONE" \r "TerminationCyclesWISHBONE"
A
Core HW Configuration
This section describessummarizes parameters that are set by the usersystem designer of the core and define itscores configuration, the user (e.g. programmer) must know. The usersystem designer must set the parameters before actually using the core in simulation or synthesis. For details read PCI IP Core design document.
A.1 HW Configuration Parameters
Configuration parameters XE "configuration parameters" are grouped into one file, which can be edited by the system designer, depending on the needs of the application (see chapters 2.4 and 2.5 of the PCI IP Core Design document). Only parameters useful for the user of the core are summarized here. The system designer should mark which parameters are defined (or the value of the parameter).
ParameterDefined value / Defined (yes, no)DescriptionHOST / GUESTThese two defines are mutually exclusive. Core will be implemented or simulated with HOST or GUEST bridge features enabled (see chapter 3.1).WBW_ADDR_LENGTHWBR_ADDR_LENGTHPCIW_ADDR_LENGTHPCIR_ADDR_LENGTHNumbers defined here define each one of four Fifos size. Size is calculated as 2^^ADDR_LENGTH. Note that Fifos control logic is such, that one location in RAM is always empty, so usable Fifo size is (2^^ADDR_LENGTH) 1. Any value equal to or larger than 3 is valid here the only restriction is the size of RAMs instantiated for Fifo storage.ADDR_TRAN_IMPLIf defined, address translation functionality is added to decoders for both, PCI and WISHBONE accesses. Address translation implementation is useful when application uses fixed address map, while PCI address map is configurable. PCI_NUM_OF_DEC_ADDR_LINESNumber defined here is used for controlling implementation of PCI images decoders. It defines how many MSB address lines are used for decoding PCI Target accesses and therefore defines what minimum image size can be. Maximum number allowed is 20 ( 4KB minimum image size ) and minimum is 1 ( 2GB minimum image size this value implies that more than two images cannot be enabled at the same time ). NO_CNF_IMAGEIf defined, it prevents Read-Only configuration image to be implemented. Read-Only Configuration space access can be provided through PCI image 0 for HOST implementation of the Core, and through WB image 0 for GUEST implementation. If NO_CNF_IMAGE is defined, then this image is not implemented (some additional space is saved).PCI_IMAGE0 *This define only has meaning when HOST and NO_CNF_IMAGE are defined also. This enables usage of additional PCI Target image 0 (PCI_IMAGE0) for accessing WISHBONE bus address space from PCI address space. Otherwise, PCI_IMAGE0 does not needs to be defined, since it is always used for accessing Configuration space.PCI_IMAGE2 *PCI_IMAGE3 *PCI_IMAGE4 *PCI_IMAGE5 *If whichever defined, then that PCI Target image is implemented.PCI_AM0 ***PCI_AM1PCI_AM2 **PCI_AM3 **PCI_AM4 **PCI_AM5 **Numbers defined here are initial ( reset ) values of PCI address masks registers. These are very important if the Core is implemented as GUEST, since configuration is done via PCI Target state machine. If the designer wants an implemented PCI Target image to be detected by device independent software at system power-up, he has to set initial masks to enabled state MS bit has to be 1. Other bits can have a value of 1 or zero, depending on what size of an image has to be presented to the software. The masks can be set inactive also, but device independent software wont detect implemented PCI Target images and therefore not configure them. Device specific software will then have to jump in to configure images with inactive initial masks defined, which also means that it will probably have to rebuild PCI address space map.PCI_BA0_MEM_IO ***PCI_BA1_MEM_IOPCI_BA2_MEM_IO **PCI_BA3_MEM_IO **PCI_BA4_MEM_IO **PCI_BA5_MEM_IO **Numbers defined here are initial ( reset ) values of PCI Base Address registers bits 0. If the Core is configured as HOST, this initial values can later be changed by writing appropriate value to appropriate PCI Base Address register. If the core is GUEST, than this values are hardwired, because device independent software must know in advance where to map each PCI Base Address.WB_NUM_OF_DEC_ADDR_LINESNumber defined here is used for controlling implementation of WISHBONE images decoders. It defines how many MSB address lines are used for decoding WISHBONE Slave accesses and therefore defines what minimum image size can be. Maximum number allowed is 20 (4KB minimum image size) and minimum is 1 (2GB minimum image size this value implies that more than two images cannot be enabled at the same time). WB_IMAGE2WB_IMAGE3WB_IMAGE4WB_IMAGE5If whichever defined, then that WB Slave image is implemented.WB_CONFIGURATION_BASENumber defined here is a 20 bit value for WISHBONE configuration image address. Those bits are compared to 20 MS bits of WB Slave address to decode Configuration accesses from WB bus. This is constant value and cannot be changed after the Core is implemented, since WB bus does not provide any special mechanism for device configuration.WB_RTY_CNT_MAXNumber defined here is used to prevent deadlock in WB Master state machine for maximum counting value of RTY terminations on WB bus, before ACK or ERR terminations. The last two terminations reset the counter. This counter is also used, when no WB device responds (e.g. if accessing to unused memory locations). In that case internal set_retry signal is set every 8 WB clock periods and counter counts to maximum value defined.PCI33 / PCI66These two defines are mutually exclusive. They are used for simulation purposes ( PCI clock speed ) and to set 66MHz Capable bit in PCI Device Status register, if PCI66 is defined. There are no other features dependent on those defines.HEADER_VENDOR_IDEach PCI bus compatible hardware vendor gets its 16 bit hexadecimal ID from PCI SIG organization. It should be specified in this define. This value shows up in Vendor ID register of PCI Type0 Configuration Header.HEADER_DEVICE_IDDevice ID is vendor specific, 16 bit hexadecimal value. It shows up in Device ID register of PCI Type0 Configuration Header.HEADER_REVISION_IDRevision ID is vendor specific, 8 bit hexadecimal value, that shows up in Revision ID register of PCI Type0 Configuration Header.* ( PCI image 1 is always implemented, without any exceptions
** ( This value is significant only if appropriate PCI image is implemented
*** ( This value is significant only if PCI image 0 is implemented to access WB bus
Table STYLEREF 1 \s 6 SEQ Table \* ARABIC \s 1 1: User Useful HARDWARE Configuration Parameters
INDEX \e " " \c "2" \z "1033" address translation logic
address mask register, setting rule 10
address range 10
architecture 11
registers 10
architecture
address translation logic 1011
clocks 8
FIFO 89
PCI bridge, general overview 3
PCI target unit 68, 25
WISHBONE slave unit 46, 19
clocks 8, 9
compliances
PCI interface 3
WISHBONE 3
configuration cycles 14, 1518
access to configuration space 15
field values 1617
generating 16
PCI, waveforms 74
registers 5557
WISHBONE, waveforms 6566
configuration parameters 78
configuration space 1218
access for guest bus bridges 14
access for host bus bridges 13
access to configuration cycles 15
access, general 12
definition 12
header
class code 44
device ID 43
header type 43
registers 4447
revision ID 43
vendor ID 43
interrupt acknowledge cycles 18
configuration write cycles 66, 74
decoder 4
device identification See configuration space header
encoding 21, 24, 28, 29, 31
expansion bus bridges See guest bus bridges
features, PCI IP core 12
field values, configuration cycles 1617
FIFO 89
architechture 9
architecture 8
PCI read FIFO 7, 26
PCI write FIFO 7, 26
register lines 8
WISHBONE read FIFO 5, 6, 19
WISHBONE write FIFO 5, 6, 19
First in First out 89. See also FIFO
identification See configuration space header
interrupt acknowledge cycles
generating 18
register 57
interrupts, generating and reporting 3334
IO ports
PCI interface
address and data pins 61
arbitration pins 62
error reporting pins 62
interface control pins, optional 63
interface control pins, required 62
interrupt pins, optional 62
system pins 62
WISHBONE interface
common control and system I/Os 64
PCI target unit 63
WISHBONE slave unit 64
operation
configuration space 1218
interrupts 3334
parity 33
transaction ordering 3233
WISHBONE slave unit 1825
parity 33
PCI bridge, introduction
architecture 3
function 1
PCI target unit 3
WISHBONE slave unit 3
PCI target unit 3
address range, example 27
address space access
I/O mapped 28
memory mapped 29
address space, non-prefetchable 31
address translation, example 28
architecture 68, 25
basic functionality 25
configuration space header 4347
encoding 28, 29, 31
error reporting mechanism 30
error reporting registers 5355
function 6
images mapped to I/O space 31
images mapped to memory space 30
images, configurable 26
images, selecting 6
read FIFO 7, 26
target module 7, 26
termination signals 24, 32
waveforms 7477
WISHBONE master module 8, 26
write cycles to WISHBONE 2830
write FIFO 26
pins
optional 6263
required 6162
read cycles
block reads 23, 31
burst reads 23, 24, 31, 32, 69, 76
delayed reads 5, 22, 23, 24, 29, 30, 31, 33, 67
single reads 12, 14, 25, 31, 66, 68, 74
WISHBONE to PCI 2123
registers
interrupt, control & status 60
list of 3538
PCI target unit, configuration space header 4347
PCI target unit, control & status 51
reporting 57
WISHBONE slave unit, control & status 42
termination cycles
PCI 7073
WISHBONE 77
termination signals
disconnect 25, 29
disconnect with data 24, 31, 73
disconnect with/without data 29, 32
disconnect without data 24, 73
error 22, 23, 30, 31, 32, 52, 53, 54, 55, 70, 77
master abort 18, 22, 25, 45, 52, 70
retry 22, 24, 25, 29, 31, 32, 33, 52, 54, 67, 72, 75, 77
system error 45
target abort 22, 24, 25, 28, 29, 32, 45, 52, 71, 72
target disconnect 22, 24, 73
target disconnect with data 14, 15, 28, 73
target disconnect without data 73
target retry 72
timeout termination 71
transaction ordering 3233
waveforms
PCI target unit
burst read cycle, initiator to target 76
burst write cycles, initiator to target 76
configuration read cycle 74
configuration write cycle 74
error on WISHBONE bus 77
read cycle to WISHBONE 75
retry on WISHBONE bus 77
target read cycle 74, 75
write transfer, WISHBONE 76
WISHBONE slave unit
access to PCI address space 67
burst read cycle, PCI 69
burst write cycle, PCI 69
configuration read cycle 65
configuration read modify write cycle 66
configuration write cycle 66
master abort termination, PCI 70
single read cycle, PCI 68
single writes, PCI 68
target abort, PCI 71
target disconnect with data, PCI 73
target disconnect without data, PCI 73
target retry, PCI 72
timeout termination 71
WISHBONE
bus agents 4
slave module
read FIFO 6
slave unit
address range, example 20
address space, non-prefetchable 23
address translation, example 21
architecture 46
decoder 4
encoding 21, 24
error reporting mechanism 2223
error reporting registers 5153
function 4
images mapped to I/O space 23
images mapped to memory space 23
images, configurable 4, 20
operation 1825
PCI master module 6, 19
read cycles to PCI 23, 25
read FIFO 5, 19
slave module 5, 19
termination signals 32
waveforms 6573
write cycles to PCI 2123
write FIFO 5, 6, 19
write cycles
block writes 21, 22, 28, 30, 67
burst writes 29, 30, 69
PCI to WISHBONE 2830
posted writes 5, 6, 21, 22, 28, 30, 33, 51, 70, 72
read modify writes (RMW) 14, 21, 66
single writes 12, 14, 21, 22, 28, 30, 68
WISHBONE to PCI 2123
Note: Because the host bus bridge normally generates configuration commands, and the PCI local bus specification does not require a host bus bridge to respond to configuration cycles, it is most likely that this feature will never be used.
INCLUDEPICTURE "http://www.opencores.org/logos/jng3.gif" \* MERGEFORMATINET OpenCores PCI IP Core Specification DATE \@ "d.M.yyyy" 28.1.2002
HYPERLINK "http://www.opencores.org" http://www.opencores.org Rev 0.6 PAGE iv
INCLUDEPICTURE "http://www.opencores.org/logos/jng3.gif" \* MERGEFORMATINET OpenCores PCI IP Core Specification DATE \@ "d.M.yyyy" 28.1.2002
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, - . 0 1 2 3 4 5 N O P Q r s t ͳߝߕ{mߝߕY &j >*B*UmH nH ph u j[ UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH ujm UmH nH u j UmH nH umH nH u 0J aJ mH nH uj 0J UmH nH u &j >*B*UmH nH ph u" ) * + - . / 0 1 2 K L M N \ ] ^ u ưƨưƨl &j >*B*UmH nH ph u j7 UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u jI UmH nH u j UmH nH umH nH u 0J aJ mH nH u $u v w y z { | } ~ ѻѳяށiѳUK 0J aJ mH nH u&j >*B*UmH nH ph u .5;B* CJ OJ QJ aJ mH nH ph sH u j UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj% UmH nH u ! " # $ = > ? @ j k l ѻѳяkѳWя&jf" >*B*UmH nH ph u +6B* CJ OJ QJ aJ mH nH ph sH uj! UmH nH u 0J aJ mH nH u&jx! >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j! UmH nH u j UmH nH umH nH u"
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, - . 0 1 2 3 4 5 N O P Q r s t ͳߝߕ{mߝߕY &j >*B*UmH nH ph u j[ UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH ujm UmH nH u j UmH nH umH nH u 0J aJ mH nH uj 0J UmH nH u &j >*B*UmH nH ph u" ) * + - . / 0 1 2 K L M N \ ] ^ u ưƨưƨl &j >*B*UmH nH ph u j7 UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u jI UmH nH u j UmH nH umH nH u 0J aJ mH nH u $u v w y z { | } ~ ѻѳяށiѳUK 0J aJ mH nH u&j >*B*UmH nH ph u .5;B* CJ OJ QJ aJ mH nH ph sH u j UmH nH u 0J aJH mH nH u&j >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj% UmH nH u ! " # $ = > ? @ j k l ѻѳяkѳWя&jf" >*B*UmH nH ph u +6B* CJ OJ QJ aJ mH nH ph sH uj! UmH nH u 0J aJ mH nH u&jx! >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j! UmH nH u j UmH nH umH nH u"
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% & ' > ? @ B C D E F G ` a b c ѻѳяѻѳmя_ j$ UmH nH u &jB$ >*B*UmH nH ph u j# UmH nH u 0J aJ mH nH u&jT# >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j UmH nH uj" UmH nH u mH nH u% ! ) * + B C D ջye[Mj& UmH nH u 0J aJH mH nH u&j & >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj% UmH nH u j UmH nH umH nH u 0J aJ mH nH u&j0% >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u D F G H I J K d e f g x y z ߿ߛw߿cY 0J aJ mH nH u&j' >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj' UmH nH u 0J aJ mH nH u&j ' >*B*UmH nH ph u mH nH u0J mH nH u.5;B* CJ OJ QJ aJ mH nH ph sH u j 0J UmH nH u j UmH nH umH nH u B C D [ \ ] _ ` a b c d } ~ ѻѳяށѻѳmcU jM* UmH nH u 0J aJ mH nH u&j) >*B*UmH nH ph u j_) UmH nH u 0J aJ mH nH u&j( >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH ujq( UmH nH u! 2 3 4 K ޜvbX 0J aJ mH nH u&j+ >*B*UmH nH ph u .5;B* CJ OJ QJ aJ mH nH ph sH u j;+ UmH nH u 0J aJH mH nH u&j* >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH u K L M O P Q R S T m n o p
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% & ' > ? @ B C D E F G ` a b c ѻѳяѻѳmя_ j$ UmH nH u &jB$ >*B*UmH nH ph u j# UmH nH u 0J aJ mH nH u&jT# >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j UmH nH uj" UmH nH u mH nH u% ! ) * + B C D ջye[Mj& UmH nH u 0J aJH mH nH u&j & >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj% UmH nH u j UmH nH umH nH u 0J aJ mH nH u&j0% >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u D F G H I J K d e f g x y z ߿ߛw߿cY 0J aJ mH nH u&j' >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj' UmH nH u 0J aJ mH nH u&j ' >*B*UmH nH ph u mH nH u0J mH nH u.5;B* CJ OJ QJ aJ mH nH ph sH u j 0J UmH nH u j UmH nH umH nH u B C D [ \ ] _ ` a b c d } ~ ѻѳяށѻѳmcU jM* UmH nH u 0J aJ mH nH u&j) >*B*UmH nH ph u j_) UmH nH u 0J aJ mH nH u&j( >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH ujq( UmH nH u! 2 3 4 K ޜvbX 0J aJ mH nH u&j+ >*B*UmH nH ph u .5;B* CJ OJ QJ aJ mH nH ph sH u j;+ UmH nH u 0J aJH mH nH u&j* >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH u K L M O P Q R S T m n o p
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ѻѳяށkѳWя &j- >*B*UmH nH ph u +6B* CJ OJ QJ aJ mH nH ph sH uj- UmH nH u 0J aJ mH nH u&j, >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj), UmH nH u
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ѻѳяށkѳWя &j- >*B*UmH nH ph u +6B* CJ OJ QJ aJ mH nH ph sH uj- UmH nH u 0J aJ mH nH u&j, >*B*UmH nH ph u mH nH u0J mH nH u+:B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj), UmH nH u
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, - . / ? @ A X Y Z \ ] ^ _ ` a z { | } ѻѳяށѻѳmя_ j/ UmH nH u &jj/ >*B*UmH nH ph u j. UmH nH u 0J aJ mH nH u&j|. >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj. UmH nH u% ! " B C D [ \ ] ԺܰxdZL j1 UmH nH u 0J aJ mH nH u&jF1 >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj0 UmH nH u j UmH nH umH nH u 0J aJ mH nH u&jX0 >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u +6B* CJ OJ QJ aJ mH nH ph sH u ] _ ` a b c d } ~
% & ' ) * + , - . G H ߝ{ߝm j3 UmH nH u &j"3 >*B*UmH nH ph u j2 UmH nH u 0J aJ mH nH u&j42 >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j UmH nH umH nH u(b , v o 2 : X! ! " y" " M# # '$ $
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, - . / ? @ A X Y Z \ ] ^ _ ` a z { | } ѻѳяށѻѳmя_ j/ UmH nH u &jj/ >*B*UmH nH ph u j. UmH nH u 0J aJ mH nH u&j|. >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u mH nH u j UmH nH uj. UmH nH u% ! " B C D [ \ ] ԺܰxdZL j1 UmH nH u 0J aJ mH nH u&jF1 >*B*UmH nH ph u +:B* CJ OJ QJ aJ mH nH ph sH uj0 UmH nH u j UmH nH umH nH u 0J aJ mH nH u&jX0 >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u +6B* CJ OJ QJ aJ mH nH ph sH u ] _ ` a b c d } ~
% & ' ) * + , - . G H ߝ{ߝm j3 UmH nH u &j"3 >*B*UmH nH ph u j2 UmH nH u 0J aJ mH nH u&j42 >*B*UmH nH ph u mH nH u0J mH nH u+6B* CJ OJ QJ aJ mH nH ph sH uj 0J UmH nH u j UmH nH umH nH u(b , v o 2 : X! ! " y" " M# # '$ $
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H I J _ ` a x y z | } ~ ͳߛߓyoaK +:B* CJ OJ QJ aJ mH nH ph sH uju5 UmH nH u 0J aJ mH nH u&j4 >*B*UmH nH ph u mH nH u0J mH nH u.5;B* CJ OJ QJ aJ mH nH ph sH u j4 UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j4 >*B*UmH nH ph u ! k l m n ƾЌ{t{aRER cH dh
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H I J _ ` a x y z | } ~ ͳߛߓyoaK +:B* CJ OJ QJ aJ mH nH ph sH uju5 UmH nH u 0J aJ mH nH u&j4 >*B*UmH nH ph u mH nH u0J mH nH u.5;B* CJ OJ QJ aJ mH nH ph sH u j4 UmH nH u j UmH nH umH nH u 0J aJH mH nH uj 0J UmH nH u &j4 >*B*UmH nH ph u ! k l m n ƾЌ{t{aRER cH dh
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af j U.5;B* CJ OJ QJ aJ mH nH ph sH u jc6 UmH nH u j UmH nH umH nH u 0J aJ` mH nH uj 0J UmH nH u &j5 >*B*UmH nH ph u mH nH u0J mH nH u paTa: 3 j7 >*B*UcH dh
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afmH nH ph u 5 6 7 8 T U V p q r s t u Χ}p}VBΧ ' jK9 UcH dh
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afmH nH ph u ! " > ? @ A M N O i Χ|o|UD 0J aJ cH dh
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afmH nH ph u ! " > ? @ A M N O i Χ|o|UD 0J aJ cH dh
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afmH nH u 3 j; >*B*UcH dh
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afmH nH ph u% j 0J UcH dh
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afmH nH u' j?; UcH dh
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afmH nH ui j k l m n o p q طfUAط ' j3= UcH dh
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afmH nH ui j k l m n o p q طfUAط ' j3= UcH dh
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afmH nH ph u % j 0J UcH dh
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afmH nH u , - . / 0 1 2 3 4 P Q R S ij~cV< 3 j> >*B*UcH dh
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afmH nH u , - . / 0 1 2 3 4 P Q R S ij~cV< 3 j> >*B*UcH dh
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afmH nH ph u ' j-> UcH dh
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afmH nH ph u ! ! ! ! 5! 6! 7! Q! Χ}p}VE 0J aJ cH dh
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afmH nH ph u ! ! ! ! 5! 6! 7! Q! Χ}p}VE 0J aJ cH dh
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afmH nH ph uP0 Q0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 qbUb; 3 jk >*B*UcH dh
|
afmH nH ph uP0 Q0 R0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 qbUb; 3 jk >*B*UcH dh
|
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|
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|
afmH nH ph u 1 1 1 1 1 1 1 1 1 %1 &1 '1 (1 01 11 21 31 41 N1 طfU9U 7 5;B* CJ OJ QJ aJ cH dh
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afmH nH ph u 1 1 1 1 1 1 1 1 1 %1 &1 '1 (1 01 11 21 31 41 N1 طfU9U 7 5;B* CJ OJ QJ aJ cH dh
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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afmH nH u4 :B* CJ OJ QJ aJ cH dh
|
afmH nH u4 :B* CJ OJ QJ aJ cH dh
|
afmH nH ph u2 2 2 2 02 12 22 32 O2 P2 Q2 R2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 P3 Q3 R3 l3 m3 n3 p3 q3 r3 s3 t3 u3 3 ڸtڸfjp UmH nH u &jxp >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jo UmH nH u j UmH nH umH nH u &j~o >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u j U j UcH dh
|
afmH nH ph u2 2 2 2 02 12 22 32 O2 P2 Q2 R2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 P3 Q3 R3 l3 m3 n3 p3 q3 r3 s3 t3 u3 3 ڸtڸfjp UmH nH u &jxp >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jo UmH nH u j UmH nH umH nH u &j~o >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u j U j UcH dh
|
af(3 3 3 3 3 3 3 3 3 3 3 3 3 4 4 4 4 4 4 !4 z4 {4 |4 4 4 4 4 4 4 4 4 4 4 4 4 4
5 5 5 δ֞v֞b &jfs >*B*UmH nH ph u jr UmH nH u &jlr >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u jq UmH nH u j UmH nH umH nH u j 0J UmH nH u &jrq >*B*UmH nH ph u 0J mH nH u &5 )5 *5 +5 -5 .5 /5 05 15 25 N5 O5 P5 Q5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 6 6 6 6 6 6 6 ѻѳѳѻѳwѳiѻѳ ju UmH nH u &jZu >*B*UmH nH ph u jt UmH nH u &j`t >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH ujs UmH nH u mH nH u) 6 ;6 <6 =6 >6 {6 |6 }6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 7 7 7 7
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@ @ *@ +@ ,@ -@ j@ k@ l@ @ @ @ @ @ @ @ @ @ ѻѳѳѻѳwѳiѻѳ jS UmH nH u &j֊ >*B*UmH nH ph u jY UmH nH u &j܉ >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj_ UmH nH u mH nH u)@ @ @ @ @ @ @ @ A A A A A A A A A %A &A 'A (A oA pA qA A A A A A A A A A A A A A A A ȼȮȼИȼvȼИb &jč >*B*UmH nH ph u jG UmH nH u &jʌ >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jM UmH nH u j UmH nH umH nH u j 0J UmH nH u &jЋ >*B*UmH nH ph u 0J mH nH u mH nH u &A A A A B B B B B B B #B $B %B &B RB SB TB nB oB pB rB sB tB uB vB wB B B B B B B B B B B B B B B кввквvвhк j5 UmH nH u &j >*B*UmH nH ph u j; UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u jA UmH nH u mH nH u j UmH nH u (B B B C C
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@ @ *@ +@ ,@ -@ j@ k@ l@ @ @ @ @ @ @ @ @ @ ѻѳѳѻѳwѳiѻѳ jS UmH nH u &j֊ >*B*UmH nH ph u jY UmH nH u &j܉ >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj_ UmH nH u mH nH u)@ @ @ @ @ @ @ @ A A A A A A A A A %A &A 'A (A oA pA qA A A A A A A A A A A A A A A A ȼȮȼИȼvȼИb &jč >*B*UmH nH ph u jG UmH nH u &jʌ >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jM UmH nH u j UmH nH umH nH u j 0J UmH nH u &jЋ >*B*UmH nH ph u 0J mH nH u mH nH u &A A A A B B B B B B B #B $B %B &B RB SB TB nB oB pB rB sB tB uB vB wB B B B B B B B B B B B B B B кввквvвhк j5 UmH nH u &j >*B*UmH nH ph u j; UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u jA UmH nH u mH nH u j UmH nH u (B B B C C
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C C MC NC OC iC jC kC mC nC oC pC qC rC C C C C C C C C C C C C C C C C C C C C ɽɯɽɽwɽc &j >*B*UmH nH ph u j) UmH nH u &j >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u j/ UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&C &D 'D (D BD CD DD FD GD HD ID JD KD gD hD iD jD D D D D D D D D D D D D D D D D E E E /E 0E 1E 3E 4E ȲȲvh j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j# UmH nH u j UmH nH umH nH u 0J mH nH u (4E 5E 6E 7E 8E TE UE VE WE ~E E E E E E E E E E E E E E E E E E E F F
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C C MC NC OC iC jC kC mC nC oC pC qC rC C C C C C C C C C C C C C C C C C C C C ɽɯɽɽwɽc &j >*B*UmH nH ph u j) UmH nH u &j >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u j/ UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&C &D 'D (D BD CD DD FD GD HD ID JD KD gD hD iD jD D D D D D D D D D D D D D D D D E E E /E 0E 1E 3E 4E ȲȲvh j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j# UmH nH u j UmH nH umH nH u 0J mH nH u (4E 5E 6E 7E 8E TE UE VE WE ~E E E E E E E E E E E E E E E E E E E F F
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F F
F F F F F -F .F ջճՅճw j UmH nH u &j >*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&.F /F 0F VF WF XF rF sF tF vF wF xF yF zF {F F F F F F F F F F F F F F F F F G G G G :G ;G *B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j >*B*UmH nH ph u&F yF F ]G G ?H H I I I AJ J &K K L L L ;L
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F F
F F F F F -F .F ջճՅճw j UmH nH u &j >*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&.F /F 0F VF WF XF rF sF tF vF wF xF yF zF {F F F F F F F F F F F F F F F F F G G G G :G ;G *B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j >*B*UmH nH ph u&F yF F ]G G ?H H I I I AJ J &K K L L L ;L
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VG WG XG ZG [G \G ]G ^G _G {G |G }G ~G G G G G G G G G G G G G G G G G H H H 8H 9H :H H ?H @H AH ]H ѻѳѳދѻѳwѳiѻѳ j UmH nH u &jp >*B*UmH nH ph u j UmH nH u &jv >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)]H ^H _H `H H H H H H H H H H H H H H H H H H H H I I
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VG WG XG ZG [G \G ]G ^G _G {G |G }G ~G G G G G G G G G G G G G G G G G H H H 8H 9H :H H ?H @H AH ]H ѻѳѳދѻѳwѳiѻѳ j UmH nH u &jp >*B*UmH nH ph u j UmH nH u &jv >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)]H ^H _H `H H H H H H H H H H H H H H H H H H H H I I
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I I
I I I I I -I .I /I 0I `I aI bI δ֞v֞b &j^ >*B*UmH nH ph u j UmH nH u &jd >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &jj >*B*UmH nH ph u 0J mH nH u &bI |I }I ~I I I I I I I I I I I I I I I I I I I I I I I I J J J J J J :J ;J J ?J @J AJ BJ CJ ѻѳѳѻѳwѳiѻѳ jϠ UmH nH u &jR >*B*UmH nH ph u j՟ UmH nH u &jX >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj۞ UmH nH u mH nH u)CJ _J `J aJ bJ J J J J J J J J J J J J J J J J K K K K K !K #K $K %K &K 'K (K DK EK FK GK K K ȼȮȼИȼvȼИb &j@ >*B*UmH nH ph u jâ UmH nH u &jF >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jɡ UmH nH u j UmH nH umH nH u j 0J UmH nH u &jL >*B*UmH nH ph u 0J mH nH u mH nH u &K K K K K K K K K K K K K K K K K K L L L L L L L L *B*UmH nH ph u j Uj UmH nH u &j: >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH u mH nH u j UmH nH u 'L L L L L L L L L L L L L M M M .M /M 0M 1M 2M 3M 4M 5M 6M RM SM TM UM M M M M M M M M M M M M M ѻѳѳދѻѳwѳiѻѳ j UmH nH u &j( >*B*UmH nH ph u j UmH nH u &j. >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)M M M M N N N N N N N N !N "N #N $N @N AN BN CN `N aN bN |N }N ~N N N N N N N N N N N N N N δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j" >*B*UmH nH ph u 0J mH nH u &N N N N N N N N N N O
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I I I I I -I .I /I 0I `I aI bI δ֞v֞b &j^ >*B*UmH nH ph u j UmH nH u &jd >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &jj >*B*UmH nH ph u 0J mH nH u &bI |I }I ~I I I I I I I I I I I I I I I I I I I I I I I I J J J J J J :J ;J J ?J @J AJ BJ CJ ѻѳѳѻѳwѳiѻѳ jϠ UmH nH u &jR >*B*UmH nH ph u j՟ UmH nH u &jX >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj۞ UmH nH u mH nH u)CJ _J `J aJ bJ J J J J J J J J J J J J J J J J K K K K K !K #K $K %K &K 'K (K DK EK FK GK K K ȼȮȼИȼvȼИb &j@ >*B*UmH nH ph u jâ UmH nH u &jF >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jɡ UmH nH u j UmH nH umH nH u j 0J UmH nH u &jL >*B*UmH nH ph u 0J mH nH u mH nH u &K K K K K K K K K K K K K K K K K K L L L L L L L L *B*UmH nH ph u j Uj UmH nH u &j: >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH u mH nH u j UmH nH u 'L L L L L L L L L L L L L M M M .M /M 0M 1M 2M 3M 4M 5M 6M RM SM TM UM M M M M M M M M M M M M M ѻѳѳދѻѳwѳiѻѳ j UmH nH u &j( >*B*UmH nH ph u j UmH nH u &j. >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)M M M M N N N N N N N N !N "N #N $N @N AN BN CN `N aN bN |N }N ~N N N N N N N N N N N N N N δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j" >*B*UmH nH ph u 0J mH nH u &N N N N N N N N N N O
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R R R :R ;R *B*UmH nH ph u j] UmH nH u &j >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jc UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&S \S ]S ^S xS yS zS |S }S ~S S S S S S S S S S S S S S S S S S S S T T T T GT HT IT cT dT eT gT hT ȲȲvh jK UmH nH u &jε >*B*UmH nH ph u jQ UmH nH u &jԴ >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u jW UmH nH u j UmH nH umH nH u 0J mH nH u (hT iT jT kT lT T T T T T T T T T T T T T T T T T T T U 8U 9U :U TU UU VU XU YU ZU [U \U ]U yU zU ջճՅճw j? UmH nH u &j· >*B*UmH nH ph u jE UmH nH u j UmH nH umH nH u &jȶ >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&zU {U |U U U U U U U U U U U U U U U U U yV zV {V V V V V V V V V V V V V V V V V W ϵߟיׅwߟיc &j >*B*UmH nH ph u j3 UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j9 UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j >*B*UmH nH ph u&W W W
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R R R :R ;R *B*UmH nH ph u j] UmH nH u &j >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jc UmH nH u j UmH nH umH nH u &j >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&S \S ]S ^S xS yS zS |S }S ~S S S S S S S S S S S S S S S S S S S S T T T T GT HT IT cT dT eT gT hT ȲȲvh jK UmH nH u &jε >*B*UmH nH ph u jQ UmH nH u &jԴ >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u jW UmH nH u j UmH nH umH nH u 0J mH nH u (hT iT jT kT lT T T T T T T T T T T T T T T T T T T T U 8U 9U :U TU UU VU XU YU ZU [U \U ]U yU zU ջճՅճw j? UmH nH u &j· >*B*UmH nH ph u jE UmH nH u j UmH nH umH nH u &jȶ >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&zU {U |U U U U U U U U U U U U U U U U U yV zV {V V V V V V V V V V V V V V V V V W ϵߟיׅwߟיc &j >*B*UmH nH ph u j3 UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j9 UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j >*B*UmH nH ph u&W W W
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X X X CX DX EX _X `X aX cX dX eX fX gX hX X X X X X X X X X X X X X X X X Y Y Y Y BY CY DY δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u &DY ^Y _Y `Y bY cY dY eY fY gY Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y *Z +Z ,Z FZ GZ HZ JZ KZ LZ MZ NZ OZ ѻѳѳѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj UmH nH u mH nH u)OZ kZ lZ mZ nZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z [
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W W W +W ,W -W .W ZW [W \W vW wW xW zW {W |W }W ~W W W W W W W W W W W W W W W W W W X ѻѳѳދѻѳwѳiѻѳ j! UmH nH u &j >*B*UmH nH ph u j' UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj- UmH nH u) X
X X X CX DX EX _X `X aX cX dX eX fX gX hX X X X X X X X X X X X X X X X X Y Y Y Y BY CY DY δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u &DY ^Y _Y `Y bY cY dY eY fY gY Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y *Z +Z ,Z FZ GZ HZ JZ KZ LZ MZ NZ OZ ѻѳѳѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj UmH nH u mH nH u)OZ kZ lZ mZ nZ Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z [
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\ \ \ \ \ \ \ \ \ /\ 0\ 1\ 2\ b\ c\ d\ ~\ \ \ \ \ \ \ кввквvвhк j UmH nH u &jh >*B*UmH nH ph u j UmH nH u &jn >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH u mH nH u j UmH nH u (\ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ \ ] ]
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] ] '] (] )] C] D] E] G] H] I] J] K] L] h] i] j] k] ɽɯɽɽwɽc &jV >*B*UmH nH ph u j UmH nH u &j\ >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u &jb >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&k] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ^
^ ^ ^ ^ ^ ^ ^ ^ 1^ 2^ 3^ 4^ X^ Y^ Z^ t^ u^ v^ x^ y^ ȲȲvh j UmH nH u &jJ >*B*UmH nH ph u j UmH nH u &jP >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH u j UmH nH umH nH u 0J mH nH u (y^ z^ {^ |^ }^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ _ _ _ _ 5_ 6_ 7_ 9_ :_ ;_ <_ =_ >_ Z_ [_ ջճՅճw j UmH nH u &j> >*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &jD >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&^ {^ ^ <_ _ ` t` ` Oa a b b c c *d d d d d d 6f 7f Tf \g g g g h
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] ] '] (] )] C] D] E] G] H] I] J] K] L] h] i] j] k] ɽɯɽɽwɽc &jV >*B*UmH nH ph u j UmH nH u &j\ >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u &jb >*B*UmH nH ph u mH nH u0J mH nH uj 0J UmH nH u&k] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ] ^
^ ^ ^ ^ ^ ^ ^ ^ 1^ 2^ 3^ 4^ X^ Y^ Z^ t^ u^ v^ x^ y^ ȲȲvh j UmH nH u &jJ >*B*UmH nH ph u j UmH nH u &jP >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH u j UmH nH umH nH u 0J mH nH u (y^ z^ {^ |^ }^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ _ _ _ _ 5_ 6_ 7_ 9_ :_ ;_ <_ =_ >_ Z_ [_ ջճՅճw j UmH nH u &j> >*B*UmH nH ph u j UmH nH u j UmH nH umH nH u &jD >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u&^ {^ ^ <_ _ ` t` ` Oa a b b c c *d d d d d d 6f 7f Tf \g g g g h
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` &` '` (` )` Q` R` S` m` ϵߟיׅwߟיc &j, >*B*UmH nH ph u j UmH nH u &j2 >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j8 >*B*UmH nH ph u&m` n` o` q` r` s` t` u` v` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` a a a ,a -a .a Ha Ia Ja La Ma Na Oa Pa Qa ma ѻѳѳދѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j& >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)ma na oa pa a a a a a a a a a a a a a a a a a a a b b b b b b b !b "b >b ?b @b Ab vb wb xb δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u &xb b b b b b b b b b b b b b b b b c
c c c c c c c c 1c 2c 3c 4c ~c c c c c c c c c c c c ѻѳѳѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj UmH nH u mH nH u)c c c c c d d d #d $d %d 'd (d )d *d +d ,d Hd Id Jd Kd d d d d d d d d d d d d d e e Pk jk ȼȮȼИȼvȼИq jhj a
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` &` '` (` )` Q` R` S` m` ϵߟיׅwߟיc &j, >*B*UmH nH ph u j UmH nH u &j2 >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u 0J mH nH uj 0J UmH nH u &j8 >*B*UmH nH ph u&m` n` o` q` r` s` t` u` v` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` ` a a a ,a -a .a Ha Ia Ja La Ma Na Oa Pa Qa ma ѻѳѳދѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j& >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u mH nH u j UmH nH uj UmH nH u)ma na oa pa a a a a a a a a a a a a a a a a a a a b b b b b b b !b "b >b ?b @b Ab vb wb xb δ֞v֞b &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j UmH nH u j UmH nH umH nH u j 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u &xb b b b b b b b b b b b b b b b b c
c c c c c c c c 1c 2c 3c 4c ~c c c c c c c c c c c c ѻѳѳѻѳwѳiѻѳ j UmH nH u &j >*B*UmH nH ph u j UmH nH u &j >*B*UmH nH ph u mH nH u0J mH nH u*5;B* CJ OJ QJ aJ mH nH ph u j 0J UmH nH u j UmH nH uj UmH nH u mH nH u)c c c c c d d d #d $d %d 'd (d )d *d +d ,d Hd Id Jd Kd d d d d d d d d d d d d d e e Pk jk ȼȮȼИȼvȼИq jhj a
H ha j U j Ujs UmH nH u &j >*B*UmH nH ph u *5;B* CJ OJ QJ aJ mH nH ph u jy UmH nH u j UmH nH umH nH u j 0J UmH nH u &j >*B*UmH nH ph u 0J mH nH u mH nH u %h 'h _h h h h h i i Ei Qi gi ui i i i xj j j j j j "k Pk *^* h^`h
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 3 4 5 6 7 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P P Q R S T U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m m n o p q r s t u v w x y z { | } ~ C$ C$ C$ C$
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 C$ 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U C$ U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r C$ r s t u v w x y z { | } ~ C$
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 C$ 8 9 : ; < = > ? @ A B C D E F G H I J K L M N O P Q R S T U C$ U V W X Y Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r C$ r s t u v w x y z { | } ~ C$
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w w x y z { | } ~ C$ C$ C$ C$
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! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = = > ? @ A B C D E F G H I J K L M N O P Q R S T U V W X Y Z Z [ \ ] ^ _ ` a b c d e f g h i j k l m n o p q r s t u v w w x y z { | } ~ C$ C$ C$ C$
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o c 5 3 0 1 9 7 9 5 2 } D y K _ T o c 5 3 0 1 9 7 9 5 2 } D y K _ T o c 5 3 0 1 9 7 9 5 3 } D y K _ T o c 5 3 0 1 9 7 9 5 3 } D y K _ T o c 5 3 0 1 9 7 9 5 4 } D y K _ T o c 5 3 0 1 9 7 9 5 4 } D y K _ T o c 5 3 0 1 9 7 9 5 5 } D y K _ T o c 5 3 0 1 9 7 9 5 5 } D y K _ T o c 5 3 0 1 9 7 9 5 6 } D y K _ T o c 5 3 0 1 9 7 9 5 6 } D y K _ T o c 5 3 0 1 9 7 9 5 7 } D y K _ T o c 5 3 0 1 9 7 9 5 7 } D y K _ T o c 5 3 0 1 9 7 9 5 8 } D y K _ T o c 5 3 0 1 9 7 9 5 8 } D y K _ T o c 5 3 0 1 9 7 9 5 9 } D y K _ T o c 5 3 0 1 9 7 9 5 9 } D y K _ T o c 5 3 0 1 9 7 9 6 0 } D y K _ T o c 5 3 0 1 9 7 9 6 0 } D y K _ T o c 5 3 0 1 9 7 9 6 1 } D y K _ T o c 5 3 0 1 9 7 9 6 1 } D y K _ T o c 5 3 0 1 9 7 9 6 2 } D y K _ T o c 5 3 0 1 9 7 9 6 2 } D y K _ T o c 5 3 0 1 9 7 9 6 3 } D y K _ T o c 5 3 0 1 9 7 9 6 3 } D y K _ T o c 5 3 0 1 9 7 9 6 4 } D y K _ T o c 5 3 0 1 9 7 9 6 4 } D y K _ T o c 5 3 0 1 9 7 9 6 5 } D y K _ T o c 5 3 0 1 9 7 9 6 5 } D y K _ T o c 5 3 0 1 9 7 9 6 6 } D y K _ T o c 5 3 0 1 9 7 9 6 6 } D y K _ T o c 5 3 0 1 9 7 9 6 7 } D y K _ T o c 5 3 0 1 9 7 9 6 7 } D y K _ T o c 5 3 0 1 9 7 9 6 8 } D y K _ T o c 5 3 0 1 9 7 9 6 8 } D y K _ T o c 5 3 0 1 9 7 9 6 9 } D y K _ T o c 5 3 0 1 9 7 9 6 9 } D y K _ T o c 5 3 0 1 9 7 9 7 0 } D y K _ T o c 5 3 0 1 9 7 9 7 0 } D y K _ T o c 5 3 0 1 9 7 9 7 1 } D y K _ T o c 5 3 0 1 9 7 9 7 1 } D y K _ T o c 5 3 0 1 9 7 9 7 2 } D y K _ T o c 5 3 0 1 9 7 9 7 2 } D y K _ T o c 5 3 0 1 9 7 9 7 3 } D y K _ T o c 5 3 0 1 9 7 9 7 3 } D y K _ T o c 5 3 0 1 9 7 9 7 4 } D y K _ T o c 5 3 0 1 9 7 9 7 4 } D y K _ T o c 5 3 0 1 9 7 9 7 5 } D y K _ T o c 5 3 0 1 9 7 9 7 5 } D y K _ T o c 5 3 0 1 9 7 9 7 6 } D y K _ T o c 5 3 0 1 9 7 9 7 6 } D y K _ T o c 5 3 0 1 9 7 9 7 7 } D y K _ T o c 5 3 0 1 9 7 9 7 7 } D y K _ T o c 5 3 0 1 9 7 9 7 8 } D y K _ T o c 5 3 0 1 9 7 9 7 8 } D y K _ T o c 5 3 0 1 9 7 9 7 9 } D y K _ T o c 5 3 0 1 9 7 9 7 9 } D y K _ T o c 5 3 0 1 9 7 9 8 0 } D y K _ T o c 5 3 0 1 9 7 9 8 0 } D y K _ T o c 5 3 0 1 9 7 9 8 1 } D y K _ T o c 5 3 0 1 9 7 9 8 1 } D y K _ T o c 5 3 0 1 9 7 9 8 2 } D y K _ T o c 5 3 0 1 9 7 9 8 2 } D y K _ T o c 5 3 0 1 9 7 9 8 3 } D y K _ T o c 5 3 0 1 9 7 9 8 3 } D y K _ T o c 5 3 0 1 9 7 9 8 4 } D y K _ T o c 5 3 0 1 9 7 9 8 4 } D y K _ T o c 5 3 0 1 9 7 9 8 5 } D y K _ T o c 5 3 0 1 9 7 9 8 5 } D y K _ T o c 5 3 0 1 9 7 9 8 6 } D y K _ T o c 5 3 0 1 9 7 9 8 6 } D y K _ T o c 5 3 0 1 9 7 9 8 7 } D y K _ T o c 5 3 0 1 9 7 9 8 7 } D y K _ T o c 5 3 0 1 9 7 9 8 8 } D y K _ T o c 5 3 0 1 9 7 9 8 8 } D y K _ T o c 5 3 0 1 9 7 9 8 9 } D y K _ T o c 5 3 0 1 9 7 9 8 9 } D y K _ T o c 5 3 0 1 9 7 9 9 0 } D y K _ T o c 5 3 0 1 9 7 9 9 0 } D y K _ T o c 5 3 0 1 9 7 9 9 1 } D y K _ T o c 5 3 0 1 9 7 9 9 1 } D y K _ T o c 5 3 0 1 9 7 9 9 2 } D y K _ T o c 5 3 0 1 9 7 9 9 2 } D y K _ T o c 5 3 0 1 9 7 9 9 3 } D y K _ T o c 5 3 0 1 9 7 9 9 3 } D y K _ T o c 5 3 0 1 9 7 9 9 4 } D y K _ T o c 5 3 0 1 9 7 9 9 4 } D y K _ T o c 5 3 0 1 9 7 9 9 5 } D y K _ T o c 5 3 0 1 9 7 9 9 5 } D y K _ T o c 5 3 0 1 9 7 9 9 6 } D y K _ T o c 5 3 0 1 9 7 9 9 6 } D y K _ T o c 5 3 0 1 9 7 9 9 7 } D y K _ T o c 5 3 0 1 9 7 9 9 7 } D y K _ T o c 5 3 0 1 9 7 9 9 8 } D y K _ T o c 5 3 0 1 9 7 9 9 8 } D y K _ T o c 5 3 0 1 9 7 9 9 9 } D y K _ T o c 5 3 0 1 9 7 9 9 9 } D y K _ T o c 5 3 0 1 9 8 0 0 0 } D y K _ T o c 5 3 0 1 9 8 0 0 0 } D y K _ T o c 5 3 0 1 9 8 0 0 1 } D y K _ T o c 5 3 0 1 9 8 0 0 1 } D y K _ T o c 5 3 0 1 9 8 0 0 2 } D y K _ T o c 5 3 0 1 9 8 0 0 2 } D y K _ T o c 5 3 0 1 9 8 0 0 3 } D y K _ T o c 5 3 0 1 9 8 0 0 3 } D y K _ T o c 5 3 0 1 9 8 0 0 4 } D y K _ T o c 5 3 0 1 9 8 0 0 4 } D y K _ T o c 5 3 0 1 9 8 0 0 5 } D y K _ T o c 5 3 0 1 9 8 0 0 5 } D y K _ T o c 5 3 0 1 9 8 0 0 6 } D y K _ T o c 5 3 0 1 9 8 0 0 6 } D y K _ T o c 5 3 0 1 9 8 0 0 7 } D y K _ T o c 5 3 0 1 9 8 0 0 7 } D y K _ T o c 5 3 0 1 9 8 0 0 8 } D y K _ T o c 5 3 0 1 9 8 0 0 8 } D y K _ T o c 5 3 0 1 9 8 0 0 9 } D y K _ T o c 5 3 0 1 9 8 0 0 9 } D y K _ T o c 5 3 0 1 9 8 0 1 0 } D y K _ T o c 5 3 0 1 9 8 0 1 0 } D y K _ T o c 5 3 0 1 9 8 0 1 1 } D y K _ T o c 5 3 0 1 9 8 0 1 1 } D y K _ T o c 5 3 0 1 9 8 0 1 2 } D y K _ T o c 5 3 0 1 9 8 0 1 2 } D y K _ T o c 5 3 0 1 9 8 0 1 3 } D y K _ T o c 5 3 0 1 9 8 0 1 3 } D y K _ T o c 5 3 0 1 9 8 0 1 4 } D y K _ T o c 5 3 0 1 9 8 0 1 4 } D y K _ T o c 5 3 0 1 9 8 0 1 5 } D y K _ T o c 5 3 0 1 9 8 0 1 5 } D y K _ T o c 5 3 0 1 9 8 0 1 6 } D y K _ T o c 5 3 0 1 9 8 0 1 6 } D y K _ T o c 5 3 0 1 9 8 0 1 7 } D y K _ T o c 5 3 0 1 9 8 0 1 7 } D y K _ T o c 5 3 0 1 9 8 0 1 8 } D y K _ T o c 5 3 0 1 9 8 0 1 8 } D y K _ T o c 5 3 0 1 9 8 0 1 9 } D y K _ T o c 5 3 0 1 9 8 0 1 9 } D y K _ T o c 5 3 0 1 9 8 0 2 0 } D y K _ T o c 5 3 0 1 9 8 0 2 0 } D y K _ T o c 5 3 0 1 9 8 0 2 1 } D y K _ T o c 5 3 0 1 9 8 0 2 1 } D y K _ T o c 5 3 0 1 9 8 0 2 2 } D y K _ T o c 5 3 0 1 9 8 0 2 2 } D y K _ T o c 5 3 0 1 9 8 0 2 3 } D y K _ T o c 5 3 0 1 9 8 0 2 3 } D y K _ T o c 5 3 0 1 9 8 0 2 4 } D y K _ T o c 5 3 0 1 9 8 0 2 4 } D y K _ T o c 5 3 0 1 9 8 0 2 5 } D y K _ T o c 5 3 0 1 9 8 0 2 5 } D y K _ T o c 5 3 0 1 9 8 0 2 6 } D y K _ T o c 5 3 0 1 9 8 0 2 6 } D y K _ T o c 5 3 0 1 9 8 0 2 7 } D y K _ T o c 5 3 0 1 9 8 0 2 7 } D y K _ T o c 5 3 0 1 9 8 0 2 8 } D y K _ T o c 5 3 0 1 9 8 0 2 8 } D y K _ T o c 5 3 0 1 9 8 0 2 9 } D y K _ T o c 5 3 0 1 9 8 0 2 9 } D y K _ T o c 5 3 0 1 9 8 0 3 0 } D y K _ T o c 5 3 0 1 9 8 0 3 0 } D y K _ T o c 5 3 0 1 9 8 0 3 1 } D y K _ T o c 5 3 0 1 9 8 0 3 1 } D y K _ T o c 5 3 0 1 9 8 0 3 2 } D y K _ T o c 5 3 0 1 9 8 0 3 2 } D y K _ T o c 5 3 0 1 9 8 0 3 3 } D y K _ T o c 5 3 0 1 9 8 0 3 3 } D y K _ T o c 5 3 0 1 9 8 0 3 4 } D y K _ T o c 5 3 0 1 9 8 0 3 4 } D y K _ T o c 5 3 0 1 9 8 0 3 5 } D y K _ T o c 5 3 0 1 9 8 0 3 5 } D y K _ T o c 5 3 0 1 9 8 0 3 6 } D y K _ T o c 5 3 0 1 9 8 0 3 6 } D y K _ T o c 5 3 0 1 9 8 0 3 7 } D y K _ T o c 5 3 0 1 9 8 0 3 7 } D y K _ T o c 5 3 0 1 9 8 0 3 8 } D y K _ T o c 5 3 0 1 9 8 0 3 8 } D y K _ T o c 5 3 0 1 9 8 0 3 9 } D y K _ T o c 5 3 0 1 9 8 0 3 9 } D y K _ T o c 5 3 0 1 9 8 0 4 0 } D y K _ T o c 5 3 0 1 9 8 0 4 0 } D y K _ T o c 5 3 0 1 9 8 0 4 1 } D y K _ T o c 5 3 0 1 9 8 0 4 1 } D y K _ T o c 5 3 0 1 9 8 0 4 2 } D y K _ T o c 5 3 0 1 9 8 0 4 2 } D y K _ T o c 5 3 0 1 9 8 0 4 3 } D y K _ T o c 5 3 0 1 9 8 0 4 3 } D y K _ T o c 5 3 0 1 9 8 0 4 4 } D y K _ T o c 5 3 0 1 9 8 0 4 4 } D y K _ T o c 5 3 0 1 9 8 0 4 5 } D y K _ T o c 5 3 0 1 9 8 0 4 5 } D y K _ T o c 5 3 0 1 9 8 0 4 6 } D y K _ T o c 5 3 0 1 9 8 0 4 6 } D y K _ T o c 5 3 0 1 9 8 0 4 7 } D y K _ T o c 5 3 0 1 9 8 0 4 7 } D y K _ T o c 5 3 0 1 9 8 0 4 8 } D y K _ T o c 5 3 0 1 9 8 0 4 8 } D y K _ T o c 5 3 0 1 9 8 0 4 9 } D y K _ T o c 5 3 0 1 9 8 0 4 9 } D y K _ T o c 5 3 0 1 9 8 0 5 0 } D y K _ T o c 5 3 0 1 9 8 0 5 0 } D y K _ T o c 5 3 0 1 9 8 0 5 1 } D y K _ T o c 5 3 0 1 9 8 0 5 1 } D y K _ T o c 5 3 0 1 9 8 0 5 2 } D y K _ T o c 5 3 0 1 9 8 0 5 2 } D y K _ T o c 5 3 0 1 9 8 0 5 3 } D y K _ T o c 5 3 0 1 9 8 0 5 3 } D y K _ T o c 5 3 0 1 9 8 0 5 4 } D y K _ T o c 5 3 0 1 9 8 0 5 4 } D y K _ T o c 5 3 0 1 9 8 0 5 5 } D y K _ T o c 5 3 0 1 9 8 0 5 5 } D y K _ T o c 5 3 0 1 9 8 0 5 6 } D y K _ T o c 5 3 0 1 9 8 0 5 6 } D y K _ T o c 5 3 0 1 9 8 0 5 7 } D y K _ T o c 5 3 0 1 9 8 0 5 7 } D y K _ T o c 5 3 0 1 9 8 0 5 8 } D y K _ T o c 5 3 0 1 9 8 0 5 8 } D y K _ T o c 5 3 0 1 9 8 0 5 9 } D y K _ T o c 5 3 0 1 9 8 0 5 9 } D y K _ T o c 5 3 0 1 9 8 0 6 0 } D y K _ T o c 5 3 0 1 9 8 0 6 0 } D y K _ T o c 5 3 0 1 9 8 0 6 1 } D y K _ T o c 5 3 0 1 9 8 0 6 1 } D y K _ T o c 5 3 0 1 9 8 0 6 2 } D y K _ T o c 5 3 0 1 9 8 0 6 2 } D y K _ T o c 5 3 0 1 9 8 0 6 3 } D y K _ T o c 5 3 0 1 9 8 0 6 3 } D y K _ T o c 5 3 0 1 9 8 0 6 4 } D y K _ T o c 5 3 0 1 9 8 0 6 4 } D y K _ T o c 5 3 0 1 9 8 0 6 5 } D y K _ T o c 5 3 0 1 9 8 0 6 5 } D y K _ T o c 5 3 0 1 9 8 0 6 6 } D y K _ T o c 5 3 0 1 9 8 0 6 6 } D y K _ T o c 5 3 0 1 9 8 0 6 7 } D y K _ T o c 5 3 0 1 9 8 0 6 7 } D y K _ T o c 5 3 0 1 9 8 0 6 8 } D y K _ T o c 5 3 0 1 9 8 0 6 8 } D y K _ T o c 5 3 0 1 9 8 0 6 9 } D y K _ T o c 5 3 0 1 9 8 0 6 9 } D y K _ T o c 5 3 0 1 9 8 0 7 0 } D y K _ T o c 5 3 0 1 9 8 0 7 0 } D y K _ T o c 5 3 0 1 9 8 0 7 1 } D y K _ T o c 5 3 0 1 9 8 0 7 1 } D y K _ T o c 5 3 0 1 9 8 0 7 2 } D y K _ T o c 5 3 0 1 9 8 0 7 2 } D y K _ T o c 5 3 0 1 9 8 0 7 3 } D y K _ T o c 5 3 0 1 9 8 0 7 3 } D y K _ T o c 5 3 0 1 9 8 0 7 4 } D y K _ T o c 5 3 0 1 9 8 0 7 4 } D y K _ T o c 5 3 0 1 9 8 0 7 5 } D y K _ T o c 5 3 0 1 9 8 0 7 5 } D y K _ T o c 5 3 0 1 9 8 0 7 6 } D y K _ T o c 5 3 0 1 9 8 0 7 6 } D y K _ T o c 5 3 0 1 9 8 0 7 7 } D y K _ T o c 5 3 0 1 9 8 0 7 7 } D y K _ T o c 5 3 0 1 9 8 0 7 8 } D y K _ T o c 5 3 0 1 9 8 0 7 8 } D y K _ T o c 5 3 0 1 9 8 0 7 9 } D y K _ T o c 5 3 0 1 9 8 0 7 9 } D y K _ T o c 5 3 0 1 9 8 0 8 0 } D y K _ T o c 5 3 0 1 9 8 0 8 0 } D y K _ T o c 5 3 0 1 9 8 0 8 1 } D y K _ T o c 5 3 0 1 9 8 0 8 1 } D y K _ T o c 5 3 0 1 9 8 0 8 2 } D y K _ T o c 5 3 0 1 9 8 0 8 2 } D y K _ T o c 5 3 0 1 9 8 0 8 3 } D y K _ T o c 5 3 0 1 9 8 0 8 3 } D y K _ T o c 5 3 0 1 9 8 0 8 4 } D y K _ T o c 5 3 0 1 9 8 0 8 4 } D y K _ T o c 5 3 0 1 9 8 0 8 5 } D y K _ T o c 5 3 0 1 9 8 0 8 5 } D y K _ T o c 5 3 0 1 9 8 0 8 6 } D y K _ T o c 5 3 0 1 9 8 0 8 6 } D y K _ T o c 5 3 0 1 9 8 0 8 7 } D y K _ T o c 5 3 0 1 9 8 0 8 7 } D y K _ T o c 5 3 0 1 9 8 0 8 8 } D y K _ T o c 5 3 0 1 9 8 0 8 8 } D y K _ T o c 5 3 0 1 9 8 0 8 9 } D y K _ T o c 5 3 0 1 9 8 0 8 9 } D y K _ T o c 5 3 0 1 9 8 0 9 0 } D y K _ T o c 5 3 0 1 9 8 0 9 0 } D y K _ T o c 5 3 0 1 9 8 0 9 1 } D y K _ T o c 5 3 0 1 9 8 0 9 1 } D y K _ T o c 5 3 0 1 9 8 0 9 2 } D y K _ T o c 5 3 0 1 9 8 0 9 2 } D y K _ T o c 5 3 0 1 9 8 0 9 3 } D y K _ T o c 5 3 0 1 9 8 0 9 3 } D y K _ T o c 5 3 0 1 9 8 0 9 4 } D y K _ T o c 5 3 0 1 9 8 0 9 4 } D y K _ T o c 5 3 0 1 9 8 0 9 5 } D y K _ T o c 5 3 0 1 9 8 0 9 5 } D y K _ T o c 5 3 0 1 9 8 0 9 6 } D y K _ T o c 5 3 0 1 9 8 0 9 6 } D y K _ T o c 5 3 0 1 9 8 0 9 7 } D y K _ T o c 5 3 0 1 9 8 0 9 7 } D y K _ T o c 5 3 0 1 9 8 0 9 8 } D y K _ T o c 5 3 0 1 9 8 0 9 8 } D y K _ T o c 5 3 0 1 9 8 0 9 9 } D y K _ T o c 5 3 0 1 9 8 0 9 9 } D y K _ T o c 5 3 0 1 9 8 1 0 0 } D y K _ T o c 5 3 0 1 9 8 1 0 0 } D y K _ T o c 5 3 0 1 9 8 1 0 1 } D y K _ T o c 5 3 0 1 9 8 1 0 1 } D y K _ T o c 5 3 0 1 9 8 1 0 2 } D y K _ T o c 5 3 0 1 9 8 1 0 2 } D y K _ T o c 5 3 0 1 9 8 1 0 3 } D y K _ T o c 5 3 0 1 9 8 1 0 3 } D y K _ T o c 5 3 0 1 9 8 1 0 4 } D y K _ T o c 5 3 0 1 9 8 1 0 4 } D y K _ T o c 5 3 0 1 9 8 1 0 5 } D y K _ T o c 5 3 0 1 9 8 1 0 5 } D y K _ T o c 5 3 0 1 9 8 1 0 6 } D y K _ T o c 5 3 0 1 9 8 1 0 6 } D y K _ T o c 5 3 0 1 9 8 1 0 7 } D y K _ T o c 5 3 0 1 9 8 1 0 7 } D y K _ T o c 5 3 0 1 9 8 1 0 8 } D y K _ T o c 5 3 0 1 9 8 1 0 8 } D y K _ T o c 5 3 0 1 9 8 1 0 9 } D y K _ T o c 5 3 0 1 9 8 1 0 9 } D y K _ T o c 5 3 0 1 9 8 1 1 0 } D y K _ T o c 5 3 0 1 9 8 1 1 0 } D y K _ R e f 5 2 7 7 4 0 8 9 0 } D y K _ R e f 5 1 4 0 0 1 6 0 0 } D y K _ R e f 5 1 4 0 0 6 5 2 0 } D y K _ R e f 5 1 4 0 0 7 8 1 2 } D y K _ R e f 5 1 4 0 0 7 8 1 2 } D y K _ R e f 5 2 8 2 2 4 0 2 4 } D y K _ R e f 5 2 8 2 2 3 1 2 8 } D y K _ R e f 5 2 7 7 4 5 1 6 1 u D y K
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4ѩ ҉N{ ftrV.=JH+#OӵRAz Rg;E5o(w <8X)' 73ۺMu>ٶn&mƶOW,:k#y]6*6x9 7"zh[T˳Ulmwr['R\)s[)G:P/7GT.- $J;' [[qmHxkd`j|:@ D|w*vӦ~vgn7 7|.\P0 s{9YM܊ i w D y K _ T o c 1 5 6 1 4 1 w D y K _ T o c 1 5 6 1 4 1 w D y K _ T o c 1 5 6 1 4 2 w D y K _ T o c 1 5 6 1 4 2 w D y K _ T o c 1 5 6 1 4 3 w D y K _ T o c 1 5 6 1 4 3 w D y K _ T o c 1 5 6 1 4 4 w D y K _ T o c 1 5 6 1 4 4 w D y K _ T o c 1 5 6 1 4 5 w D y K _ T o c 1 5 6 1 4 5 w D y K _ T o c 1 5 6 1 4 6 w D y K _ T o c 1 5 6 1 4 6 w D y K _ T o c 1 5 6 1 4 7 w D y K _ T o c 1 5 6 1 4 7 w D y K _ T o c 1 5 6 1 4 8 w D y K _ T o c 1 5 6 1 4 8 w D y K _ T o c 1 5 6 1 4 9 w D y K _ T o c 1 5 6 1 4 9 w D y K _ T o c 1 5 6 1 5 0 w D y K _ T o c 1 5 6 1 5 0 w D y K _ T o c 1 5 6 1 5 1 w D y K _ T o c 1 5 6 1 5 1 w D y K _ T o c 1 5 6 1 5 2 w D y K _ T o c 1 5 6 1 5 2 w D y K _ T o c 1 5 6 1 5 3 w D y K _ T o c 1 5 6 1 5 3 w D y K _ T o c 1 5 6 1 5 4 w D y K _ T o c 1 5 6 1 5 4 w D y K _ T o c 1 5 6 1 5 5 w D y K _ T o c 1 5 6 1 5 5 w D y K _ T o c 1 5 6 1 5 6 w D y K _ T o c 1 5 6 1 5 6 w D y K _ T o c 1 5 6 1 5 7 w D y K _ T o c 1 5 6 1 5 7 w D y K _ T o c 1 5 6 1 5 8 w D y K _ T o c 1 5 6 1 5 8 w D y K _ T o c 1 5 6 1 5 9 w D y K _ T o c 1 5 6 1 5 9 w D y K _ T o c 1 5 6 1 6 0 w D y K _ T o c 1 5 6 1 6 0 w D y K _ T o c 1 5 6 1 6 1 w D y K _ T o c 1 5 6 1 6 1 w D y K _ T o c 1 5 6 1 6 2 w D y K _ T o c 1 5 6 1 6 2 w D y K _ T o c 1 5 6 1 6 3 w D y K _ T o c 1 5 6 1 6 3 w D y K _ T o c 1 5 6 1 6 4 w D y K _ T o c 1 5 6 1 6 4 w D y K _ T o c 1 5 6 1 6 5 w D y K _ T o c 1 5 6 1 6 5 w D y K _ T o c 1 5 6 1 6 6 w D y K _ T o c 1 5 6 1 6 6 w D y K _ T o c 1 5 6 1 6 7 w D y K _ T o c 1 5 6 1 6 7 w D y K _ T o c 1 5 6 1 6 8 w D y K _ T o c 1 5 6 1 6 8 w D y K _ T o c 1 5 6 1 6 9 w D y K _ T o c 1 5 6 1 6 9 w D y K _ T o c 1 5 6 1 7 0 w D y K _ T o c 1 5 6 1 7 0 w D y K _ T o c 1 5 6 1 7 1 w D y K _ T o c 1 5 6 1 7 1 w D y K _ T o c 1 5 6 1 7 2 w D y K _ T o c 1 5 6 1 7 2 w D y K _ T o c 1 5 6 1 7 3 w D y K _ T o c 1 5 6 1 7 3 w D y K _ T o c 1 5 6 1 7 4 w D y K _ T o c 1 5 6 1 7 4 w D y K _ T o c 1 5 6 1 7 5 w D y K _ T o c 1 5 6 1 7 5 w D y K _ T o c 1 5 6 1 7 6 w D y K _ T o c 1 5 6 1 7 6 w D y K _ T o c 1 5 6 1 7 7 w D y K _ T o c 1 5 6 1 7 7 w D y K _ T o c 1 5 6 1 7 8 w D y K _ T o c 1 5 6 1 7 8 w D y K _ T o c 1 5 6 1 7 9 w D y K _ T o c 1 5 6 1 7 9 w D y K _ T o c 1 5 6 1 8 0 w D y K _ T o c 1 5 6 1 8 0 w D y K _ T o c 1 5 6 1 8 1 w D y K _ T o c 1 5 6 1 8 1 w D y K _ T o c 1 5 6 1 8 2 w D y K _ T o c 1 5 6 1 8 2 w D y K _ T o c 1 5 6 1 8 3 w D y K _ T o c 1 5 6 1 8 3 w D y K _ T o c 1 5 6 1 8 4 w D y K _ T o c 1 5 6 1 8 4 w D y K _ T o c 1 5 6 1 8 5 w D y K _ T o c 1 5 6 1 8 5 w D y K _ T o c 1 5 6 1 8 6 w D y K _ T o c 1 5 6 1 8 6 w D y K _ T o c 1 5 6 1 8 7 w D y K _ T o c 1 5 6 1 8 7 w D y K _ T o c 1 5 6 1 8 8 w D y K _ T o c 1 5 6 1 8 8 w D y K _ T o c 1 5 6 1 8 9 w D y K _ T o c 1 5 6 1 8 9 w D y K _ T o c 1 5 6 1 9 0 w D y K _ T o c 1 5 6 1 9 0 w D y K _ T o c 1 5 6 1 9 1 w D y K _ T o c 1 5 6 1 9 1 w D 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1 9 8 0 6 9 } D y K _ T o c 5 3 0 1 9 8 0 7 0 } D y K _ T o c 5 3 0 1 9 8 0 7 0 } D y K _ T o c 5 3 0 1 9 8 0 7 1 } D y K _ T o c 5 3 0 1 9 8 0 7 1 } D y K _ T o c 5 3 0 1 9 8 0 7 2 } D y K _ T o c 5 3 0 1 9 8 0 7 2 } D y K _ T o c 5 3 0 1 9 8 0 7 3 } D y K _ T o c 5 3 0 1 9 8 0 7 3 } D y K _ T o c 5 3 0 1 9 8 0 7 4 } D y K _ T o c 5 3 0 1 9 8 0 7 4 } D y K _ T o c 5 3 0 1 9 8 0 7 5 } D y K _ T o c 5 3 0 1 9 8 0 7 5 } D y K _ T o c 5 3 0 1 9 8 0 7 6 } D y K _ T o c 5 3 0 1 9 8 0 7 6 } D y K _ T o c 5 3 0 1 9 8 0 7 7 } D y K _ T o c 5 3 0 1 9 8 0 7 7 } D y K _ T o c 5 3 0 1 9 8 0 7 8 } D y K _ T o c 5 3 0 1 9 8 0 7 8 } D y K _ T o c 5 3 0 1 9 8 0 7 9 } D y K _ T o c 5 3 0 1 9 8 0 7 9 } D y K _ T o c 5 3 0 1 9 8 0 8 0 } D y K _ T o c 5 3 0 1 9 8 0 8 0 } D y K _ T o c 5 3 0 1 9 8 0 8 1 } D y K _ T o c 5 3 0 1 9 8 0 8 1 } D y K _ T o c 5 3 0 1 9 8 0 8 2 } D y K _ T o c 5 3 0 1 9 8 0 8 2 } D y K _ T o c 5 3 0 1 9 8 0 8 3 } D y K _ T o c 5 3 0 1 9 8 0 8 3 } D y K _ T o c 5 3 0 1 9 8 0 8 4 } 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|
M
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
N
|
N
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
O
|
O
|
3 ,-1? . ]' : ^' N B
|
3 ,-1? . ]' : ^' N B
|
P
|
P
|
3 ,-1? s ]' ^' N B
|
3 ,-1? s ]' ^' N B
|
Q
|
Q
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
R
|
R
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
S
|
S
|
3 ,-1? D ]' Q ^' N B
|
3 ,-1? D ]' Q ^' N B
|
T
|
T
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
U
|
U
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
V
|
V
|
3 ,-1? ]' " ^' N B
|
3 ,-1? ]' " ^' N B
|
W
|
W
|
3 ,-1? [ ]' g ^' N B
|
3 ,-1? [ ]' g ^' N B
|
X
|
X
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
Y
|
Y
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
Z
|
Z
|
3 ,-1? , ]' 8 ^' N B
|
3 ,-1? , ]' 8 ^' N B
|
[
|
[
|
3 ,-1? q ]' ~ ^' N B
|
3 ,-1? q ]' ~ ^' N B
|
\
|
\
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
]
|
]
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
^
|
^
|
3 ,-1? B ]' O ^' N B
|
3 ,-1? B ]' O ^' N B
|
_
|
_
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
`
|
`
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
a
|
a
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
b
|
b
|
3 ,-1? Y ]' f ^' N B
|
3 ,-1? Y ]' f ^' N B
|
c
|
c
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
d
|
d
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
e
|
e
|
3 ,-1? * ]' 6 ^' N B
|
3 ,-1? * ]' 6 ^' N B
|
f
|
f
|
3 ,-1? o ]' | ^' N B
|
3 ,-1? o ]' | ^' N B
|
g
|
g
|
3 ,-1? ]' ^' N B
|
3 ,-1? ]' ^' N B
|
h
|
h
|
3 ,-1? ]' ! ^' N B
|
3 ,-1? ]' ! ^' N B
|
i
|
i
|
3 ,-1? @! ]' M! ^' N B
|
3 ,-1? @! ]' M! ^' N B
|
j
|
j
|
3 ,-1? ! ]' ! ^' N B
|
3 ,-1? ! ]' ! ^' N B
|
k
|
k
|
3 ,-1? ! ]' ! ^' N B
|
3 ,-1? ! ]' ! ^' N B
|
l
|
l
|
3 ,-1? " ]' " ^' N B
|
3 ,-1? " ]' " ^' N B
|
m
|
m
|
3 ,-1? W" ]' d" ^' N B
|
3 ,-1? W" ]' d" ^' N B
|
n
|
n
|
3 ,-1? " ]' " ^' N B
|
3 ,-1? " ]' " ^' N B
|
o
|
o
|
3 ,-1? " ]' " ^' N B
|
3 ,-1? " ]' " ^' N B
|
p
|
p
|
3 ,-1? (# ]' 5# ^' N B
|
3 ,-1? (# ]' 5# ^' N B
|
q
|
q
|
3 ,-1? n# ]' z# ^' N B
|
3 ,-1? n# ]' z# ^' N B
|
r
|
r
|
3 ,-1? # ]' # ^' N B
|
3 ,-1? # ]' # ^' N B
|
s
|
s
|
3 ,-1? # ]' $ ^' N B
|
3 ,-1? # ]' $ ^' N B
|
t
|
t
|
3 ,-1? ?$ ]' K$ ^' N B
|
3 ,-1? ?$ ]' K$ ^' N B
|
u
|
u
|
3 ,-1? $ ]' $ ^' N B
|
3 ,-1? $ ]' $ ^' N B
|
v
|
v
|
3 ,-1? $ ]' $ ^' N B
|
3 ,-1? $ ]' $ ^' N B
|
w
|
w
|
3 ,-1? % ]' % ^' N B
|
3 ,-1? % ]' % ^' N B
|
x
|
x
|
3 ,-1? U% ]' b% ^' N B
|
3 ,-1? U% ]' b% ^' N B
|
y
|
y
|
3 ,-1? % ]' % ^' N B
|
3 ,-1? % ]' % ^' N B
|
z
|
z
|
3 ,-1? % ]' % ^' N B
|
3 ,-1? % ]' % ^' N B
|
{
|
{
|
3 ,-1? && ]' 3& ^' N B
|
3 ,-1? && ]' 3& ^' N B
|
|
|
|
|
3 ,-1? l& ]' x& ^' N B
|
3 ,-1? l& ]' x& ^' N B
|
}
|
}
|
3 ,-1? & ]' & ^' N B
|
3 ,-1? & ]' & ^' N B
|
~
|
~
|
3 ,-1? & ]' ' ^' N B
|
3 ,-1? & ]' ' ^' N B
|
|
|
3 ,-1? =' ]' I' ^' N B
|
3 ,-1? =' ]' I' ^' N B
|
|
|
3 ,-1? ' ]' ' ^' N B
|
3 ,-1? ' ]' ' ^' N B
|
|
|
3 ,-1? ' ]' ' ^' N B
|
3 ,-1? ' ]' ' ^' N B
|
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|
3 ,-1? ( ]' ( ^' N B
|
3 ,-1? ( ]' ( ^' N B
|
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|
3 ,-1? S( ]' `( ^' N B
|
3 ,-1? S( ]' `( ^' N B
|
|
|
3 ,-1? ( ]' ( ^' N B
|
3 ,-1? ( ]' ( ^' N B
|
|
|
3 ,-1? ( ]' ( ^' N B
|
3 ,-1? ( ]' ( ^' N B
|
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|
3 ,-1? $) ]' 1) ^' N B
|
3 ,-1? $) ]' 1) ^' N B
|
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3 ,-1? j) ]' w) ^' N B
|
3 ,-1? j) ]' w) ^' N B
|
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|
3 ,-1? ) ]' ) ^' N B
|
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|
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|
3 ,-1? ) ]' * ^' N B
|
3 ,-1? ) ]' * ^' N B
|
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|
3 ,-1? ;* ]' G* ^' N B
|
3 ,-1? ;* ]' G* ^' N B
|
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|
3 ,-1? * ]' * ^' N B
|
3 ,-1? * ]' * ^' N B
|
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|
3 ,-1? * ]' * ^' N B
|
3 ,-1? * ]' * ^' N B
|
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|
3 ,-1? + ]' + ^' N B
|
3 ,-1? + ]' + ^' N B
|
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|
3 ,-1? Q+ ]' ^+ ^' N B
|
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|
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3 ,-1? + ]' + ^' N B
|
3 ,-1? + ]' + ^' N B
|
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|
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|
3 ,-1? + ]' + ^' N B
|
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|
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|
3 ,-1? ", ]' /, ^' N B
|
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|
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|
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|
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|
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|
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|
3 ,-1? 9- ]' F- ^' N B
|
3 ,-1? 9- ]' F- ^' N B
|
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|
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|
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|
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|
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|
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|
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|
3 ,-1? P. ]' \. ^' N B
|
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|
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|
3 ,-1? . ]' . ^' N B
|
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|
|
|
3 ,-1? . ]' . ^' N B
|
3 ,-1? . ]' . ^' N B
|
|
|
3 ,-1? / ]' -/ ^' N B
|
3 ,-1? / ]' -/ ^' N B
|
|
|
3 ,-1? f/ ]' s/ ^' N B
|
3 ,-1? f/ ]' s/ ^' N B
|
|
|
3 ,-1? / ]' / ^' N B
|
3 ,-1? / ]' / ^' N B
|
|
|
3 ,-1? / ]' / ^' N B
|
3 ,-1? / ]' / ^' N B
|
|
|
3 ,-1? 70 ]' D0 ^' N B
|
3 ,-1? 70 ]' D0 ^' N B
|
|
|
3 ,-1? }0 ]' 0 ^' N B
|
3 ,-1? }0 ]' 0 ^' N B
|
|
|
3 ,-1? 0 ]' 0 ^' N B
|
3 ,-1? 0 ]' 0 ^' N B
|
|
|
3 ,-1? 1 ]' 1 ^' N B
|
3 ,-1? 1 ]' 1 ^' N B
|
|
|
3 ,-1? N1 ]' Z1 ^' N B
|
3 ,-1? N1 ]' Z1 ^' N B
|
|
|
3 ,-1? 1 ]' 1 ^' N B
|
3 ,-1? 1 ]' 1 ^' N B
|
|
|
3 ,-1? 1 ]' 1 ^' N B
|
3 ,-1? 1 ]' 1 ^' N B
|
|
|
3 ,-1? 2 ]' +2 ^' N B
|
3 ,-1? 2 ]' +2 ^' N B
|
|
|
3 ,-1? d2 ]' q2 ^' N B
|
3 ,-1? d2 ]' q2 ^' N B
|
|
|
3 ,-1? 2 ]' 2 ^' N B
|
3 ,-1? 2 ]' 2 ^' N B
|
|
|
3 ,-1? 2 ]' 2 ^' N B
|
3 ,-1? 2 ]' 2 ^' N B
|
|
|
3 ,-1? 53 ]' B3 ^' N B
|
3 ,-1? 53 ]' B3 ^' N B
|
|
|
3 ,-1? {3 ]' 3 ^' N B
|
3 ,-1? {3 ]' 3 ^' N B
|
|
|
3 ,-1? 3 ]' 3 ^' N B
|
3 ,-1? 3 ]' 3 ^' N B
|
|
|
3 ,-1? 4 ]' 4 ^' N B
|
3 ,-1? 4 ]' 4 ^' N B
|
|
|
3 ,-1? L4 ]' X4 ^' N B
|
3 ,-1? L4 ]' X4 ^' N B
|
|
|
3 ,-1? 4 ]' 4 ^' N B
|
3 ,-1? 4 ]' 4 ^' N B
|
|
|
3 ,-1? 4 ]' 4 ^' N B
|
3 ,-1? 4 ]' 4 ^' N B
|
|
|
3 ,-1? 5 ]' )5 ^' N B
|
3 ,-1? 5 ]' )5 ^' N B
|
|
|
3 ,-1? b5 ]' o5 ^' N B
|
3 ,-1? b5 ]' o5 ^' N B
|
|
|
3 ,-1? 5 ]' 5 ^' N B
|
3 ,-1? 5 ]' 5 ^' N B
|
|
|
3 ,-1? 5 ]' 5 ^' N B
|
3 ,-1? 5 ]' 5 ^' N B
|
|
|
3 ,-1? 36 ]' @6 ^' N B
|
3 ,-1? 36 ]' @6 ^' N B
|
|
|
3 ,-1? y6 ]' 6 ^' N B
|
3 ,-1? y6 ]' 6 ^' N B
|
|
|
3 ,-1? 6 ]' 6 ^' N B
|
3 ,-1? 6 ]' 6 ^' N B
|
|
|
3 ,-1? 7 ]' 7 ^' N B
|
3 ,-1? 7 ]' 7 ^' N B
|
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|
3 ,-1? J7 ]' W7 ^' N B
|
3 ,-1? J7 ]' W7 ^' N B
|
|
|
3 ,-1? 7 ]' 7 ^' N B
|
3 ,-1? 7 ]' 7 ^' N B
|
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|
3 ,-1? 7 ]' 7 ^' N B
|
3 ,-1? 7 ]' 7 ^' N B
|
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|
3 ,-1? 7 '' 7 4' N B
|
3 ,-1? 7 '' 7 4' N B
|
|
|
3 ,-1? 7 & 7 & N B
|
3 ,-1? 7 & 7 & N B
|
|
|
3 ,-1? 7 & 7 & N B
|
3 ,-1? 7 & 7 & N B
|
|
|
3 ,-1? 7 V& 7 b& N B
|
3 ,-1? 7 V& 7 b& N B
|
|
|
3 ,-1? 7 & 7 & N B
|
3 ,-1? 7 & 7 & N B
|
|
|
3 ,-1? 7 % 7 % N B
|
3 ,-1? 7 % 7 % N B
|
|
|
3 ,-1? 7 % 7 % N B
|
3 ,-1? 7 % 7 % N B
|
|
|
3 ,-1? 7 ?% 7 K% N B
|
3 ,-1? 7 ?% 7 K% N B
|
|
|
3 ,-1? 7 $ 7 % N B
|
3 ,-1? 7 $ 7 % N B
|
|
|
3 ,-1? 7 $ 7 $ N B
|
3 ,-1? 7 $ 7 $ N B
|
|
|
3 ,-1? 7 n$ 7 z$ N B
|
3 ,-1? 7 n$ 7 z$ N B
|
|
|
3 ,-1? 7 ($ 7 4$ N B
|
3 ,-1? 7 ($ 7 4$ N B
|
|
|
3 ,-1? 7 # 7 # N B
|
3 ,-1? 7 # 7 # N B
|
|
|
3 ,-1? 7 # 7 # N B
|
3 ,-1? 7 # 7 # N B
|
|
|
3 ,-1? 7 W# 7 c# N B
|
3 ,-1? 7 W# 7 c# N B
|
|
|
3 ,-1? 7 # 7 # N B
|
3 ,-1? 7 # 7 # N B
|
|
|
3 ,-1? 7 " 7 " N B
|
3 ,-1? 7 " 7 " N B
|
|
|
3 ,-1? 7 " 7 " N B
|
3 ,-1? 7 " 7 " N B
|
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|
3 ,-1? 7 @" 7 L" N B
|
3 ,-1? 7 @" 7 L" N B
|
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|
3 ,-1? 7 ! 7 " N B
|
3 ,-1? 7 ! 7 " N B
|
|
|
3 ,-1? 7 ! 7 ! N B
|
3 ,-1? 7 ! 7 ! N B
|
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|
3 ,-1? 7 n! 7 {! N B
|
3 ,-1? 7 n! 7 {! N B
|
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|
3 ,-1? 7 )! 7 5! N B
|
3 ,-1? 7 )! 7 5! N B
|
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|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
3 ,-1? 7 W 7 d N B
|
3 ,-1? 7 W 7 d N B
|
|
|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
|
|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
|
|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
3 ,-1? 7 @ 7 M N B
|
3 ,-1? 7 @ 7 M N B
|
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|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
|
|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
3 ,-1? 7 o 7 | N B
|
3 ,-1? 7 o 7 | N B
|
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|
3 ,-1? 7 ) 7 6 N B
|
3 ,-1? 7 ) 7 6 N B
|
|
|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
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|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
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|
3 ,-1? 7 7 N B
|
3 ,-1? 7 7 N B
|
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|
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|
3 ,-1? P7 ]7 N B
|
3 ,-1? P7 ]7 N B
|
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|
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|
3 ,-1? 7 7 N B
|
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|
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|
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|
3 ,-1? 6 6 N B
|
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|
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|
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|
3 ,-1? 6 6 N B
|
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|
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|
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|
3 ,-1? :6 F6 N B
|
3 ,-1? :6 F6 N B
|
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|
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|
3 ,-1? 5 6 N B
|
3 ,-1? 5 6 N B
|
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|
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|
3 ,-1? 5 5 N B
|
3 ,-1? 5 5 N B
|
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|
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|
3 ,-1? i5 u5 N B
|
3 ,-1? i5 u5 N B
|
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|
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|
3 ,-1? #5 05 N B
|
3 ,-1? #5 05 N B
|
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|
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|
3 ,-1? 4 4 N B
|
3 ,-1? 4 4 N B
|
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|
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|
3 ,-1? 4 4 N B
|
3 ,-1? 4 4 N B
|
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|
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|
3 ,-1? R4 _4 N B
|
3 ,-1? R4 _4 N B
|
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|
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|
3 ,-1? 4 4 N B
|
3 ,-1? 4 4 N B
|
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|
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|
3 ,-1? 3 3 N B
|
3 ,-1? 3 3 N B
|
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|
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|
3 ,-1? 3 3 N B
|
3 ,-1? 3 3 N B
|
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|
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|
3 ,-1? <3 H3 N B
|
3 ,-1? <3 H3 N B
|
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|
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|
3 ,-1? 2 3 N B
|
3 ,-1? 2 3 N B
|
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|
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|
3 ,-1? 2 2 N B
|
3 ,-1? 2 2 N B
|
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|
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|
3 ,-1? k2 w2 N B
|
3 ,-1? k2 w2 N B
|
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|
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|
3 ,-1? %2 22 N B
|
3 ,-1? %2 22 N B
|
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|
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|
3 ,-1? 1 1 N B
|
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|
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|
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|
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|
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|
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3 ,-1? T1 a1 N B
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
3 ,-1? l/ y/ N B
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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3 ,-1? - - N B
|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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|
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WISHBONE SLAVE UNIT
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; < E K N R } ~ Đ ʐ ͐ ϐ 7 8 A G J N { | ۑ ܑ . n o " # 4 @ A D H I z { O ? E L R ^ _ b e p ԝ ՝ / 0 A d e j k Š Ǡ ͠ ՠ ܠ ݠ @ A S Y ` l m t x E F H ` n o p ۣ ܣ ! $ ' 2 w x Ѥ Ҥ N O R S G I K M O P T V X Z ^ _ § ԧ ڧ } ~ ƨ Ǩ ɨ ߨ & ? U V
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) * 1 2 9 < = A J K P Q Ʈ ̮ Ӯ ߮ K L
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̲ Ͳ - . ? P Q T X Y ~ Ƕ , - ظ v w 8 l m s ! " $ & s t < = @ B O P S U J K M O % & ( * B C p 0 K L ^ d p q x [ \ ? @ B K L N < s t v w ; < ? @ I V W \ ]
N T [ a m n q t 6 7 8 I k l q r = > P V [ g h o s | } A B D H Q R Y Z u v y z - . 1 2 & ( * , . / 3 5 7 9 = > O P U Y 0 > ? m s z m n q r
- . @ F K W X [ { E F K O H I ~ f g B C F G $ % + 0 < = E Y K L Q U o p % Z ` g m y z } s t : B
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̲ Ͳ - . ? P Q T X Y ~ Ƕ , - ظ v w 8 l m s ! " $ & s t < = @ B O P S U J K M O % & ( * B C p 0 K L ^ d p q x [ \ ? @ B K L N < s t v w ; < ? @ I V W \ ]
N T [ a m n q t 6 7 8 I k l q r = > P V [ g h o s | } A B D H Q R Y Z u v y z - . 1 2 & ( * , . / 3 5 7 9 = > O P U Y 0 > ? m s z m n q r
- . @ F K W X [ { E F K O H I ~ f g B C F G $ % + 0 < = E Y K L Q U o p % Z ` g m y z } s t : B
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( ( ( ( ( ( ( ) ) ) ) * 4* 5* <* E* F* * * * * * * * * =+ >+ P+ V+ [+ g+ h+ p+ t+ + + + + q, r, z, , - - - - - - - . W. X. Z. ^. p. q. s. x. . . . / / / / / / / / / / / / 0 F0 G0 0 0 1 1 1 1 1 1 1 1 1 1 1 :2 ;2 2 2 2 2 3
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3 3 3 3 3 #3 .3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 f6 g6 h6 z6 6 6 6 6 6 6 k7 /8 08 28 R8 9 9 9 9 : : : ; ; ; ; ; q< < < < < n= o= > b? ? ? ? ? ? ? ? @
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3 3 3 3 3 #3 .3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 6 f6 g6 h6 z6 6 6 6 6 6 6 k7 /8 08 28 R8 9 9 9 9 : : : ; ; ; ; ; q< < < < < n= o= > b? ? ? ? ? ? ? ? @
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@ @ @ ~@ @ @ @ @ @ A A A A RB SB XB YB C C C C GC IC KC MC OC QC RC VC _C hC qC yC }C ~C C C C C C C D D
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D D E !F "F $F =F $G %G 'G ;G H H !H 8H H H H H H I I J [K K K K M O [P uQ @S oS pS yS S wT T T T T T T T T T T T T T U U U U U U U U )V *V +V 0V 6V @V LV MV TV VV ZV yV zV V V V V V V V W vW wW }W W W W W W W W FX GX MX OX QX X X TY UY VY [Y aY kY wY xY ~Y Y Y Y Y Y Y Y Y Y 3Z 4Z 5Z :Z @Z JZ VZ WZ \Z ^Z `Z Z Z Z Z Z Z Z U[ V[ W[ \[ b[ l[ x[ y[ }[ [ [ [ [ [ [ [ !\ "\ \ \ \ \ \ ] ] ] ] ] ] I] J] ] ] ] ] ] ] ] ] ] ] ] j^ k^ s^ u^ {^ _ _ _ _ _ _ _ ` ` ` }a ~a a a a a a a a a a a a a a a a a a a a a a a a 0b b b b b b b b b b b
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D D E !F "F $F =F $G %G 'G ;G H H !H 8H H H H H H I I J [K K K K M O [P uQ @S oS pS yS S wT T T T T T T T T T T T T T U U U U U U U U )V *V +V 0V 6V @V LV MV TV VV ZV yV zV V V V V V V V W vW wW }W W W W W W W W FX GX MX OX QX X X TY UY VY [Y aY kY wY xY ~Y Y Y Y Y Y Y Y Y Y 3Z 4Z 5Z :Z @Z JZ VZ WZ \Z ^Z `Z Z Z Z Z Z Z Z U[ V[ W[ \[ b[ l[ x[ y[ }[ [ [ [ [ [ [ [ !\ "\ \ \ \ \ \ ] ] ] ] ] ] I] J] ] ] ] ] ] ] ] ] ] ] ] j^ k^ s^ u^ {^ _ _ _ _ _ _ _ ` ` ` }a ~a a a a a a a a a a a a a a a a a a a a a a a a 0b b b b b b b b b b b
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c c c c c =c >c Dc Fc Hc c c c c c c c c c c "d #d )d +d -d {d |d e e e e &e 0e m ?m @m Bm n n n n n n q q r r r r v v kw w y y y _z `z bz { { j k m a b d 3 Ӌ \ O ۗ ܗ 2 ݘ ޘ C ! # Ǟ Ȟ p q # $ 8 ά < = ? ư ǰ Ȱ ʰ [ \ ] _ - . / K ӳ " # % @ A C Y H I S u v ! 1 2 3 C D E V W X i j k Ƽ Ǽ ּ ؼ ٽ ڽ ۽ m n { | } ! . / 0 = > ? L M N 3 4 5 D E F X Y Z l m n / 0 1 8 9 O P Q a b p q r _ ` q r s I J [ \ ] r s S " 3 C P ] }
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c c c c c =c >c Dc Fc Hc c c c c c c c c c c "d #d )d +d -d {d |d e e e e &e 0e m ?m @m Bm n n n n n n q q r r r r v v kw w y y y _z `z bz { { j k m a b d 3 Ӌ \ O ۗ ܗ 2 ݘ ޘ C ! # Ǟ Ȟ p q # $ 8 ά < = ? ư ǰ Ȱ ʰ [ \ ] _ - . / K ӳ " # % @ A C Y H I S u v ! 1 2 3 C D E V W X i j k Ƽ Ǽ ּ ؼ ٽ ڽ ۽ m n { | } ! . / 0 = > ? L M N 3 4 5 D E F X Y Z l m n / 0 1 8 9 O P Q a b p q r _ ` q r s I J [ \ ] r s S " 3 C P ] }
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4 U h v ' I \ j q H d $ 5 Q n $ - ; T h ( ; R \ v + = W l z / L l w ! 1 N m { 8 N X w % / ; O a R b ' B L \ 5 N j ~ 2 S m % 2 > I c : [ v 0 = ] u ! " $ %
0 0 0 0 0 0 0 0 0 0 0 0 X 0 X 0 X 0 0 ^ 0 ^ 0 0 X 0 } 0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 0 0 0 X 0 } 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 !0 0 X 0 } 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . X 0 } 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H @ 0 H 0 0 0 ` 0 ` 0 ` 0 ` 0 7b 0 7b 0 7b 0 ` 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0
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4 U h v ' I \ j q H d $ 5 Q n $ - ; T h ( ; R \ v + = W l z / L l w ! 1 N m { 8 N X w % / ; O a R b ' B L \ 5 N j ~ 2 S m % 2 > I c : [ v 0 = ] u ! " $ %
0 0 0 0 0 0 0 0 0 0 0 0 X 0 X 0 X 0 0 ^ 0 ^ 0 0 X 0 } 0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 "0 0 "0 "0 "0 "0 0 0 0 X 0 } 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 !0 0 X 0 } 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . 0 . X 0 } 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H 0 H @ 0 H 0 0 0 ` 0 ` 0 ` 0 ` 0 7b 0 7b 0 7b 0 ` 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0 c 0
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|
_ T o c 1 5 6 1 5 4
_ R e f 5 1 4 0 0 7 8 1 2
_ T o c 5 1 4 6 2 8 3 8 1
_ T o c 5 3 0 1 9 8 0 6 2
_ H l t 5 3 6 8 2 0 3 7 6
|
_ T o c 1 5 6 1 5 4
_ R e f 5 1 4 0 0 7 8 1 2
_ T o c 5 1 4 6 2 8 3 8 1
_ T o c 5 3 0 1 9 8 0 6 2
_ H l t 5 3 6 8 2 0 3 7 6
|
_ T o c 1 5 6 1 5 5
_ T o c 5 1 4 6 2 8 3 3 4 C o n f i g u r a t i o n S p a c e
_ R e f 5 3 6 8 2 0 4 0 4
_ R e f 5 3 6 8 2 0 4 3 8
_ R e f 5 3 6 8 2 0 4 4 0
_ R e f 5 3 6 8 2 0 4 4 1
_ R e f 5 3 6 8 2 0 4 8 1
_ H l t 5 3 6 8 2 0 4 9 4
_ R e f 5 3 6 8 2 0 5 1 8
_ H l t 5 3 6 8 2 0 5 3 1
|
_ T o c 1 5 6 1 5 5
_ T o c 5 1 4 6 2 8 3 3 4 C o n f i g u r a t i o n S p a c e
_ R e f 5 3 6 8 2 0 4 0 4
_ R e f 5 3 6 8 2 0 4 3 8
_ R e f 5 3 6 8 2 0 4 4 0
_ R e f 5 3 6 8 2 0 4 4 1
_ R e f 5 3 6 8 2 0 4 8 1
_ H l t 5 3 6 8 2 0 4 9 4
_ R e f 5 3 6 8 2 0 5 1 8
_ H l t 5 3 6 8 2 0 5 3 1
|
_ T o c 1 5 6 1 5 6
_ R e f 5 1 4 0 4 8 4 6 4
_ T o c 5 1 4 6 2 8 3 8 2
_ T o c 5 3 0 1 9 8 0 6 3
_ T o c 5 1 4 6 2 8 3 3 5
_ R e f 5 2 8 2 2 3 7 5 0
_ R e f 5 2 8 2 2 4 0 9 1
_ R e f 5 2 8 2 2 4 1 6 3 _ H l t 5 9 0 2 9
|
_ T o c 1 5 6 1 5 6
_ R e f 5 1 4 0 4 8 4 6 4
_ T o c 5 1 4 6 2 8 3 8 2
_ T o c 5 3 0 1 9 8 0 6 3
_ T o c 5 1 4 6 2 8 3 3 5
_ R e f 5 2 8 2 2 3 7 5 0
_ R e f 5 2 8 2 2 4 0 9 1
_ R e f 5 2 8 2 2 4 1 6 3 _ H l t 5 9 0 2 9
|
_ T o c 1 5 6 1 5 7
_ T o c 5 1 4 6 2 8 3 8 3
_ T o c 5 3 0 1 9 8 0 6 4
_ T o c 5 1 4 6 2 8 3 3 6
|
_ T o c 1 5 6 1 5 7
_ T o c 5 1 4 6 2 8 3 8 3
_ T o c 5 3 0 1 9 8 0 6 4
_ T o c 5 1 4 6 2 8 3 3 6
|
_ T o c 1 5 6 1 5 8
_ T o c 5 1 4 6 2 8 3 8 4
_ T o c 5 3 0 1 9 8 0 6 5
_ T o c 5 1 4 6 2 8 3 3 7 C o n f i g u r a t i o n C y c l e s
|
_ T o c 1 5 6 1 5 8
_ T o c 5 1 4 6 2 8 3 8 4
_ T o c 5 3 0 1 9 8 0 6 5
_ T o c 5 1 4 6 2 8 3 3 7 C o n f i g u r a t i o n C y c l e s
|
_ T o c 1 5 6 1 5 9
_ T o c 5 1 4 6 2 8 3 3 8
|
_ T o c 1 5 6 1 5 9
_ T o c 5 1 4 6 2 8 3 3 8
|
_ T o c 1 5 6 1 6 0 F i e l d V a l u e s
_ T o c 5 1 4 6 2 8 4 2 6
_ T o c 5 3 0 1 9 8 0 0 2
_ T o c 5 1 4 6 2 8 3 3 9
|
_ T o c 1 5 6 1 6 0 F i e l d V a l u e s
_ T o c 5 1 4 6 2 8 4 2 6
_ T o c 5 3 0 1 9 8 0 0 2
_ T o c 5 1 4 6 2 8 3 3 9
|
_ T o c 1 5 6 1 6 1
_ T o c 5 1 3 8 8 8 0 2 6
_ T o c 5 1 4 6 2 8 3 4 0 S l a v e U n i t W i s h b o n e O p e r a t i o n
|
_ T o c 1 5 6 1 6 1
_ T o c 5 1 3 8 8 8 0 2 6
_ T o c 5 1 4 6 2 8 3 4 0 S l a v e U n i t W i s h b o n e O p e r a t i o n
|
_ T o c 1 5 6 1 6 2
_ T o c 5 1 3 8 8 8 0 2 7
_ T o c 5 1 4 6 2 8 3 4 1
|
_ T o c 1 5 6 1 6 2
_ T o c 5 1 3 8 8 8 0 2 7
_ T o c 5 1 4 6 2 8 3 4 1
|
_ T o c 1 5 6 1 6 3
_ T o c 5 1 3 8 8 8 0 5 9
_ T o c 5 1 4 6 2 8 3 8 5
_ T o c 5 3 0 1 9 8 0 6 6
_ T o c 5 1 3 8 8 8 0 2 8
_ T o c 5 1 4 6 2 8 3 4 2
|
_ T o c 1 5 6 1 6 3
_ T o c 5 1 3 8 8 8 0 5 9
_ T o c 5 1 4 6 2 8 3 8 5
_ T o c 5 3 0 1 9 8 0 6 6
_ T o c 5 1 3 8 8 8 0 2 8
_ T o c 5 1 4 6 2 8 3 4 2
|
_ T o c 1 5 6 1 6 4
_ T o c 5 1 3 8 8 8 1 2 3
_ T o c 5 1 4 6 2 8 4 8 0
_ T o c 5 3 0 1 9 8 0 6 7
_ T o c 5 1 3 8 8 8 1 2 4
_ T o c 5 1 4 6 2 8 4 8 1
_ T o c 5 3 0 1 9 8 0 6 8
_ R e f 5 1 3 9 5 5 1 8 0
_ T o c 5 1 4 6 2 8 3 4 3
_ R e f 5 2 7 7 5 8 3 6 4 W r i t e C y c l e s T o P C I
|
_ T o c 1 5 6 1 6 4
_ T o c 5 1 3 8 8 8 1 2 3
_ T o c 5 1 4 6 2 8 4 8 0
_ T o c 5 3 0 1 9 8 0 6 7
_ T o c 5 1 3 8 8 8 1 2 4
_ T o c 5 1 4 6 2 8 4 8 1
_ T o c 5 3 0 1 9 8 0 6 8
_ R e f 5 1 3 9 5 5 1 8 0
_ T o c 5 1 4 6 2 8 3 4 3
_ R e f 5 2 7 7 5 8 3 6 4 W r i t e C y c l e s T o P C I
|
_ T o c 1 5 6 1 6 5
_ T o c 5 1 4 6 2 8 4 2 7
_ T o c 5 3 0 1 9 8 0 0 3 E r r o r R e p o r t i n g W I S H B O N E
_ R e f 5 1 4 5 2 9 8 0 1
_ T o c 5 1 4 6 2 8 3 4 4
_ R e f 5 2 7 7 5 8 3 8 4 R e a d C y c l e s T o P C I
|
_ T o c 1 5 6 1 6 5
_ T o c 5 1 4 6 2 8 4 2 7
_ T o c 5 3 0 1 9 8 0 0 3 E r r o r R e p o r t i n g W I S H B O N E
_ R e f 5 1 4 5 2 9 8 0 1
_ T o c 5 1 4 6 2 8 3 4 4
_ R e f 5 2 7 7 5 8 3 8 4 R e a d C y c l e s T o P C I
|
_ T o c 1 5 6 1 6 6
_ T o c 5 1 4 6 2 8 4 2 8
_ T o c 5 3 0 1 9 8 0 0 4 _ R e f 7 1 3 2 5
_ T o c 5 1 4 6 2 8 3 4 5 T a r g e t U n i t P C I 2
|
_ T o c 1 5 6 1 6 6
_ T o c 5 1 4 6 2 8 4 2 8
_ T o c 5 3 0 1 9 8 0 0 4 _ R e f 7 1 3 2 5
_ T o c 5 1 4 6 2 8 3 4 5 T a r g e t U n i t P C I 2
|
_ T o c 1 5 6 1 6 7
_ T o c 5 1 4 6 2 8 3 4 6
|
_ T o c 1 5 6 1 6 7
_ T o c 5 1 4 6 2 8 3 4 6
|
_ T o c 1 5 6 1 6 8
_ T o c 5 1 4 6 2 8 3 8 6
_ T o c 5 3 0 1 9 8 0 6 9
_ T o c 5 1 4 6 2 8 3 4 7
_ R e f 5 2 8 2 2 4 0 2 4
_ R e f 5 2 8 2 2 4 1 0 5
_ R e f 5 2 8 2 2 4 1 7 6
|
_ T o c 1 5 6 1 6 8
_ T o c 5 1 4 6 2 8 3 8 6
_ T o c 5 3 0 1 9 8 0 6 9
_ T o c 5 1 4 6 2 8 3 4 7
_ R e f 5 2 8 2 2 4 0 2 4
_ R e f 5 2 8 2 2 4 1 0 5
_ R e f 5 2 8 2 2 4 1 7 6
|
_ T o c 1 5 6 1 6 9
_ T o c 5 1 4 6 2 8 4 8 2
_ T o c 5 3 0 1 9 8 0 7 0
_ T o c 5 1 4 6 2 8 4 8 3
_ T o c 5 3 0 1 9 8 0 7 1
_ R e f 5 1 4 5 3 9 8 2 2
_ R e f 5 1 4 5 5 0 0 1 8
_ R e f 5 1 4 5 6 5 5 5 0
_ T o c 5 1 4 6 2 8 3 4 8
_ R e f 5 2 7 7 5 8 5 1 5 W r i t e C y c l e s T o W I S H B O N E
|
_ T o c 1 5 6 1 6 9
_ T o c 5 1 4 6 2 8 4 8 2
_ T o c 5 3 0 1 9 8 0 7 0
_ T o c 5 1 4 6 2 8 4 8 3
_ T o c 5 3 0 1 9 8 0 7 1
_ R e f 5 1 4 5 3 9 8 2 2
_ R e f 5 1 4 5 5 0 0 1 8
_ R e f 5 1 4 5 6 5 5 5 0
_ T o c 5 1 4 6 2 8 3 4 8
_ R e f 5 2 7 7 5 8 5 1 5 W r i t e C y c l e s T o W I S H B O N E
|
_ T o c 1 5 6 1 7 0
_ R e f 5 1 4 5 5 0 0 7 7
_ T o c 5 1 4 6 2 8 4 2 9
_ T o c 5 3 0 1 9 8 0 0 5
_ R e f 5 1 4 4 7 3 5 6 6
_ T o c 5 1 4 6 2 8 4 3 0
_ T o c 5 3 0 1 9 8 0 0 6 E r r o r R e p o r t i n g P C I
_ R e f 5 1 4 5 6 5 5 5 4
_ T o c 5 1 4 6 2 8 3 4 9
_ R e f 5 2 7 7 5 8 5 3 0 R e a d C y c l e s T o W I S H B O N E
|
_ T o c 1 5 6 1 7 0
_ R e f 5 1 4 5 5 0 0 7 7
_ T o c 5 1 4 6 2 8 4 2 9
_ T o c 5 3 0 1 9 8 0 0 5
_ R e f 5 1 4 4 7 3 5 6 6
_ T o c 5 1 4 6 2 8 4 3 0
_ T o c 5 3 0 1 9 8 0 0 6 E r r o r R e p o r t i n g P C I
_ R e f 5 1 4 5 6 5 5 5 4
_ T o c 5 1 4 6 2 8 3 4 9
_ R e f 5 2 7 7 5 8 5 3 0 R e a d C y c l e s T o W I S H B O N E
|
_ T o c 1 5 6 1 7 1
_ T o c 5 1 4 6 2 8 4 3 1
_ T o c 5 3 0 1 9 8 0 0 7 _ R e f 6 8 6 9 7
_ T o c 5 1 4 6 2 8 3 5 0 T r a n s a c t i o n O r d e r i n g
|
_ T o c 1 5 6 1 7 1
_ T o c 5 1 4 6 2 8 4 3 1
_ T o c 5 3 0 1 9 8 0 0 7 _ R e f 6 8 6 9 7
_ T o c 5 1 4 6 2 8 3 5 0 T r a n s a c t i o n O r d e r i n g
|
_ T o c 1 5 6 1 7 2
_ T o c 5 1 4 6 2 8 3 5 1 P a r i t y
|
_ T o c 1 5 6 1 7 2
_ T o c 5 1 4 6 2 8 3 5 1 P a r i t y
|
_ T o c 1 5 6 1 7 3
_ T o c 5 1 4 6 2 8 3 5 2
|
_ T o c 1 5 6 1 7 3
_ T o c 5 1 4 6 2 8 3 5 2
|
I n t e r r u p t s
|
I n t e r r u p t s
|
_ T o c 1 5 6 1 7 4
|
_ T o c 1 5 6 1 7 4
|
_ T o c 1 5 6 1 7 5
_ T o c 5 1 3 5 3 2 4 9 9
_ R e f 5 2 8 2 2 3 1 2 8
_ R e f 5 2 8 2 2 3 7 8 3
|
_ T o c 1 5 6 1 7 5
_ T o c 5 1 3 5 3 2 4 9 9
_ R e f 5 2 8 2 2 3 1 2 8
_ R e f 5 2 8 2 2 3 7 8 3
|
_ T o c 1 5 6 1 7 6
L i s t R e g i s t e r s
_ T o c 5 1 3 5 3 2 5 0 0
_ T o c 5 3 0 1 9 8 0 0 8
_ T o c 5 1 4 6 2 8 3 5 5 R e g i s t e r s W I S H B O N E
|
_ T o c 1 5 6 1 7 6
L i s t R e g i s t e r s
_ T o c 5 1 3 5 3 2 5 0 0
_ T o c 5 3 0 1 9 8 0 0 8
_ T o c 5 1 4 6 2 8 3 5 5 R e g i s t e r s W I S H B O N E
|
_ T o c 1 5 6 1 7 7
_ T o c 5 1 4 6 2 8 4 3 2
_ T o c 5 3 0 1 9 8 0 0 9
_ T o c 5 1 4 6 2 8 3 8 7
_ T o c 5 3 0 1 9 8 0 7 2
_ T o c 5 1 4 6 2 8 4 3 3
_ T o c 5 3 0 1 9 8 0 1 0
_ T o c 5 1 4 6 2 8 3 8 8
_ T o c 5 3 0 1 9 8 0 7 3
_ T o c 5 1 4 6 2 8 4 3 4
_ T o c 5 3 0 1 9 8 0 1 1
_ T o c 5 1 4 6 2 8 4 3 5
_ T o c 5 3 0 1 9 8 0 1 2
_ T o c 5 1 4 6 2 8 3 8 9
_ T o c 5 3 0 1 9 8 0 7 4
_ T o c 5 1 4 6 2 8 4 3 6
_ T o c 5 3 0 1 9 8 0 1 3
_ T o c 5 1 4 6 2 8 4 3 7
_ T o c 5 3 0 1 9 8 0 1 4
_ T o c 5 1 4 6 2 8 3 9 0
_ T o c 5 3 0 1 9 8 0 7 5
_ T o c 5 1 4 6 2 8 4 3 8
_ T o c 5 3 0 1 9 8 0 1 5
_ T o c 5 1 4 6 2 8 4 3 9
_ T o c 5 3 0 1 9 8 0 1 6
_ T o c 5 1 4 6 2 8 3 9 1
_ T o c 5 3 0 1 9 8 0 7 6
_ T o c 5 1 4 6 2 8 4 4 0
_ T o c 5 3 0 1 9 8 0 1 7
_ T o c 5 1 4 6 2 8 3 5 6 R e g i s t e r s P C I _ R e f 7 0 8 8 7
|
_ T o c 1 5 6 1 7 7
_ T o c 5 1 4 6 2 8 4 3 2
_ T o c 5 3 0 1 9 8 0 0 9
_ T o c 5 1 4 6 2 8 3 8 7
_ T o c 5 3 0 1 9 8 0 7 2
_ T o c 5 1 4 6 2 8 4 3 3
_ T o c 5 3 0 1 9 8 0 1 0
_ T o c 5 1 4 6 2 8 3 8 8
_ T o c 5 3 0 1 9 8 0 7 3
_ T o c 5 1 4 6 2 8 4 3 4
_ T o c 5 3 0 1 9 8 0 1 1
_ T o c 5 1 4 6 2 8 4 3 5
_ T o c 5 3 0 1 9 8 0 1 2
_ T o c 5 1 4 6 2 8 3 8 9
_ T o c 5 3 0 1 9 8 0 7 4
_ T o c 5 1 4 6 2 8 4 3 6
_ T o c 5 3 0 1 9 8 0 1 3
_ T o c 5 1 4 6 2 8 4 3 7
_ T o c 5 3 0 1 9 8 0 1 4
_ T o c 5 1 4 6 2 8 3 9 0
_ T o c 5 3 0 1 9 8 0 7 5
_ T o c 5 1 4 6 2 8 4 3 8
_ T o c 5 3 0 1 9 8 0 1 5
_ T o c 5 1 4 6 2 8 4 3 9
_ T o c 5 3 0 1 9 8 0 1 6
_ T o c 5 1 4 6 2 8 3 9 1
_ T o c 5 3 0 1 9 8 0 7 6
_ T o c 5 1 4 6 2 8 4 4 0
_ T o c 5 3 0 1 9 8 0 1 7
_ T o c 5 1 4 6 2 8 3 5 6 R e g i s t e r s P C I _ R e f 7 0 8 8 7
|
_ T o c 1 5 6 1 7 8 C o n f i g u r a t i o n S p a c e H e a d e r
_ R e f 5 1 4 5 5 1 5 7 0
_ T o c 5 1 4 6 2 8 3 9 2
_ T o c 5 3 0 1 9 8 0 7 7 ! C o n f i g u r a t i o n S p a c e H e a d e r R e g i s t e r s
_ T o c 5 1 4 6 2 8 4 4 1
_ T o c 5 3 0 1 9 8 0 1 8
_ T o c 5 1 4 6 2 8 4 4 2
_ T o c 5 3 0 1 9 8 0 1 9
_ T o c 5 1 4 6 2 8 4 4 3
_ T o c 5 3 0 1 9 8 0 2 0
_ T o c 5 1 4 6 2 8 4 4 4
_ T o c 5 3 0 1 9 8 0 2 1
_ T o c 5 1 4 6 2 8 4 4 5
_ R e f 5 2 7 9 7 6 3 1 3
_ T o c 5 3 0 1 9 8 0 2 2
_ T o c 5 1 4 6 2 8 3 9 3
_ R e f 5 2 7 9 7 6 3 3 0
_ R e f 5 2 7 9 7 6 3 4 8
_ T o c 5 3 0 1 9 8 0 7 8
_ T o c 5 1 4 6 2 8 4 4 6
_ R e f 5 2 7 9 7 5 4 7 1
_ R e f 5 2 7 9 7 5 5 6 2
_ T o c 5 3 0 1 9 8 0 2 3
_ T o c 5 1 4 6 2 8 3 9 4
_ T o c 5 3 0 1 9 8 0 7 9
_ T o c 5 1 4 6 2 8 4 4 7
_ T o c 5 3 0 1 9 8 0 2 4
_ T o c 5 1 4 6 2 8 4 4 8
_ R e f 5 2 7 9 7 5 5 0 3
_ T o c 5 3 0 1 9 8 0 2 5
_ T o c 5 1 4 6 2 8 3 9 5
_ T o c 5 3 0 1 9 8 0 8 0
_ T o c 5 1 4 6 2 8 4 4 9
_ T o c 5 3 0 1 9 8 0 2 6
_ T o c 5 1 4 6 2 8 4 5 0
_ R e f 5 2 7 9 7 5 5 1 3
_ T o c 5 3 0 1 9 8 0 2 7
_ T o c 5 1 4 6 2 8 3 9 6
_ T o c 5 3 0 1 9 8 0 8 1
_ T o c 5 1 4 6 2 8 4 5 1
_ T o c 5 3 0 1 9 8 0 2 8
_ T o c 5 1 4 6 2 8 4 5 2
_ R e f 5 2 7 9 7 5 5 1 8
_ T o c 5 3 0 1 9 8 0 2 9
_ T o c 5 1 4 6 2 8 3 9 7
_ T o c 5 3 0 1 9 8 0 8 2
_ T o c 5 1 4 6 2 8 4 5 3
_ T o c 5 3 0 1 9 8 0 3 0
_ T o c 5 1 4 6 2 8 3 5 7 R e g i s t e r s R e p o r t i n g
|
_ T o c 1 5 6 1 7 8 C o n f i g u r a t i o n S p a c e H e a d e r
_ R e f 5 1 4 5 5 1 5 7 0
_ T o c 5 1 4 6 2 8 3 9 2
_ T o c 5 3 0 1 9 8 0 7 7 ! C o n f i g u r a t i o n S p a c e H e a d e r R e g i s t e r s
_ T o c 5 1 4 6 2 8 4 4 1
_ T o c 5 3 0 1 9 8 0 1 8
_ T o c 5 1 4 6 2 8 4 4 2
_ T o c 5 3 0 1 9 8 0 1 9
_ T o c 5 1 4 6 2 8 4 4 3
_ T o c 5 3 0 1 9 8 0 2 0
_ T o c 5 1 4 6 2 8 4 4 4
_ T o c 5 3 0 1 9 8 0 2 1
_ T o c 5 1 4 6 2 8 4 4 5
_ R e f 5 2 7 9 7 6 3 1 3
_ T o c 5 3 0 1 9 8 0 2 2
_ T o c 5 1 4 6 2 8 3 9 3
_ R e f 5 2 7 9 7 6 3 3 0
_ R e f 5 2 7 9 7 6 3 4 8
_ T o c 5 3 0 1 9 8 0 7 8
_ T o c 5 1 4 6 2 8 4 4 6
_ R e f 5 2 7 9 7 5 4 7 1
_ R e f 5 2 7 9 7 5 5 6 2
_ T o c 5 3 0 1 9 8 0 2 3
_ T o c 5 1 4 6 2 8 3 9 4
_ T o c 5 3 0 1 9 8 0 7 9
_ T o c 5 1 4 6 2 8 4 4 7
_ T o c 5 3 0 1 9 8 0 2 4
_ T o c 5 1 4 6 2 8 4 4 8
_ R e f 5 2 7 9 7 5 5 0 3
_ T o c 5 3 0 1 9 8 0 2 5
_ T o c 5 1 4 6 2 8 3 9 5
_ T o c 5 3 0 1 9 8 0 8 0
_ T o c 5 1 4 6 2 8 4 4 9
_ T o c 5 3 0 1 9 8 0 2 6
_ T o c 5 1 4 6 2 8 4 5 0
_ R e f 5 2 7 9 7 5 5 1 3
_ T o c 5 3 0 1 9 8 0 2 7
_ T o c 5 1 4 6 2 8 3 9 6
_ T o c 5 3 0 1 9 8 0 8 1
_ T o c 5 1 4 6 2 8 4 5 1
_ T o c 5 3 0 1 9 8 0 2 8
_ T o c 5 1 4 6 2 8 4 5 2
_ R e f 5 2 7 9 7 5 5 1 8
_ T o c 5 3 0 1 9 8 0 2 9
_ T o c 5 1 4 6 2 8 3 9 7
_ T o c 5 3 0 1 9 8 0 8 2
_ T o c 5 1 4 6 2 8 4 5 3
_ T o c 5 3 0 1 9 8 0 3 0
_ T o c 5 1 4 6 2 8 3 5 7 R e g i s t e r s R e p o r t i n g
|
_ T o c 1 5 6 1 7 9 E r r o r R e p o r t i n g R e g i s t e r s W I S H B O N E
_ T o c 5 1 4 6 2 8 4 5 4
_ T o c 5 3 0 1 9 8 0 3 1
_ T o c 5 1 4 6 2 8 3 9 8
_ T o c 5 3 0 1 9 8 0 8 3
_ T o c 5 1 4 6 2 8 4 5 5
_ T o c 5 3 0 1 9 8 0 3 2
_ T o c 5 1 4 6 2 8 4 5 6
_ T o c 5 3 0 1 9 8 0 3 3
_ T o c 5 1 4 6 2 8 4 5 7
_ T o c 5 3 0 1 9 8 0 3 4 E r r o r R e p o r t i n g R e g i s t e r s P C I
_ T o c 5 1 4 6 2 8 4 5 8
_ T o c 5 3 0 1 9 8 0 3 5
_ T o c 5 1 4 6 2 8 3 9 9
_ T o c 5 3 0 1 9 8 0 8 4
_ T o c 5 1 4 6 2 8 4 5 9
_ T o c 5 3 0 1 9 8 0 3 6
_ T o c 5 1 4 6 2 8 4 6 0
_ T o c 5 3 0 1 9 8 0 3 7
_ T o c 5 1 4 6 2 8 4 6 1
_ T o c 5 3 0 1 9 8 0 3 8 C o n f i g u r a t i o n C y c l e s R e g i s t e r s
_ T o c 5 1 4 6 2 8 4 6 2
_ T o c 5 3 0 1 9 8 0 3 9
_ T o c 5 1 4 6 2 8 4 0 0
_ T o c 5 3 0 1 9 8 0 8 5
_ T o c 5 1 4 6 2 8 4 6 3
_ T o c 5 3 0 1 9 8 0 4 0
_ T o c 5 1 4 6 2 8 4 6 4
_ T o c 5 3 0 1 9 8 0 4 1
_ T o c 5 1 4 6 2 8 4 6 5
_ T o c 5 3 0 1 9 8 0 4 2
_ T o c 5 1 4 6 2 8 3 5 8
_ H l t 5 2 7 9 8 6 3 2 0 R e g i s t e r s I n t e r r u p t
|
_ T o c 1 5 6 1 7 9 E r r o r R e p o r t i n g R e g i s t e r s W I S H B O N E
_ T o c 5 1 4 6 2 8 4 5 4
_ T o c 5 3 0 1 9 8 0 3 1
_ T o c 5 1 4 6 2 8 3 9 8
_ T o c 5 3 0 1 9 8 0 8 3
_ T o c 5 1 4 6 2 8 4 5 5
_ T o c 5 3 0 1 9 8 0 3 2
_ T o c 5 1 4 6 2 8 4 5 6
_ T o c 5 3 0 1 9 8 0 3 3
_ T o c 5 1 4 6 2 8 4 5 7
_ T o c 5 3 0 1 9 8 0 3 4 E r r o r R e p o r t i n g R e g i s t e r s P C I
_ T o c 5 1 4 6 2 8 4 5 8
_ T o c 5 3 0 1 9 8 0 3 5
_ T o c 5 1 4 6 2 8 3 9 9
_ T o c 5 3 0 1 9 8 0 8 4
_ T o c 5 1 4 6 2 8 4 5 9
_ T o c 5 3 0 1 9 8 0 3 6
_ T o c 5 1 4 6 2 8 4 6 0
_ T o c 5 3 0 1 9 8 0 3 7
_ T o c 5 1 4 6 2 8 4 6 1
_ T o c 5 3 0 1 9 8 0 3 8 C o n f i g u r a t i o n C y c l e s R e g i s t e r s
_ T o c 5 1 4 6 2 8 4 6 2
_ T o c 5 3 0 1 9 8 0 3 9
_ T o c 5 1 4 6 2 8 4 0 0
_ T o c 5 3 0 1 9 8 0 8 5
_ T o c 5 1 4 6 2 8 4 6 3
_ T o c 5 3 0 1 9 8 0 4 0
_ T o c 5 1 4 6 2 8 4 6 4
_ T o c 5 3 0 1 9 8 0 4 1
_ T o c 5 1 4 6 2 8 4 6 5
_ T o c 5 3 0 1 9 8 0 4 2
_ T o c 5 1 4 6 2 8 3 5 8
_ H l t 5 2 7 9 8 6 3 2 0 R e g i s t e r s I n t e r r u p t
|
_ T o c 1 5 6 1 8 0
_ T o c 5 1 4 6 2 8 4 6 6
_ T o c 5 3 0 1 9 8 0 4 3
_ T o c 5 1 4 6 2 8 4 0 1
_ T o c 5 3 0 1 9 8 0 8 6
_ T o c 5 1 4 6 2 8 4 6 7
_ T o c 5 3 0 1 9 8 0 4 4
_ T o c 5 1 4 6 2 8 4 6 8
_ T o c 5 3 0 1 9 8 0 4 5
_ T o c 5 1 4 6 2 8 4 0 2
_ T o c 5 3 0 1 9 8 0 8 7
_ T o c 5 1 4 6 2 8 4 6 9
_ T o c 5 3 0 1 9 8 0 4 6
|
_ T o c 1 5 6 1 8 0
_ T o c 5 1 4 6 2 8 4 6 6
_ T o c 5 3 0 1 9 8 0 4 3
_ T o c 5 1 4 6 2 8 4 0 1
_ T o c 5 3 0 1 9 8 0 8 6
_ T o c 5 1 4 6 2 8 4 6 7
_ T o c 5 3 0 1 9 8 0 4 4
_ T o c 5 1 4 6 2 8 4 6 8
_ T o c 5 3 0 1 9 8 0 4 5
_ T o c 5 1 4 6 2 8 4 0 2
_ T o c 5 3 0 1 9 8 0 8 7
_ T o c 5 1 4 6 2 8 4 6 9
_ T o c 5 3 0 1 9 8 0 4 6
|
_ T o c 1 5 6 1 8 1
|
_ T o c 1 5 6 1 8 1
|
_ T o c 1 5 6 1 8 2
_ T o c 5 1 2 4 1 0 4 5 2
_ T o c 5 1 2 4 1 0 8 1 3
_ T o c 5 1 4 6 2 8 3 6 0
_ R e f 5 2 7 7 3 9 3 9 3
_ R e f 5 2 7 7 4 5 1 6 1 P i n s R e q u i r e d
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_ T o c 1 5 6 1 8 2
_ T o c 5 1 2 4 1 0 4 5 2
_ T o c 5 1 2 4 1 0 8 1 3
_ T o c 5 1 4 6 2 8 3 6 0
_ R e f 5 2 7 7 3 9 3 9 3
_ R e f 5 2 7 7 4 5 1 6 1 P i n s R e q u i r e d
|
_ T o c 1 5 6 1 8 3
_ T o c 5 1 4 6 2 8 3 6 1
|
_ T o c 1 5 6 1 8 3
_ T o c 5 1 4 6 2 8 3 6 1
|
_ T o c 1 5 6 1 8 4
_ T o c 5 1 3 5 3 2 4 9 7
_ T o c 5 1 4 6 2 8 4 7 0
_ T o c 5 3 0 1 9 8 0 4 7
_ T o c 5 1 4 6 2 8 4 7 1
_ T o c 5 3 0 1 9 8 0 4 8
_ T o c 5 1 4 6 2 8 4 7 2
_ T o c 5 3 0 1 9 8 0 4 9
_ T o c 5 1 4 6 2 8 4 7 3
_ T o c 5 3 0 1 9 8 0 5 0
_ T o c 5 1 4 6 2 8 4 7 4
_ T o c 5 3 0 1 9 8 0 5 1 P i n s O p t i o n a l
_ T o c 5 1 4 6 2 8 3 6 2
|
_ T o c 1 5 6 1 8 4
_ T o c 5 1 3 5 3 2 4 9 7
_ T o c 5 1 4 6 2 8 4 7 0
_ T o c 5 3 0 1 9 8 0 4 7
_ T o c 5 1 4 6 2 8 4 7 1
_ T o c 5 3 0 1 9 8 0 4 8
_ T o c 5 1 4 6 2 8 4 7 2
_ T o c 5 3 0 1 9 8 0 4 9
_ T o c 5 1 4 6 2 8 4 7 3
_ T o c 5 3 0 1 9 8 0 5 0
_ T o c 5 1 4 6 2 8 4 7 4
_ T o c 5 3 0 1 9 8 0 5 1 P i n s O p t i o n a l
_ T o c 5 1 4 6 2 8 3 6 2
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_ T o c 1 5 6 1 8 5
_ T o c 5 1 4 6 2 8 4 7 5
_ T o c 5 3 0 1 9 8 0 5 2
_ T o c 5 1 4 6 2 8 4 7 6
_ T o c 5 3 0 1 9 8 0 5 3
_ T o c 5 1 4 6 2 8 3 6 3
_ R e f 5 2 7 7 4 0 8 9 0
_ R e f 5 2 7 7 4 9 4 3 1
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_ T o c 1 5 6 1 8 5
_ T o c 5 1 4 6 2 8 4 7 5
_ T o c 5 3 0 1 9 8 0 5 2
_ T o c 5 1 4 6 2 8 4 7 6
_ T o c 5 3 0 1 9 8 0 5 3
_ T o c 5 1 4 6 2 8 3 6 3
_ R e f 5 2 7 7 4 0 8 9 0
_ R e f 5 2 7 7 4 9 4 3 1
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_ T o c 1 5 6 1 8 6
_ T o c 5 1 4 6 2 8 4 7 7
_ T o c 5 3 0 1 9 8 0 5 4
_ T o c 5 1 4 6 2 8 4 7 8
_ T o c 5 3 0 1 9 8 0 5 5
_ T o c 5 1 4 6 2 8 4 7 9
_ T o c 5 3 0 1 9 8 0 5 6
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_ T o c 1 5 6 1 8 6
_ T o c 5 1 4 6 2 8 4 7 7
_ T o c 5 3 0 1 9 8 0 5 4
_ T o c 5 1 4 6 2 8 4 7 8
_ T o c 5 3 0 1 9 8 0 5 5
_ T o c 5 1 4 6 2 8 4 7 9
_ T o c 5 3 0 1 9 8 0 5 6
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_ H l t 1 6 0 2 6 5
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_ H l t 1 6 0 2 6 5
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_ T o c 1 5 6 1 8 7
_ T o c 5 1 4 6 2 8 3 6 5 W a v e f o r m s W I S H B O N E
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_ T o c 1 5 6 1 8 7
_ T o c 5 1 4 6 2 8 3 6 5 W a v e f o r m s W I S H B O N E
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_ T o c 1 5 6 1 8 8
_ T o c 5 1 4 6 2 8 3 6 6 C o n f i g u r a t i o n C y c l e s W I S H B O N E
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_ T o c 1 5 6 1 8 8
_ T o c 5 1 4 6 2 8 3 6 6 C o n f i g u r a t i o n C y c l e s W I S H B O N E
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_ T o c 1 5 6 1 8 9
_ R e f 5 1 3 8 7 5 6 9 8
_ T o c 5 1 4 6 2 8 4 0 3
_ T o c 5 3 0 1 9 8 0 8 8
_ R e f 5 1 3 8 7 4 4 2 1
_ T o c 5 1 4 6 2 8 4 0 4
_ T o c 5 3 0 1 9 8 0 8 9
_ R e f 5 1 3 8 7 6 8 1 3
_ T o c 5 1 4 6 2 8 4 0 5
_ T o c 5 3 0 1 9 8 0 9 0
_ T o c 5 1 4 6 2 8 3 6 7
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_ T o c 1 5 6 1 8 9
_ R e f 5 1 3 8 7 5 6 9 8
_ T o c 5 1 4 6 2 8 4 0 3
_ T o c 5 3 0 1 9 8 0 8 8
_ R e f 5 1 3 8 7 4 4 2 1
_ T o c 5 1 4 6 2 8 4 0 4
_ T o c 5 3 0 1 9 8 0 8 9
_ R e f 5 1 3 8 7 6 8 1 3
_ T o c 5 1 4 6 2 8 4 0 5
_ T o c 5 3 0 1 9 8 0 9 0
_ T o c 5 1 4 6 2 8 3 6 7
|
_ T o c 1 5 6 1 9 0
_ R e f 5 1 3 8 7 8 5 4 1
_ T o c 5 1 4 6 2 8 4 0 6
_ T o c 5 3 0 1 9 8 0 9 1
_ T o c 5 1 4 6 2 8 3 6 8
|
_ T o c 1 5 6 1 9 0
_ R e f 5 1 3 8 7 8 5 4 1
_ T o c 5 1 4 6 2 8 4 0 6
_ T o c 5 3 0 1 9 8 0 9 1
_ T o c 5 1 4 6 2 8 3 6 8
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_ T o c 1 5 6 1 9 1
_ R e f 5 1 3 8 8 1 5 9 8
_ T o c 5 1 4 6 2 8 4 0 7
_ T o c 5 3 0 1 9 8 0 9 2
_ R e f 5 1 3 8 8 5 1 8 6
_ T o c 5 1 4 6 2 8 4 0 8
_ T o c 5 3 0 1 9 8 0 9 3
_ R e f 5 1 3 8 8 6 1 0 6
_ T o c 5 1 4 6 2 8 4 0 9
_ T o c 5 3 0 1 9 8 0 9 4 _ 1 0 5 2 2 0 6 0 7 4
_ R e f 5 1 3 8 8 7 0 6 7
_ T o c 5 1 4 6 2 8 4 1 0
_ T o c 5 3 0 1 9 8 0 9 5
_ T o c 5 1 4 6 2 8 3 6 9 T e r m i n a t i o n C y c l e s P C I
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_ T o c 1 5 6 1 9 1
_ R e f 5 1 3 8 8 1 5 9 8
_ T o c 5 1 4 6 2 8 4 0 7
_ T o c 5 3 0 1 9 8 0 9 2
_ R e f 5 1 3 8 8 5 1 8 6
_ T o c 5 1 4 6 2 8 4 0 8
_ T o c 5 3 0 1 9 8 0 9 3
_ R e f 5 1 3 8 8 6 1 0 6
_ T o c 5 1 4 6 2 8 4 0 9
_ T o c 5 3 0 1 9 8 0 9 4 _ 1 0 5 2 2 0 6 0 7 4
_ R e f 5 1 3 8 8 7 0 6 7
_ T o c 5 1 4 6 2 8 4 1 0
_ T o c 5 3 0 1 9 8 0 9 5
_ T o c 5 1 4 6 2 8 3 6 9 T e r m i n a t i o n C y c l e s P C I
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_ T o c 1 5 6 1 9 2
_ R e f 5 1 3 9 5 1 7 5 9
_ T o c 5 1 4 6 2 8 4 1 1
_ T o c 5 3 0 1 9 8 0 9 6
_ R e f 5 1 3 9 5 7 4 1 1
_ T o c 5 1 4 6 2 8 4 1 2
_ T o c 5 3 0 1 9 8 0 9 7 _ 1 0 5 2 2 0 6 3 0 7
_ T o c 5 1 4 6 2 8 4 1 3
_ T o c 5 3 0 1 9 8 0 9 8
_ T o c 5 1 4 6 2 8 4 1 4
_ T o c 5 3 0 1 9 8 0 9 9
_ T o c 5 1 4 6 2 8 4 1 5
_ T o c 5 3 0 1 9 8 1 0 0
_ T o c 5 1 4 6 2 8 4 1 6
_ T o c 5 3 0 1 9 8 1 0 1
_ T o c 5 1 4 6 2 8 3 7 0 W a v e f o r m s P C I
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_ T o c 1 5 6 1 9 2
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_ T o c 5 1 4 6 2 8 4 1 1
_ T o c 5 3 0 1 9 8 0 9 6
_ R e f 5 1 3 9 5 7 4 1 1
_ T o c 5 1 4 6 2 8 4 1 2
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_ T o c 5 3 0 1 9 8 0 9 8
_ T o c 5 1 4 6 2 8 4 1 4
_ T o c 5 3 0 1 9 8 0 9 9
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_ T o c 5 1 4 6 2 8 4 1 6
_ T o c 5 3 0 1 9 8 1 0 1
_ T o c 5 1 4 6 2 8 3 7 0 W a v e f o r m s P C I
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_ T o c 1 5 6 1 9 3
_ T o c 5 1 4 6 2 8 3 7 1 C o n f i g u r a t i o n C y c l e s P C I
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_ T o c 1 5 6 1 9 3
_ T o c 5 1 4 6 2 8 3 7 1 C o n f i g u r a t i o n C y c l e s P C I
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_ T o c 1 5 6 1 9 4
_ R e f 5 1 4 5 6 3 1 8 7
_ T o c 5 1 4 6 2 8 4 1 7
_ T o c 5 3 0 1 9 8 1 0 2
_ R e f 5 1 4 5 6 3 2 0 0
_ T o c 5 1 4 6 2 8 4 1 8
_ T o c 5 3 0 1 9 8 1 0 3
_ T o c 5 1 4 6 2 8 3 7 2
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_ T o c 1 5 6 1 9 4
_ R e f 5 1 4 5 6 3 1 8 7
_ T o c 5 1 4 6 2 8 4 1 7
_ T o c 5 3 0 1 9 8 1 0 2
_ R e f 5 1 4 5 6 3 2 0 0
_ T o c 5 1 4 6 2 8 4 1 8
_ T o c 5 3 0 1 9 8 1 0 3
_ T o c 5 1 4 6 2 8 3 7 2
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_ T o c 1 5 6 1 9 5
_ R e f 5 1 4 5 6 3 9 6 0
_ T o c 5 1 4 5 6 6 1 4 6
_ R e f 5 1 4 5 6 7 4 1 3
_ T o c 5 1 4 6 2 8 4 1 9
_ T o c 5 3 0 1 9 8 1 0 4
_ T o c 5 1 4 5 6 6 1 4 7
_ T o c 5 1 4 6 2 8 4 2 0
_ T o c 5 3 0 1 9 8 1 0 5
_ R e f 5 1 4 5 6 4 8 5 8
_ T o c 5 1 4 5 6 6 1 4 8
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_ T o c 5 1 4 6 2 8 4 2 1
_ T o c 5 3 0 1 9 8 1 0 6 _ 1 0 5 2 2 0 6 7 4 0
_ R e f 5 1 4 5 6 4 8 6 4
_ T o c 5 1 4 6 2 8 4 2 2
_ T o c 5 3 0 1 9 8 1 0 7
_ T o c 5 1 4 5 6 6 1 5 0
_ T o c 5 1 4 6 2 8 4 2 3
_ T o c 5 3 0 1 9 8 1 0 8
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_ R e f 5 1 4 5 6 3 9 6 0
_ T o c 5 1 4 5 6 6 1 4 6
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_ T o c 5 1 4 6 2 8 4 1 9
_ T o c 5 3 0 1 9 8 1 0 4
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_ R e f 5 1 4 5 6 4 8 5 8
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PL P^P`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`B* OJ QJ o( 0 ^`0o( - h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`OJ QJ o( h h^h`OJ QJ o( " ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ ` . h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^ ` o( T ^T`o( . p^ ` o( . . ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 8 8^8`CJ OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h h^h`OJ QJ o( h h h^h`CJ OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h h^h` . ^` . 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PL P^P`L . h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h` . h h^h`OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^`CJ OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^`OJ QJ o( h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h h^h`OJ QJ o( h h^h`OJ QJ o( h ^`OJ QJ o( h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^ ` o( T ^T`o( . p^ ` o( . . ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( h h^h` . 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L ^`L . ^` . ^` . PL P^P`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^ ` o( ` ^``o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( h h^h`B* CJ OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h h^h`B* OJ QJ o( h h^h`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h^ ` 56 CJ` OJ QJ o( A p p e n d i x 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( ^ ` . ^` . pL p^p`L . @ @ ^@ ` . ^` . L ^`L . ^` . ^` . PL P^P`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`B* OJ QJ o( 0 ^`0o( - h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`OJ QJ o( h h^h`OJ QJ o( " ^`OJ QJ o( o p p^p`OJ QJ o( @ @ ^@ `OJ QJ o( ^`OJ QJ o( o ^`OJ QJ o( ^`OJ QJ o( ^`OJ QJ o( o P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ ` . h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^ ` o( T ^T`o( . p^ ` o( . . ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( ^ ` o( h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 8 8^8`CJ OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h h^h`OJ QJ o( h h h^h`CJ OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h h^h` . ^` . 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L ^`L . h h^h`OJ QJ o( h ^h` OJ QJ o( h h^h`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`OJ QJ o( " h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`B* OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^ ` . h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h^ ` 56 CJ` OJ QJ o( I n d e x h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h h^h`B* OJ QJ o( h h^h` . ^ ` o( h ^h`o( . H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( h ^ ` . h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h h^h`B* OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . 8 h h^h`CJ OJ QJ o( 8 h h^h`OJ QJ o( o 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( h ^ ` . h ^` . h L ^`L . h | | ^| ` . h L L^L` . h L ^ `L . h ^` . h ^` . h L ^`L . h h^h`B* OJ QJ o( ^ ` o( ` ^``o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( @ @^@` o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h^ ` 56 CJ` OJ QJ o( h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h ^`OJ QJ o( h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h h^h`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( h ^`OJ QJ o( h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . h ^` . h ^` . h pL p^p`L . h @ @ ^@ ` . h ^` . h L ^`L . h ^` . h ^` . h PL P^P`L . ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h h^h`B* OJ QJ o( h h^h`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( o p p^p`CJ OJ QJ o( @ @ ^@ `CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( ^`CJ OJ QJ o( P P^P`CJ OJ QJ o( h h^h`B* OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( h ^`OJ QJ o( o h P P^P`OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 h h^h`CJ OJ QJ o( 8 8 8^8`OJ QJ o( 8 ^`OJ QJ o( 8 ^ `OJ QJ o( o 8 ^ `OJ QJ o( 8 x x^x`OJ QJ o( 8 H H^H`OJ QJ o( o 8 ^`OJ QJ o( ^ ` o( h ^h`o( . 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H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( H H ^H ` o( h^ ` 56 CJ` OJ QJ o( A p p e n d i x h h^h`OJ QJ o( " h ^`OJ QJ o( h ^`OJ QJ o( o h p p^p`OJ QJ o( h @ @ ^@ `OJ QJ o( h ^`OJ QJ o( o h ^`OJ QJ o( h ^`OJ QJ o( for Core's Specifications s jeanne e ean ean Specifications Template.dot Tadej ic 7 de Microsoft Word 9.0 l@ P}D#@ @ 3~@ o 6k c
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_ T o c 5 3 0 1 9 8 0 3 9 < _ T o c 5 3 0 1 9 8 0 3 8 < _ T o c 5 3 0 1 9 8 0 3 7 < _ T o c 5 3 0 1 9 8 0 3 6 < _ T o c 5 3 0 1 9 8 0 3 5 < _ T o c 5 3 0 1 9 8 0 3 4 < _ T o c 5 3 0 1 9 8 0 3 3 < } _ T o c 5 3 0 1 9 8 0 3 2 < w _ T o c 5 3 0 1 9 8 0 3 1 < q _ T o c 5 3 0 1 9 8 0 3 0 < k _ T o c 5 3 0 1 9 8 0 2 9 < e _ T o c 5 3 0 1 9 8 0 2 8 < _ _ T o c 5 3 0 1 9 8 0 2 7 < Y _ T o c 5 3 0 1 9 8 0 2 6 < S _ T o c 5 3 0 1 9 8 0 2 5 < M _ T o c 5 3 0 1 9 8 0 2 4 < G _ T o c 5 3 0 1 9 8 0 2 3 < A _ T o c 5 3 0 1 9 8 0 2 2 < ; _ T o c 5 3 0 1 9 8 0 2 1 < 5 _ T o c 5 3 0 1 9 8 0 2 0 < / _ T o c 5 3 0 1 9 8 0 1 9 < ) _ T o c 5 3 0 1 9 8 0 1 8 < # _ T o c 5 3 0 1 9 8 0 1 7 < _ T o c 5 3 0 1 9 8 0 1 6 < _ T o c 5 3 0 1 9 8 0 1 5 < _ T o c 5 3 0 1 9 8 0 1 4 < _ T o c 5 3 0 1 9 8 0 1 3 < _ T o c 5 3 0 1 9 8 0 1 2 < _ T o c 5 3 0 1 9 8 0 1 1 < _ T o c 5 3 0 1 9 8 0 1 0 < _ T o c 5 3 0 1 9 8 0 0 9 < _ T o c 5 3 0 1 9 8 0 0 8 < _ T o c 5 3 0 1 9 8 0 0 7 < _ T o c 5 3 0 1 9 8 0 0 6 < _ T o c 5 3 0 1 9 8 0 0 5 < _ T o c 5 3 0 1 9 8 0 0 4 < _ T o c 5 3 0 1 9 8 0 0 3 < _ T o c 5 3 0 1 9 8 0 0 2 < _ T o c 5 3 0 1 9 8 0 0 1 < _ T o c 5 3 0 1 9 8 0 0 0 5 _ T o c 5 3 0 1 9 7 9 9 9 5 _ T o c 5 3 0 1 9 7 9 9 8 5 _ T o c 5 3 0 1 9 7 9 9 7 5 _ T o c 5 3 0 1 9 7 9 9 6 5 _ T o c 5 3 0 1 9 7 9 9 5 5 _ T o c 5 3 0 1 9 7 9 9 4 5 _ T o c 5 3 0 1 9 7 9 9 3 5 _ T o c 5 3 0 1 9 7 9 9 2 5 _ T o c 5 3 0 1 9 7 9 9 1 5 ~ _ T o c 5 3 0 1 9 7 9 9 0 5 x _ T o c 5 3 0 1 9 7 9 8 9 5 r _ T ՜. +,D ՜. +,\ h p
Flextronics Semiconductor l 8 }
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Specifications Template Title G 8 @ _PID_HLINKS A G d = T _ T o c 5 3 0 1 9 8 1 1 0 = N _ T o c 5 3 0 1 9 8 1 0 9 = H _ T o c 5 3 0 1 9 8 1 0 8 = B _ T o c 5 3 0 1 9 8 1 0 7 = < _ T o c 5 3 0 1 9 8 1 0 6 = 6 _ T o c 5 3 0 1 9 8 1 0 5 = 0 _ T o c 5 3 0 1 9 8 1 0 4 = * _ T o c 5 3 0 1 9 8 1 0 3 = $ _ T o c 5 3 0 1 9 8 1 0 2 = _ T o c 5 3 0 1 9 8 1 0 1 = _ T o c 5 3 0 1 9 8 1 0 0 < _ T o c 5 3 0 1 9 8 0 9 9 < _ T o c 5 3 0 1 9 8 0 9 8 < _ T o c 5 3 0 1 9 8 0 9 7 < _ T o c 5 3 0 1 9 8 0 9 6 < _ T o c 5 3 0 1 9 8 0 9 5 < _ T o c 5 3 0 1 9 8 0 9 4 < _ T o c 5 3 0 1 9 8 0 9 3 < _ T o c 5 3 0 1 9 8 0 9 2 < _ T o c 5 3 0 1 9 8 0 9 1 < _ T o c 5 3 0 1 9 8 0 9 0 < _ T o c 5 3 0 1 9 8 0 8 9 < _ T o c 5 3 0 1 9 8 0 8 8 < _ T o c 5 3 0 1 9 8 0 8 7 < _ T o c 5 3 0 1 9 8 0 8 6 < _ T o c 5 3 0 1 9 8 0 8 5 < _ T o c 5 3 0 1 9 8 0 8 4 < _ T o c 5 3 0 1 9 8 0 8 3 < _ T o c 5 3 0 1 9 8 0 8 2 < _ T o c 5 3 0 1 9 8 0 8 1 < _ T o c 5 3 0 1 9 8 0 8 0 < _ T o c 5 3 0 1 9 8 0 7 9 < _ T o c 5 3 0 1 9 8 0 7 8 < _ T o c 5 3 0 1 9 8 0 7 7 < _ T o c 5 3 0 1 9 8 0 7 6 < _ T o c 5 3 0 1 9 8 0 7 5 < | _ T o c 5 3 0 1 9 8 0 7 4 < v _ T o c 5 3 0 1 9 8 0 7 3 < p _ T o c 5 3 0 1 9 8 0 7 2 < j _ T o c 5 3 0 1 9 8 0 7 1 < d _ T o c 5 3 0 1 9 8 0 7 0 < ^ _ T o c 5 3 0 1 9 8 0 6 9 < X _ T o c 5 3 0 1 9 8 0 6 8 < R _ T o c 5 3 0 1 9 8 0 6 7 < L _ T o c 5 3 0 1 9 8 0 6 6 < F _ T o c 5 3 0 1 9 8 0 6 5 < @ _ T o c 5 3 0 1 9 8 0 6 4 < : _ T o c 5 3 0 1 9 8 0 6 3 < 4 _ T o c 5 3 0 1 9 8 0 6 2 < . _ T o c 5 3 0 1 9 8 0 6 1 < ( _ T o c 5 3 0 1 9 8 0 6 0 < " _ T o c 5 3 0 1 9 8 0 5 9 < _ T o c 5 3 0 1 9 8 0 5 8 < _ T o c 5 3 0 1 9 8 0 5 7 <
_ T o c 5 3 0 1 9 8 0 5 6 < _ T o c 5 3 0 1 9 8 0 5 5 < _ T o c 5 3 0 1 9 8 0 5 4 < _ T o c 5 3 0 1 9 8 0 5 3 < _ T o c 5 3 0 1 9 8 0 5 2 < _ T o c 5 3 0 1 9 8 0 5 1 < _ T o c 5 3 0 1 9 8 0 5 0 < _ T o c 5 3 0 1 9 8 0 4 9 < _ T o c 5 3 0 1 9 8 0 4 8 < _ T o c 5 3 0 1 9 8 0 4 7 < _ T o c 5 3 0 1 9 8 0 4 6 < _ T o c 5 3 0 1 9 8 0 4 5 < _ T o c 5 3 0 1 9 8 0 4 4 < _ T o c 5 3 0 1 9 8 0 4 3 < _ T o c 5 3 0 1 9 8 0 4 2 < _ T o c 5 3 0 1 9 8 0 4 1 < _ T o c 5 3 0 1 9 8 0 4 0 < o c 5 3 0 1 9 7 9 8 8 5 l _ T o c 5 3 0 1 9 7 9 8 7 5 f _ T o c 5 3 0 1 9 7 9 8 6 5 ` _ T o c 5 3 0 1 9 7 9 8 5 5 Z _ T o c 5 3 0 1 9 7 9 8 4 5 T _ T o c 5 3 0 1 9 7 9 8 3 5 N _ T o c 5 3 0 1 9 7 9 8 2 5 H _ T o c 5 3 0 1 9 7 9 8 1 5 B _ T o c 5 3 0 1 9 7 9 8 0 5 < _ T o c 5 3 0 1 9 7 9 7 9 5 6 _ T o c 5 3 0 1 9 7 9 7 8 5 0 _ T o c 5 3 0 1 9 7 9 7 7 5 * _ T o c 5 3 0 1 9 7 9 7 6 5 $ _ T o c 5 3 0 1 9 7 9 7 5 5 _ T o c 5 3 0 1 9 7 9 7 4 5 _ T o c 5 3 0 1 9 7 9 7 3 5 _ T o c 5 3 0 1 9 7 9 7 2 5 _ T o c 5 3 0 1 9 7 9 7 1 5 _ T o c 5 3 0 1 9 7 9 7 0 5 _ T o c 5 3 0 1 9 7 9 6 9 5 _ T o c 5 3 0 1 9 7 9 6 8 5 _ T o c 5 3 0 1 9 7 9 6 7 5 _ T o c 5 3 0 1 9 7 9 6 6 5 _ T o c 5 3 0 1 9 7 9 6 5 5 _ T o c 5 3 0 1 9 7 9 6 4 5 _ T o c 5 3 0 1 9 7 9 6 3 5 _ T o c 5 3 0 1 9 7 9 6 2 5 _ T o c 5 3 0 1 9 7 9 6 1 5 _ T o c 5 3 0 1 9 7 9 6 0 5 _ T o c 5 3 0 1 9 7 9 5 9 5 _ T o c 5 3 0 1 9 7 9 5 8 5 _ T o c 5 3 0 1 9 7 9 5 7 5 _ T o c 5 3 0 1 9 7 9 5 6 5 _ T o c 5 3 0 1 9 7 9 5 5 5 _ T o c 5 3 0 1 9 7 9 5 4 5 _ T o c 5 3 0 1 9 7 9 5 3 5 _ T o c 5 3 0 1 9 7 9 5 2 5 _ T o c 5 3 0 1 9 7 9 5 1 5 _ T o c 5 3 0 1 9 7 9 5 0 5 _ T o c 5 3 0 1 9 7 9 4 9 5 _ T o c 5 3 0 1 9 7 9 4 8 5 | _ T o c 5 3 0 1 9 7 9 4 7 5 v _ T o c 5 3 0 1 9 7 9 4 6 5 p _ T o c 5 3 0 1 9 7 9 4 5 5 j _ T o c 5 3 0 1 9 7 9 4 4 * a _ T o c 1 5 6 1 9 9 + [ _ T o c 1 5 6 1 9 8 $ U _ T o c 1 5 6 1 9 7 % O _ T o c 1 5 6 1 9 6 & I _ T o c 1 5 6 1 9 5 ' C _ T o c 1 5 6 1 9 4 = _ T o c 1 5 6 1 9 3 ! 7 _ T o c 1 5 6 1 9 2 " 1 _ T o c 1 5 6 1 9 1 # + _ T o c 1 5 6 1 9 0 * % _ T o c 1 5 6 1 8 9 + _ T o c 1 5 6 1 8 8 $ _ T o c 1 5 6 1 8 7 % _ T o c 1 5 6 1 8 6 &
_ T o c 1 5 6 1 8 5 ' _ T o c 1 5 6 1 8 4 _ T o c 1 5 6 1 8 3 ! _ T o c 1 5 6 1 8 2 " _ T o c 1 5 6 1 8 1 # _ T o c 1 5 6 1 8 0 * _ T o c 1 5 6 1 7 9 + _ T o c 1 5 6 1 7 8 $ _ T o c 1 5 6 1 7 7 % _ T o c 1 5 6 1 7 6 & _ T o c 1 5 6 1 7 5 ' _ T o c 1 5 6 1 7 4 _ T o c 1 5 6 1 7 3 ! _ T o c 1 5 6 1 7 2 " _ T o c 1 5 6 1 7 1 # _ T o c 1 5 6 1 7 0 * _ T o c 1 5 6 1 6 9 + _ T o c 1 5 6 1 6 8 $ _ T o c 1 5 6 1 6 7 % _ T o c 1 5 6 1 6 6 & _ T o c 1 5 6 1 6 5 ' _ T o c 1 5 6 1 6 4 _ T o c 1 5 6 1 6 3 ! _ T o c 1 5 6 1 6 2 " } _ T o c 1 5 6 1 6 1 # w _ T o c 1 5 6 1 6 0 * q _ T o c 1 5 6 1 5 9 + k _ T o c 1 5 6 1 5 8 $ e _ T o c 1 5 6 1 5 7 % _ _ T o c 1 5 6 1 5 6 & Y _ T o c 1 5 6 1 5 5 ' S _ T o c 1 5 6 1 5 4 M _ T o c 1 5 6 1 5 3 ! G _ T o c 1 5 6 1 5 2 " A _ T o c 1 5 6 1 5 1 # ; _ T o c 1 5 6 1 5 0 * 5 _ T o c 1 5 6 1 4 9 + / _ T o c 1 5 6 1 4 8 $ ) _ T o c 1 5 6 1 4 7 % # _ T o c 1 5 6 1 4 6 & _ T o c 1 5 6 1 4 5 ' _ T o c 1 5 6 1 4 4 _ T o c 1 5 6 1 4 3 ! _ T o c 1 5 6 1 4 2 " _ T o c 1 5 6 1 4 1 K h t t p : / / w w w . o p e n c o r e s . o r g / " y ( h t t p : / / w w w . o p e n c o r e s . o r g / l o g o s / j n g 3 . g i f " y ( h t t p : / / w w w . o p e n c o r e s . o r g / l o g o s / j n g 3 . g i f \ & w i s h b o n e _ c o m p a t i b l e . g i f
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Specifications Template Title G 8 @ _PID_HLINKS A G d = T _ T o c 5 3 0 1 9 8 1 1 0 = N _ T o c 5 3 0 1 9 8 1 0 9 = H _ T o c 5 3 0 1 9 8 1 0 8 = B _ T o c 5 3 0 1 9 8 1 0 7 = < _ T o c 5 3 0 1 9 8 1 0 6 = 6 _ T o c 5 3 0 1 9 8 1 0 5 = 0 _ T o c 5 3 0 1 9 8 1 0 4 = * _ T o c 5 3 0 1 9 8 1 0 3 = $ _ T o c 5 3 0 1 9 8 1 0 2 = _ T o c 5 3 0 1 9 8 1 0 1 = _ T o c 5 3 0 1 9 8 1 0 0 < _ T o c 5 3 0 1 9 8 0 9 9 < _ T o c 5 3 0 1 9 8 0 9 8 < _ T o c 5 3 0 1 9 8 0 9 7 < _ T o c 5 3 0 1 9 8 0 9 6 < _ T o c 5 3 0 1 9 8 0 9 5 < _ T o c 5 3 0 1 9 8 0 9 4 < _ T o c 5 3 0 1 9 8 0 9 3 < _ T o c 5 3 0 1 9 8 0 9 2 < _ T o c 5 3 0 1 9 8 0 9 1 < _ T o c 5 3 0 1 9 8 0 9 0 < _ T o c 5 3 0 1 9 8 0 8 9 < _ T o c 5 3 0 1 9 8 0 8 8 < _ T o c 5 3 0 1 9 8 0 8 7 < _ T o c 5 3 0 1 9 8 0 8 6 < _ T o c 5 3 0 1 9 8 0 8 5 < _ T o c 5 3 0 1 9 8 0 8 4 < _ T o c 5 3 0 1 9 8 0 8 3 < _ T o c 5 3 0 1 9 8 0 8 2 < _ T o c 5 3 0 1 9 8 0 8 1 < _ T o c 5 3 0 1 9 8 0 8 0 < _ T o c 5 3 0 1 9 8 0 7 9 < _ T o c 5 3 0 1 9 8 0 7 8 < _ T o c 5 3 0 1 9 8 0 7 7 < _ T o c 5 3 0 1 9 8 0 7 6 < _ T o c 5 3 0 1 9 8 0 7 5 < | _ T o c 5 3 0 1 9 8 0 7 4 < v _ T o c 5 3 0 1 9 8 0 7 3 < p _ T o c 5 3 0 1 9 8 0 7 2 < j _ T o c 5 3 0 1 9 8 0 7 1 < d _ T o c 5 3 0 1 9 8 0 7 0 < ^ _ T o c 5 3 0 1 9 8 0 6 9 < X _ T o c 5 3 0 1 9 8 0 6 8 < R _ T o c 5 3 0 1 9 8 0 6 7 < L _ T o c 5 3 0 1 9 8 0 6 6 < F _ T o c 5 3 0 1 9 8 0 6 5 < @ _ T o c 5 3 0 1 9 8 0 6 4 < : _ T o c 5 3 0 1 9 8 0 6 3 < 4 _ T o c 5 3 0 1 9 8 0 6 2 < . _ T o c 5 3 0 1 9 8 0 6 1 < ( _ T o c 5 3 0 1 9 8 0 6 0 < " _ T o c 5 3 0 1 9 8 0 5 9 < _ T o c 5 3 0 1 9 8 0 5 8 < _ T o c 5 3 0 1 9 8 0 5 7 <
_ T o c 5 3 0 1 9 8 0 5 6 < _ T o c 5 3 0 1 9 8 0 5 5 < _ T o c 5 3 0 1 9 8 0 5 4 < _ T o c 5 3 0 1 9 8 0 5 3 < _ T o c 5 3 0 1 9 8 0 5 2 < _ T o c 5 3 0 1 9 8 0 5 1 < _ T o c 5 3 0 1 9 8 0 5 0 < _ T o c 5 3 0 1 9 8 0 4 9 < _ T o c 5 3 0 1 9 8 0 4 8 < _ T o c 5 3 0 1 9 8 0 4 7 < _ T o c 5 3 0 1 9 8 0 4 6 < _ T o c 5 3 0 1 9 8 0 4 5 < _ T o c 5 3 0 1 9 8 0 4 4 < _ T o c 5 3 0 1 9 8 0 4 3 < _ T o c 5 3 0 1 9 8 0 4 2 < _ T o c 5 3 0 1 9 8 0 4 1 < _ T o c 5 3 0 1 9 8 0 4 0 < o c 5 3 0 1 9 7 9 8 8 5 l _ T o c 5 3 0 1 9 7 9 8 7 5 f _ T o c 5 3 0 1 9 7 9 8 6 5 ` _ T o c 5 3 0 1 9 7 9 8 5 5 Z _ T o c 5 3 0 1 9 7 9 8 4 5 T _ T o c 5 3 0 1 9 7 9 8 3 5 N _ T o c 5 3 0 1 9 7 9 8 2 5 H _ T o c 5 3 0 1 9 7 9 8 1 5 B _ T o c 5 3 0 1 9 7 9 8 0 5 < _ T o c 5 3 0 1 9 7 9 7 9 5 6 _ T o c 5 3 0 1 9 7 9 7 8 5 0 _ T o c 5 3 0 1 9 7 9 7 7 5 * _ T o c 5 3 0 1 9 7 9 7 6 5 $ _ T o c 5 3 0 1 9 7 9 7 5 5 _ T o c 5 3 0 1 9 7 9 7 4 5 _ T o c 5 3 0 1 9 7 9 7 3 5 _ T o c 5 3 0 1 9 7 9 7 2 5 _ T o c 5 3 0 1 9 7 9 7 1 5 _ T o c 5 3 0 1 9 7 9 7 0 5 _ T o c 5 3 0 1 9 7 9 6 9 5 _ T o c 5 3 0 1 9 7 9 6 8 5 _ T o c 5 3 0 1 9 7 9 6 7 5 _ T o c 5 3 0 1 9 7 9 6 6 5 _ T o c 5 3 0 1 9 7 9 6 5 5 _ T o c 5 3 0 1 9 7 9 6 4 5 _ T o c 5 3 0 1 9 7 9 6 3 5 _ T o c 5 3 0 1 9 7 9 6 2 5 _ T o c 5 3 0 1 9 7 9 6 1 5 _ T o c 5 3 0 1 9 7 9 6 0 5 _ T o c 5 3 0 1 9 7 9 5 9 5 _ T o c 5 3 0 1 9 7 9 5 8 5 _ T o c 5 3 0 1 9 7 9 5 7 5 _ T o c 5 3 0 1 9 7 9 5 6 5 _ T o c 5 3 0 1 9 7 9 5 5 5 _ T o c 5 3 0 1 9 7 9 5 4 5 _ T o c 5 3 0 1 9 7 9 5 3 5 _ T o c 5 3 0 1 9 7 9 5 2 5 _ T o c 5 3 0 1 9 7 9 5 1 5 _ T o c 5 3 0 1 9 7 9 5 0 5 _ T o c 5 3 0 1 9 7 9 4 9 5 _ T o c 5 3 0 1 9 7 9 4 8 5 | _ T o c 5 3 0 1 9 7 9 4 7 5 v _ T o c 5 3 0 1 9 7 9 4 6 5 p _ T o c 5 3 0 1 9 7 9 4 5 5 j _ T o c 5 3 0 1 9 7 9 4 4 * a _ T o c 1 5 6 1 9 9 + [ _ T o c 1 5 6 1 9 8 $ U _ T o c 1 5 6 1 9 7 % O _ T o c 1 5 6 1 9 6 & I _ T o c 1 5 6 1 9 5 ' C _ T o c 1 5 6 1 9 4 = _ T o c 1 5 6 1 9 3 ! 7 _ T o c 1 5 6 1 9 2 " 1 _ T o c 1 5 6 1 9 1 # + _ T o c 1 5 6 1 9 0 * % _ T o c 1 5 6 1 8 9 + _ T o c 1 5 6 1 8 8 $ _ T o c 1 5 6 1 8 7 % _ T o c 1 5 6 1 8 6 &
_ T o c 1 5 6 1 8 5 ' _ T o c 1 5 6 1 8 4 _ T o c 1 5 6 1 8 3 ! _ T o c 1 5 6 1 8 2 " _ T o c 1 5 6 1 8 1 # _ T o c 1 5 6 1 8 0 * _ T o c 1 5 6 1 7 9 + _ T o c 1 5 6 1 7 8 $ _ T o c 1 5 6 1 7 7 % _ T o c 1 5 6 1 7 6 & _ T o c 1 5 6 1 7 5 ' _ T o c 1 5 6 1 7 4 _ T o c 1 5 6 1 7 3 ! _ T o c 1 5 6 1 7 2 " _ T o c 1 5 6 1 7 1 # _ T o c 1 5 6 1 7 0 * _ T o c 1 5 6 1 6 9 + _ T o c 1 5 6 1 6 8 $ _ T o c 1 5 6 1 6 7 % _ T o c 1 5 6 1 6 6 & _ T o c 1 5 6 1 6 5 ' _ T o c 1 5 6 1 6 4 _ T o c 1 5 6 1 6 3 ! _ T o c 1 5 6 1 6 2 " } _ T o c 1 5 6 1 6 1 # w _ T o c 1 5 6 1 6 0 * q _ T o c 1 5 6 1 5 9 + k _ T o c 1 5 6 1 5 8 $ e _ T o c 1 5 6 1 5 7 % _ _ T o c 1 5 6 1 5 6 & Y _ T o c 1 5 6 1 5 5 ' S _ T o c 1 5 6 1 5 4 M _ T o c 1 5 6 1 5 3 ! G _ T o c 1 5 6 1 5 2 " A _ T o c 1 5 6 1 5 1 # ; _ T o c 1 5 6 1 5 0 * 5 _ T o c 1 5 6 1 4 9 + / _ T o c 1 5 6 1 4 8 $ ) _ T o c 1 5 6 1 4 7 % # _ T o c 1 5 6 1 4 6 & _ T o c 1 5 6 1 4 5 ' _ T o c 1 5 6 1 4 4 _ T o c 1 5 6 1 4 3 ! _ T o c 1 5 6 1 4 2 " _ T o c 1 5 6 1 4 1 K h t t p : / / w w w . o p e n c o r e s . o r g / " y ( h t t p : / / w w w . o p e n c o r e s . o r g / l o g o s / j n g 3 . g i f " y ( h t t p : / / w w w . o p e n c o r e s . o r g / l o g o s / j n g 3 . g i f \ & w i s h b o n e _ c o m p a t i b l e . g i f
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