-cdslib ../bin/cds.lib
|
-cdslib ../bin/cds.lib
|
-hdlvar ../bin/hdl.var
|
-hdlvar ../bin/hdl.var
|
-logfile ../log/ncvlog_sim.log
|
-logfile ../log/ncvlog_sim.log
|
-update
|
-update
|
-messages
|
-messages
|
-INCDIR ../../../bench/verilog
|
-INCDIR ../../../bench/verilog
|
-INCDIR ../../../rtl/verilog
|
-INCDIR ../../../rtl/verilog
|
../../../bench/verilog/wb_master32.v
|
../../../bench/verilog/wb_master32.v
|
../../../bench/verilog/wb_master_behavioral.v
|
../../../bench/verilog/wb_master_behavioral.v
|
../../../bench/verilog/system.v
|
../../../bench/verilog/system.v
|
../../../bench/verilog/pci_blue_arbiter.v
|
../../../bench/verilog/pci_blue_arbiter.v
|
../../../bench/verilog/pci_bus_monitor.v
|
../../../bench/verilog/pci_bus_monitor.v
|
../../../bench/verilog/pci_behaviorial_device.v
|
../../../bench/verilog/pci_behaviorial_device.v
|
../../../bench/verilog/pci_behaviorial_master.v
|
../../../bench/verilog/pci_behaviorial_master.v
|
../../../bench/verilog/pci_behaviorial_target.v
|
../../../bench/verilog/pci_behaviorial_target.v
|
../../../bench/verilog/wb_slave_behavioral.v
|
../../../bench/verilog/wb_slave_behavioral.v
|
../../../bench/verilog/wb_bus_mon.v
|
../../../bench/verilog/wb_bus_mon.v
|
../../../bench/verilog/pci_behavioral_iack_target.v
|
../../../bench/verilog/pci_behavioral_iack_target.v
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
../../../bench/verilog/pci_unsupported_commands_master.v
|
|
|
