/*
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/*
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* User defines for synthesizing RTC IP core
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* User defines for synthesizing RTC IP core
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*
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*
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*/
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*/
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TOPLEVEL = TOP
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TOPLEVEL = TOP
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include select_tech.inc
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include select_tech.inc
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PCI_CLK = CLK
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PCI_CLK = CLK
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WB_CLK = CLK_I
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WB_CLK = CLK_I
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RST = RST_I
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RST = RST_I
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PCI_CLK_PERIOD = 15 /* 66 MHz */
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PCI_CLK_PERIOD = 15 /* 66 MHz */
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WB_CLK_PERIOD = 5 /* 200 MHz */
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WB_CLK_PERIOD = 5 /* 200 MHz */
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MAX_AREA = 0 /* Push hard */
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MAX_AREA = 0 /* Push hard */
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DO_UNGROUP = yes /* yes, no */
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DO_UNGROUP = yes /* yes, no */
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DO_VERIFY = no /* yes, no */
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DO_VERIFY = no /* yes, no */
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CHECK = no /* yes, no */
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CHECK = no /* yes, no */
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/* Set some basic variables related to environment */
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/* Set some basic variables related to environment */
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include set_env.inc
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include set_env.inc
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STAGE = final
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STAGE = final
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/* Load libraries */
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/* Load libraries */
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include tech_ + TECH + .inc
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include tech_ + TECH + .inc
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/* Load HDL source files */
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/* Load HDL source files */
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/*include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log*/
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/*include read_design.inc > LOG_PATH + read_design_ + TOPLEVEL + .log*/
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include analyze_design.inc > LOG_PATH + analyze_design_ + TOPLEVEL + .log
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include analyze_design.inc > LOG_PATH + analyze_design_ + TOPLEVEL + .log
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include elaborate_design.inc > LOG_PATH + elaborate_design_ + TOPLEVEL + .log
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include elaborate_design.inc > LOG_PATH + elaborate_design_ + TOPLEVEL + .log
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/* Set design top */
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/* Set design top */
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current_design TOPLEVEL
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current_design TOPLEVEL
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/* Link all blocks and uniquify them */
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/* Link all blocks and uniquify them */
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link
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link
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uniquify
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uniquify
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if (CHECK == "yes"){
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if (CHECK == "yes"){
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check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
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check_design > LOG_PATH + check_design_ + TOPLEVEL + .log
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}
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}
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create_clock WB_CLK -period WB_CLK_PERIOD
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create_clock WB_CLK -period WB_CLK_PERIOD
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create_clock PCI_CLK -period PCI_CLK_PERIOD
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create_clock PCI_CLK -period PCI_CLK_PERIOD
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/* Apply PCI constraints */
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/* Apply PCI constraints */
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include cons_pci_ports.inc
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include cons_pci_ports.inc
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include cons_wb_ports.inc
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include cons_wb_ports.inc
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/* Apply technology constraints */
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/* Apply technology constraints */
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if (TECH == "vs_umc18") {
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if (TECH == "vs_umc18") {
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include cons_vs_umc18.inc
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include cons_vs_umc18.inc
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} else if (TECH == "art_umc18") {
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} else if (TECH == "art_umc18") {
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include cons_art_umc18.inc
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include cons_art_umc18.inc
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} else {
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} else {
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echo "Error: Unsupported technology"
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echo "Error: Unsupported technology"
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exit
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exit
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}
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}
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/* Lets do basic synthesis */
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/* Lets do basic synthesis */
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if (DO_UNGROUP == "yes") {
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if (DO_UNGROUP == "yes") {
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ungroup -all -flatten
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ungroup -all -flatten
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}
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}
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compile -boundary_optimization -map_effort low
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compile -boundary_optimization -map_effort low
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/* Dump gate-level from incremental synthesis */
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/* Dump gate-level from incremental synthesis */
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include save_design.inc
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include save_design.inc
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/* Generate reports for incremental synthesis */
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/* Generate reports for incremental synthesis */
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include reports.inc
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include reports.inc
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/* Verify design */
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/* Verify design */
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if (DO_VERIFY == "yes") {
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if (DO_VERIFY == "yes") {
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compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
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compile -no_map -verify > LOG_PATH + verify_ + TOPLEVEL + .log
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}
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}
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/* Finish */
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/* Finish */
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sh date
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sh date
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exit
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exit
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