%PDF-1.2
%âãÏÓ
|
%PDF-1.2
%âãÏÓ
|
1149 0 obj
<<
/Linearized 1
/O 1151
/H [ 2595 1703 ]
/L 718903
/E 77297
/N 94
/T 695803
>>
endobj
xref
1149 105
0000000016 00000 n
|
1149 0 obj
<<
/Linearized 1
/O 1151
/H [ 2595 1703 ]
/L 718903
/E 77297
/N 94
/T 695803
>>
endobj
xref
1149 105
0000000016 00000 n
|
0000002456 00000 n
|
0000002456 00000 n
|
0000004298 00000 n
|
0000004298 00000 n
|
0000004460 00000 n
|
0000004460 00000 n
|
0000004530 00000 n
|
0000004530 00000 n
|
0000004684 00000 n
|
0000004684 00000 n
|
0000004848 00000 n
|
0000004848 00000 n
|
0000005017 00000 n
|
0000005017 00000 n
|
0000005132 00000 n
|
0000005132 00000 n
|
0000005298 00000 n
|
0000005298 00000 n
|
0000005464 00000 n
|
0000005464 00000 n
|
0000005626 00000 n
|
0000005626 00000 n
|
0000005758 00000 n
|
0000005758 00000 n
|
0000005885 00000 n
|
0000005885 00000 n
|
0000006052 00000 n
|
0000006052 00000 n
|
0000006189 00000 n
|
0000006189 00000 n
|
0000006354 00000 n
|
0000006354 00000 n
|
0000006486 00000 n
|
0000006486 00000 n
|
0000006623 00000 n
|
0000006623 00000 n
|
0000006779 00000 n
|
0000006779 00000 n
|
0000006925 00000 n
|
0000006925 00000 n
|
0000007093 00000 n
|
0000007093 00000 n
|
0000007252 00000 n
|
0000007252 00000 n
|
0000007374 00000 n
|
0000007374 00000 n
|
0000007506 00000 n
|
0000007506 00000 n
|
0000007651 00000 n
|
0000007651 00000 n
|
0000007819 00000 n
|
0000007819 00000 n
|
0000007995 00000 n
|
0000007995 00000 n
|
0000008118 00000 n
|
0000008118 00000 n
|
0000008302 00000 n
|
0000008302 00000 n
|
0000008443 00000 n
|
0000008443 00000 n
|
0000008626 00000 n
|
0000008626 00000 n
|
0000008822 00000 n
|
0000008822 00000 n
|
0000008974 00000 n
|
0000008974 00000 n
|
0000009128 00000 n
|
0000009128 00000 n
|
0000009291 00000 n
|
0000009291 00000 n
|
0000009455 00000 n
|
0000009455 00000 n
|
0000009585 00000 n
|
0000009585 00000 n
|
0000009724 00000 n
|
0000009724 00000 n
|
0000009875 00000 n
|
0000009875 00000 n
|
0000010046 00000 n
|
0000010046 00000 n
|
0000010211 00000 n
|
0000010211 00000 n
|
0000010324 00000 n
|
0000010324 00000 n
|
0000010449 00000 n
|
0000010449 00000 n
|
0000010588 00000 n
|
0000010588 00000 n
|
0000010765 00000 n
|
0000010765 00000 n
|
0000010946 00000 n
|
0000010946 00000 n
|
0000011123 00000 n
|
0000011123 00000 n
|
0000011255 00000 n
|
0000011255 00000 n
|
0000011404 00000 n
|
0000011404 00000 n
|
0000011569 00000 n
|
0000011569 00000 n
|
0000011693 00000 n
|
0000011693 00000 n
|
0000011822 00000 n
|
0000011822 00000 n
|
0000011954 00000 n
|
0000011954 00000 n
|
0000012086 00000 n
|
0000012086 00000 n
|
0000012267 00000 n
|
0000012267 00000 n
|
0000012399 00000 n
|
0000012399 00000 n
|
0000012548 00000 n
|
0000012548 00000 n
|
0000012717 00000 n
|
0000012717 00000 n
|
0000012845 00000 n
|
0000012845 00000 n
|
0000012969 00000 n
|
0000012969 00000 n
|
0000013100 00000 n
|
0000013100 00000 n
|
0000013231 00000 n
|
0000013231 00000 n
|
0000013383 00000 n
|
0000013383 00000 n
|
0000013527 00000 n
|
0000013527 00000 n
|
0000013679 00000 n
|
0000013679 00000 n
|
0000013820 00000 n
|
0000013820 00000 n
|
0000013985 00000 n
|
0000013985 00000 n
|
0000014096 00000 n
|
0000014096 00000 n
|
0000014267 00000 n
|
0000014267 00000 n
|
0000014390 00000 n
|
0000014390 00000 n
|
0000014519 00000 n
|
0000014519 00000 n
|
0000014644 00000 n
|
0000014644 00000 n
|
0000014821 00000 n
|
0000014821 00000 n
|
0000015002 00000 n
|
0000015002 00000 n
|
0000015162 00000 n
|
0000015162 00000 n
|
0000015286 00000 n
|
0000015286 00000 n
|
0000015415 00000 n
|
0000015415 00000 n
|
0000015547 00000 n
|
0000015547 00000 n
|
0000015711 00000 n
|
0000015711 00000 n
|
0000015839 00000 n
|
0000015839 00000 n
|
0000015963 00000 n
|
0000015963 00000 n
|
0000016094 00000 n
|
0000016094 00000 n
|
0000016225 00000 n
|
0000016225 00000 n
|
0000016349 00000 n
|
0000016349 00000 n
|
0000016472 00000 n
|
0000016472 00000 n
|
0000016615 00000 n
|
0000016615 00000 n
|
0000016853 00000 n
|
0000016853 00000 n
|
0000017378 00000 n
|
0000017378 00000 n
|
0000017560 00000 n
|
0000017560 00000 n
|
0000017778 00000 n
|
0000017778 00000 n
|
0000018473 00000 n
|
0000018473 00000 n
|
0000019070 00000 n
|
0000019070 00000 n
|
0000019281 00000 n
|
0000019281 00000 n
|
0000019471 00000 n
|
0000019471 00000 n
|
0000020040 00000 n
|
0000020040 00000 n
|
0000020492 00000 n
|
0000020492 00000 n
|
0000020684 00000 n
|
0000020684 00000 n
|
0000021160 00000 n
|
0000021160 00000 n
|
0000021352 00000 n
|
0000021352 00000 n
|
0000021847 00000 n
|
0000021847 00000 n
|
0000021927 00000 n
|
0000021927 00000 n
|
0000045798 00000 n
|
0000045798 00000 n
|
0000002595 00000 n
|
0000002595 00000 n
|
0000004274 00000 n
|
0000004274 00000 n
|
trailer
<<
/Size 1254
/Info 1148 0 R
/Root 1150 0 R
/Prev 695791
/ID[]
>>
startxref
0
%%EOF
1150 0 obj
<<
/Type /Catalog
/Pages 1138 0 R
/Outlines 1152 0 R
/OpenAction [ 1151 0 R /FitH 796 ]
/PageMode /UseOutlines
>>
endobj
1252 0 obj
<< /S 2775 /O 3100 /Filter /FlateDecode /Length 1253 0 R >>
stream
|
trailer
<<
/Size 1254
/Info 1148 0 R
/Root 1150 0 R
/Prev 695791
/ID[]
>>
startxref
0
%%EOF
1150 0 obj
<<
/Type /Catalog
/Pages 1138 0 R
/Outlines 1152 0 R
/OpenAction [ 1151 0 R /FitH 796 ]
/PageMode /UseOutlines
>>
endobj
1252 0 obj
<< /S 2775 /O 3100 /Filter /FlateDecode /Length 1253 0 R >>
stream
|
H‰ÜV]lU>³3Ýnÿè"6…«ËO‰…ŒºcP«vf˜»Ã¶³eiEûƒ0L(ÐÂR
|
H‰ÜV]lU>³3Ýnÿè"6…«ËO‰…ŒºcP«vf˜»Ã¶³eiEûƒ0L(ÐÂR
|
ú@° !"*šÅDðÁ„J@kbâF_HÔ€ÑøÓçÎi»ÛÆøì$3;çžs¾óïž;- ° …UPà}‚0q!|À¯Â„³nOGíL/¤ †LÛòyðYŒ·Üp:€žš˜m_<‚C¦½Xà †x0¤x|½þHzMÇV²“c¯†6~án›ñŸÎ¼Ñ?ÛÓYÕ÷!{Ëìi¨mñ0Ÿ§ŸK…¹ÒÙFþ³†ÀhÞßž:þJÇÂHñ÷/%S
!Ï^þ[¾znÑ›ìV8˜ ubÁ*þ¢a¹_f¥ãW^ô=æ©ço¤W¬Ô±/¥¯.Ž”Æ=¿^-Y>2ãÛdÞ6kÛúÙgÌÓüü†Ò÷ÙÓüwé`cÙá‚àÕµ£úâ½@¦£~¤ä«üOžó/óÍe‹ù›#ù;óçxJÌŠ=?Îz÷nó"ñ榓ÑúÅá“jŵLJOýqmhøÔo{•û±Ë½ÊØ'w{›¾¾t·éþÒw)^úé©Ðíó9ª)‚$–¸¾¹%¦X²ª}qQôèúæX:Qô¾xTÕÖÇš[TK–ExIÐU,‘1ÃÂw
ß™¤º‘qcj¤ Y¢¦öÅí,Ieeû¾ÖýÛ:7ØÑOr-ÁÄý;6(òþÖmÛ÷Ù\¢
|
ú@° !"*šÅDðÁ„J@kbâF_HÔ€ÑøÓçÎi»ÛÆøì$3;çžs¾óïž;- ° …UPà}‚0q!|À¯Â„³nOGíL/¤ †LÛòyðYŒ·Üp:€žš˜m_<‚C¦½Xà †x0¤x|½þHzMÇV²“c¯†6~án›ñŸÎ¼Ñ?ÛÓYÕ÷!{Ëìi¨mñ0Ÿ§ŸK…¹ÒÙFþ³†ÀhÞßž:þJÇÂHñ÷/%S
!Ï^þ[¾znÑ›ìV8˜ ubÁ*þ¢a¹_f¥ãW^ô=æ©ço¤W¬Ô±/¥¯.Ž”Æ=¿^-Y>2ãÛdÞ6kÛúÙgÌÓüü†Ò÷ÙÓüwé`cÙá‚àÕµ£úâ½@¦£~¤ä«üOžó/óÍe‹ù›#ù;óçxJÌŠ=?Îz÷nó"ñ榓ÑúÅá“jŵLJOýqmhøÔo{•û±Ë½ÊØ'w{›¾¾t·éþÒw)^úé©Ðíó9ª)‚$–¸¾¹%¦X²ª}qQôèúæX:Qô¾xTÕÖÇš[TK–ExIÐU,‘1ÃÂw
ß™¤º‘qcj¤ Y¢¦öÅí,Ieeû¾ÖýÛ:7ØÑOr-ÁÄý;6(òþÖmÛ÷Ù\¢
|
2
‹ð¹ußöýÛK4T
QqÍd4%-¡&£ú+M”¿Bª&’„‚UTM¶$Q0’ ê7,YIŠRBÐþ¢ºašJü"²3”×^•n<”LDu›œÝ¦¯‚eˆí–*‡ÐÉUN1pÁ$¬í’¡KØ®M$Ý%TIÄb:¢“ú6¤Œ<³½˜@¼SªLáo)²!ˆ’ª%’NnŸ¥©JÛ ÜÕMdºi°K-a[bÍNšÚÖ58ÐMVÆ·™*ç±i°Â:$s9¡Â‚"Q]S»Û/ÖÒŒc„;&Úv2a×gûg‘bvµ
hªÍÂPìÝR5*<*gÎp鿨EøÙå–û{Xn?¢¨ÉDÖÜ&»¡,™³ŒœÎíØ»YV-Õ۳騯h²Ô›BKÅéӣû¶ì&MŠ$íÚ½e˜`™{ŽwPj8NÇsO‡¼©§÷hÊnÆV„l“¬hÓHšed³ÓBL49=gV)÷œÙ#œÃGÚÉyrO$ù„F)ññ¼Ið<©—úÉî~û›Ì̲@ ’.86tÙ«q'*b1°Ÿ‚ Æm/ÀÜÊN@¿ó©§‰è+[žåaÊ×P;»bç;¼ˆ™MƒÃNt°j¹Ã׎ñÆ[©éL¤PžJš€]ŽNH$w’!쥩‘l¤ÊÊp˜Ö‡—8ä]A…#`‚n‚ïÜ0YFÊÜæ(ÅEêa\=,Jc‚•U´8V
|
2
‹ð¹ußöýÛK4T
QqÍd4%-¡&£ú+M”¿Bª&’„‚UTM¶$Q0’ ê7,YIŠRBÐþ¢ºašJü"²3”×^•n<”LDu›œÝ¦¯‚eˆí–*‡ÐÉUN1pÁ$¬í’¡KØ®M$Ý%TIÄb:¢“ú6¤Œ<³½˜@¼SªLáo)²!ˆ’ª%’NnŸ¥©JÛ ÜÕMdºi°K-a[bÍNšÚÖ58ÐMVÆ·™*ç±i°Â:$s9¡Â‚"Q]S»Û/ÖÒŒc„;&Úv2a×gûg‘bvµ
hªÍÂPìÝR5*<*gÎp鿨EøÙå–û{Xn?¢¨ÉDÖÜ&»¡,™³ŒœÎíØ»YV-Õ۳騯h²Ô›BKÅéӣû¶ì&MŠ$íÚ½e˜`™{ŽwPj8NÇsO‡¼©§÷hÊnÆV„l“¬hÓHšed³ÓBL49=gV)÷œÙ#œÃGÚÉyrO$ù„F)ññ¼Ið<©—úÉî~û›Ì̲@ ’.86tÙ«q'*b1°Ÿ‚ Æm/ÀÜÊN@¿ó©§‰è+[žåaÊ×P;»bç;¼ˆ™MƒÃNt°j¹Ã׎ñÆ[©éL¤PžJš€]ŽNH$w’!쥩‘l¤ÊÊp˜Ö‡—8ä]A…#`‚n‚ïÜ0YFÊÜæ(ÅEêa\=,Jc‚•U´8V
|
»õ‡°S;.¡æL‰¶MAY7“6ç™LÔÑÒò8úRM\J8ĦÌEVSùâqGH'ŠuìÊì„hÔœŸÈ¸ª“ÕË„ødT›¶úüG5å¡pI5¶ià}–d5”Âe$3’—)Ö‹øÐÑü‹ùÂë÷é³Òóài8ÏÔ°þ¼”×,5ç›1¸·Ø×1#4Ï|á#¦‹Ép
…¡Ùü£æ"ØÌ”³ë¼÷JôRs…vø™¹ÇfJ2Äl†Ncî°£…|s×À§p†}˜mÈ×KÒKÍ-p½cl¦(=Ãœ+¡Í³\j&lM×Â0÷ƒ¯ŽÛo®Ò£æJæüî=·êM‹Â´ÎÛÈù}5yéPúºÙ O1w§(T¦×ñÏ›ï1už/¹{E5eéêô³§º™¹kýlþ?„L/|å¬z‰É˜Ëx@³‚mAS0´¦½8œ“¢"|y ¦ê ‹9°Â
endstream
endobj
1253 0 obj
1581
endobj
1151 0 obj
<<
/Type /Page
/Parent 1137 0 R
/Resources 1235 0 R
/Contents 1239 0 R
/MediaBox [ 0 0 612 792 ]
/CropBox [ 0 0 612 792 ]
/Rotate 0
>>
endobj
1152 0 obj
<<
/Count 82
/First 1153 0 R
/Last 1154 0 R
>>
endobj
1153 0 obj
<<
/Title (Introduction)
/Dest [ 196 0 R /FitH 608 ]
/Parent 1152 0 R
/Next 1188 0 R
/First 1232 0 R
/Last 1233 0 R
/Count 3
>>
endobj
1154 0 obj
<<
/Title (Core HW Configuration)
/Dest [ 1067 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1155 0 R
/First 1156 0 R
/Last 1156 0 R
/Count 1
>>
endobj
1155 0 obj
<<
/Title (Waveforms)
/Dest [ 1009 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1157 0 R
/Next 1154 0 R
/First 1158 0 R
/Last 1159 0 R
/Count 11
>>
endobj
1156 0 obj
<<
/Title (A.1 HW Configuration Parameters)
/Dest [ 1067 0 R /FitH 427 ]
/Parent 1154 0 R
>>
endobj
1157 0 obj
<<
/Title (IO Ports)
/Dest [ 997 0 R /FitH 607 ]
/Parent 1152 0 R
/Prev 1169 0 R
/Next 1155 0 R
/First 1170 0 R
/Last 1171 0 R
/Count 4
>>
endobj
1158 0 obj
<<
/Title (6.1 Wishbone Slave Unit)
/Dest [ 1009 0 R /FitH 483 ]
/Parent 1155 0 R
/Next 1159 0 R
/First 1163 0 R
/Last 1164 0 R
/Count 6
>>
endobj
1159 0 obj
<<
/Title (6.2 PCI Target Unit)
/Dest [ 1047 0 R /FitH 679 ]
/Parent 1155 0 R
/Prev 1158 0 R
/First 1160 0 R
/Last 1161 0 R
/Count 3
>>
endobj
1160 0 obj
<<
/Title (6.1.2 PCI Configuration Accesses)
/Dest [ 1047 0 R /FitH 588 ]
/Parent 1159 0 R
/Next 1162 0 R
>>
endobj
1161 0 obj
<<
/Title (6.2.3 WISHBONE Terminations)
/Dest [ 1061 0 R /FitH 679 ]
/Parent 1159 0 R
/Prev 1162 0 R
>>
endobj
1162 0 obj
<<
/Title (6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles)
/Dest [ 1052 0 R /FitH 679 ]
/Parent 1159 0 R
/Prev 1160 0 R
/Next 1161 0 R
>>
endobj
1163 0 obj
<<
/Title (6.1.1 WISHBONE Configuration Accesses)
/Dest [ 1009 0 R /FitH 391 ]
/Parent 1158 0 R
/Next 1168 0 R
>>
endobj
1164 0 obj
<<
/Title (6.1.4 PCI Terminations)
/Dest [ 1032 0 R /FitH 619 ]
/Parent 1158 0 R
/Prev 1165 0 R
/First 1166 0 R
/Last 1167 0 R
/Count 2
>>
endobj
1165 0 obj
<<
/Title (6.1.3 PCI Cycles)
/Dest [ 1018 0 R /FitH 148 ]
/Parent 1158 0 R
/Prev 1168 0 R
/Next 1164 0 R
>>
endobj
1166 0 obj
<<
/Title (6.1.4.1 Master Initiated Terminations)
/Dest [ 1032 0 R /FitH 584 ]
/Parent 1164 0 R
/Next 1167 0 R
>>
endobj
1167 0 obj
<<
/Title (6.1.4.2 Target Terminations Handled by PCI Master Module)
/Dest [ 1037 0 R /FitH 274 ]
/Parent 1164 0 R
/Prev 1166 0 R
>>
endobj
1168 0 obj
<<
/Title (6.1.2 WISHBONE to PCI Accesses)
/Dest [ 1018 0 R /FitH 679 ]
/Parent 1158 0 R
/Prev 1163 0 R
/Next 1165 0 R
>>
endobj
1169 0 obj
<<
/Title (Registers)
/Dest [ 905 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1174 0 R
/Next 1157 0 R
/First 1175 0 R
/Last 1176 0 R
/Count 13
>>
endobj
1170 0 obj
<<
/Title (5.1 PCI Interface)
/Dest [ 997 0 R /FitH 482 ]
/Parent 1157 0 R
/Next 1171 0 R
/First 1172 0 R
/Last 1173 0 R
/Count 2
>>
endobj
1171 0 obj
<<
/Title (5.2 WISHBONE Interface)
/Dest [ 1003 0 R /FitH 466 ]
/Parent 1157 0 R
/Prev 1170 0 R
>>
endobj
1172 0 obj
<<
/Title (5.1.1 Required PCI Interface Pins)
/Dest [ 997 0 R /FitH 397 ]
/Parent 1170 0 R
/Next 1173 0 R
>>
endobj
1173 0 obj
<<
/Title (5.1.2 Implemented Optional PCI Interface Pins)
/Dest [ 1000 0 R /FitH 195 ]
/Parent 1170 0 R
/Prev 1172 0 R
>>
endobj
1174 0 obj
<<
/Title (Operation)
/Dest [ 821 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1188 0 R
/Next 1169 0 R
/First 1189 0 R
/Last 1190 0 R
/Count 27
>>
endobj
1175 0 obj
<<
/Title (4.1 Register List and Description)
/Dest [ 905 0 R /FitH 427 ]
/Parent 1169 0 R
/Next 1176 0 R
/First 1177 0 R
/Last 1178 0 R
/Count 11
>>
endobj
1176 0 obj
<<
/Title (4.2 Software obligations)
/Dest [ 991 0 R /FitH 443 ]
/Parent 1169 0 R
/Prev 1175 0 R
>>
endobj
1177 0 obj
<<
/Title (4.1.1 WISHBONE Slave Unit Control & Status)
/Dest [ 914 0 R /FitH 453 ]
/Parent 1175 0 R
/Next 1180 0 R
/First 1186 0 R
/Last 1187 0 R
/Count 2
>>
endobj
1178 0 obj
<<
/Title (4.1.4 Interrupt Control & Status Registers)
/Dest [ 985 0 R /FitH 475 ]
/Parent 1175 0 R
/Prev 1179 0 R
>>
endobj
1179 0 obj
<<
/Title (4.1.3 Reporting Registers)
/Dest [ 967 0 R /FitH 281 ]
/Parent 1175 0 R
/Prev 1180 0 R
/Next 1178 0 R
/First 1181 0 R
/Last 1182 0 R
/Count 4
>>
endobj
1180 0 obj
<<
/Title (4.1.2 PCI Target Unit Control & Status)
/Dest [ 930 0 R /FitH 298 ]
/Parent 1175 0 R
/Prev 1177 0 R
/Next 1179 0 R
/First 1185 0 R
/Last 1185 0 R
/Count 1
>>
endobj
1181 0 obj
<<
/Title (4.1.3.1 WISHBONE Slave Unit Error Reporting Registers)
/Dest [ 967 0 R /FitH 173 ]
/Parent 1179 0 R
/Next 1184 0 R
>>
endobj
1182 0 obj
<<
/Title (4.1.3.4 Interrupt Acknowledge Cycle Generation Register)
/Dest [ 985 0 R /FitH 632 ]
/Parent 1179 0 R
/Prev 1183 0 R
>>
endobj
1183 0 obj
<<
/Title (4.1.3.3 Configuration Cycle Generation Registers)
/Dest [ 976 0 R /FitH 307 ]
/Parent 1179 0 R
/Prev 1184 0 R
/Next 1182 0 R
>>
endobj
1184 0 obj
<<
/Title (4.1.3.2 PCI Target Unit Error Reporting Registers)
/Dest [ 970 0 R /FitH 233 ]
/Parent 1179 0 R
/Prev 1181 0 R
/Next 1183 0 R
>>
endobj
1185 0 obj
<<
/Title (4.1.2.2 PCI Image Control and Address Registers)
/Dest [ 943 0 R /FitH 424 ]
/Parent 1180 0 R
>>
endobj
1186 0 obj
<<
/Title (4.1.1.1 WISHBONE Configuration Space BAR)
/Dest [ 914 0 R /FitH 333 ]
/Parent 1177 0 R
/Next 1187 0 R
>>
endobj
1187 0 obj
<<
/Title (4.1.1.2 WISHBONE Image Control and Address Registers)
/Dest [ 921 0 R /FitH 583 ]
/Parent 1177 0 R
/Prev 1186 0 R
>>
endobj
1188 0 obj
<<
/Title (Architecture)
/Dest [ 202 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1153 0 R
/Next 1174 0 R
/First 1216 0 R
/Last 1217 0 R
/Count 16
>>
endobj
1189 0 obj
<<
/Title (3.1 Configuration Space)
/Dest [ 821 0 R /FitH 483 ]
/Parent 1174 0 R
/Next 1194 0 R
/First 1211 0 R
/Last 1212 0 R
/Count 5
>>
endobj
1190 0 obj
<<
/Title (3.6 Interrupts)
/Dest [ 899 0 R /FitH 133 ]
/Parent 1174 0 R
/Prev 1191 0 R
>>
endobj
1191 0 obj
<<
/Title (3.5 Parity)
/Dest [ 899 0 R /FitH 397 ]
/Parent 1174 0 R
/Prev 1192 0 R
/Next 1190 0 R
>>
endobj
1192 0 obj
<<
/Title (3.4 Transaction Ordering)
/Dest [ 895 0 R /FitH 145 ]
/Parent 1174 0 R
/Prev 1193 0 R
/Next 1191 0 R
>>
endobj
1193 0 obj
<<
/Title (3.3 PCI Target Unit)
/Dest [ 865 0 R /FitH 434 ]
/Parent 1174 0 R
/Prev 1194 0 R
/Next 1192 0 R
/First 1195 0 R
/Last 1196 0 R
/Count 8
>>
endobj
1194 0 obj
<<
/Title (3.2 WISHBONE Slave Unit)
/Dest [ 843 0 R /FitH 338 ]
/Parent 1174 0 R
/Prev 1189 0 R
/Next 1193 0 R
/First 1203 0 R
/Last 1204 0 R
/Count 8
>>
endobj
1195 0 obj
<<
/Title (3.3.1 PCI Target Unit Functionality)
/Dest [ 865 0 R /FitH 330 ]
/Parent 1193 0 R
/Next 1198 0 R
/First 1199 0 R
/Last 1200 0 R
/Count 4
>>
endobj
1196 0 obj
<<
/Title (3.3.4 PCI to WISHBONE Read Cycles)
/Dest [ 887 0 R /FitH 279 ]
/Parent 1193 0 R
/Prev 1197 0 R
>>
endobj
1197 0 obj
<<
/Title (3.3.3 PCI to WISHBONE Write Cycles)
/Dest [ 879 0 R /FitH 638 ]
/Parent 1193 0 R
/Prev 1198 0 R
/Next 1196 0 R
>>
endobj
1198 0 obj
<<
/Title (3.3.2 Addressing and Images of the PCI Target Unit)
/Dest [ 869 0 R /FitH 245 ]
/Parent 1193 0 R
/Prev 1195 0 R
/Next 1197 0 R
>>
endobj
1199 0 obj
<<
/Title (3.3.1.1 PCI Target Module)
/Dest [ 869 0 R /FitH 606 ]
/Parent 1195 0 R
/Next 1202 0 R
>>
endobj
1200 0 obj
<<
/Title (3.3.1.4 WISHBONE Master Module)
/Dest [ 869 0 R /FitH 351 ]
/Parent 1195 0 R
/Prev 1201 0 R
>>
endobj
1201 0 obj
<<
/Title (3.3.1.3 PCIR_FIFO)
/Dest [ 869 0 R /FitH 432 ]
/Parent 1195 0 R
/Prev 1202 0 R
/Next 1200 0 R
>>
endobj
1202 0 obj
<<
/Title (3.3.1.2 PCIW_FIFO)
/Dest [ 869 0 R /FitH 513 ]
/Parent 1195 0 R
/Prev 1199 0 R
/Next 1201 0 R
>>
endobj
1203 0 obj
<<
/Title (3.2.1 WISHBONE Slave Unit Functionality)
/Dest [ 846 0 R /FitH 667 ]
/Parent 1194 0 R
/Next 1206 0 R
/First 1207 0 R
/Last 1208 0 R
/Count 4
>>
endobj
1204 0 obj
<<
/Title (3.2.4 WISHBONE to PCI Read Cycles)
/Dest [ 859 0 R /FitH 613 ]
/Parent 1194 0 R
/Prev 1205 0 R
>>
endobj
1205 0 obj
<<
/Title (3.2.3 WISHBONE to PCI Write Cycles)
/Dest [ 853 0 R /FitH 483 ]
/Parent 1194 0 R
/Prev 1206 0 R
/Next 1204 0 R
>>
endobj
1206 0 obj
<<
/Title (3.2.2 Addressing and Images of the WISHBONE Slave Unit)
/Dest [ 849 0 R /FitH 625 ]
/Parent 1194 0 R
/Prev 1203 0 R
/Next 1205 0 R
>>
endobj
1207 0 obj
<<
/Title (3.2.1.1 WISHBONE Slave Module)
/Dest [ 846 0 R /FitH 403 ]
/Parent 1203 0 R
/Next 1210 0 R
>>
endobj
1208 0 obj
<<
/Title (3.2.1.4 PCI Master Module)
/Dest [ 846 0 R /FitH 136 ]
/Parent 1203 0 R
/Prev 1209 0 R
>>
endobj
1209 0 obj
<<
/Title (3.2.1.3 WBR_FIFO)
/Dest [ 846 0 R /FitH 217 ]
/Parent 1203 0 R
/Prev 1210 0 R
/Next 1208 0 R
>>
endobj
1210 0 obj
<<
/Title (3.2.1.2 WBW_FIFO)
/Dest [ 846 0 R /FitH 310 ]
/Parent 1203 0 R
/Prev 1207 0 R
/Next 1209 0 R
>>
endobj
1211 0 obj
<<
/Title (3.1.1 Configuration Space Access for Host Bus Bridges)
/Dest [ 824 0 R /FitH 217 ]
/Parent 1189 0 R
/Next 1215 0 R
>>
endobj
1212 0 obj
<<
/Title (3.1.5 Generating Interrupt Acknowledge Cycles)
/Dest [ 843 0 R /FitH 514 ]
/Parent 1189 0 R
/Prev 1213 0 R
>>
endobj
1213 0 obj
<<
/Title (3.1.4 Generating Configuration Cycles)
/Dest [ 836 0 R /FitH 544 ]
/Parent 1189 0 R
/Prev 1214 0 R
/Next 1212 0 R
>>
endobj
1214 0 obj
<<
/Title (3.1.3 Configuration Cycles)
/Dest [ 833 0 R /FitH 187 ]
/Parent 1189 0 R
/Prev 1215 0 R
/Next 1213 0 R
>>
endobj
1215 0 obj
<<
/Title (3.1.2 Configuration Space Access for Guest Bridges)
/Dest [ 830 0 R /FitH 250 ]
/Parent 1189 0 R
/Prev 1211 0 R
/Next 1214 0 R
>>
endobj
1216 0 obj
<<
/Title (2.1 Overview)
/Dest [ 202 0 R /FitH 483 ]
/Parent 1188 0 R
/Next 1222 0 R
>>
endobj
1217 0 obj
<<
/Title (2.6 Address Translation Logic)
/Dest [ 813 0 R /FitH 679 ]
/Parent 1188 0 R
/Prev 1218 0 R
/First 1219 0 R
/Last 1219 0 R
/Count 1
>>
endobj
1218 0 obj
<<
/Title (2.5 FIFO)
/Dest [ 803 0 R /FitH 415 ]
/Parent 1188 0 R
/Prev 1220 0 R
/Next 1217 0 R
>>
endobj
1219 0 obj
<<
/Title (2.6.1 Description of Address Translation Logic)
/Dest [ 813 0 R /FitH 514 ]
/Parent 1217 0 R
>>
endobj
1220 0 obj
<<
/Title (2.4 Clocks)
/Dest [ 803 0 R /FitH 532 ]
/Parent 1188 0 R
/Prev 1221 0 R
/Next 1218 0 R
>>
endobj
1221 0 obj
<<
/Title (2.3 PCI Target Unit)
/Dest [ 797 0 R /FitH 326 ]
/Parent 1188 0 R
/Prev 1222 0 R
/Next 1220 0 R
/First 1223 0 R
/Last 1223 0 R
/Count 4
>>
endobj
1222 0 obj
<<
/Title (2.2 WISHBONE Slave Unit)
/Dest [ 791 0 R /FitH 364 ]
/Parent 1188 0 R
/Prev 1216 0 R
/Next 1221 0 R
/First 1227 0 R
/Last 1227 0 R
/Count 5
>>
endobj
1223 0 obj
<<
/Title (2.3.1 PCI Target Unit Architecture)
/Dest [ 797 0 R /FitH 136 ]
/Parent 1221 0 R
/First 1224 0 R
/Last 1225 0 R
/Count 3
>>
endobj
1224 0 obj
<<
/Title (2.3.1.1 PCI Target Module)
/Dest [ 800 0 R /FitH 284 ]
/Parent 1223 0 R
/Next 1226 0 R
>>
endobj
1225 0 obj
<<
/Title (2.3.1.3 WISHBONE Master Module)
/Dest [ 803 0 R /FitH 649 ]
/Parent 1223 0 R
/Prev 1226 0 R
>>
endobj
1226 0 obj
<<
/Title (2.3.1.2 PCIR_FIFO)
/Dest [ 800 0 R /FitH 160 ]
/Parent 1223 0 R
/Prev 1224 0 R
/Next 1225 0 R
>>
endobj
1227 0 obj
<<
/Title (2.2.1 WISHBONE Slave Unit Architecture)
/Dest [ 794 0 R /FitH 532 ]
/Parent 1222 0 R
/First 1228 0 R
/Last 1229 0 R
/Count 4
>>
endobj
1228 0 obj
<<
/Title (2.2.1.1 WISHBONE Slave Module)
/Dest [ 794 0 R /FitH 193 ]
/Parent 1227 0 R
/Next 1231 0 R
>>
endobj
1229 0 obj
<<
/Title (2.2.1.4 PCI Master Module)
/Dest [ 797 0 R /FitH 431 ]
/Parent 1227 0 R
/Prev 1230 0 R
>>
endobj
1230 0 obj
<<
/Title (2.2.1.3 WBR_FIFO)
/Dest [ 797 0 R /FitH 543 ]
/Parent 1227 0 R
/Prev 1231 0 R
/Next 1229 0 R
>>
endobj
1231 0 obj
<<
/Title (2.2.1.2 WBW_FIFO)
/Dest [ 797 0 R /FitH 679 ]
/Parent 1227 0 R
/Prev 1228 0 R
/Next 1230 0 R
>>
endobj
1232 0 obj
<<
/Title (1.1 What is a PCI Bridge?)
/Dest [ 196 0 R /FitH 483 ]
/Parent 1153 0 R
/Next 1234 0 R
>>
endobj
1233 0 obj
<<
/Title (1.3 PCI IP Core Features)
/Dest [ 196 0 R /FitH 220 ]
/Parent 1153 0 R
/Prev 1234 0 R
>>
endobj
1234 0 obj
<<
/Title (1.2 PCI IP Core Introduction)
/Dest [ 196 0 R /FitH 355 ]
/Parent 1153 0 R
/Prev 1232 0 R
/Next 1233 0 R
>>
endobj
1235 0 obj
<<
/ProcSet [ /PDF /Text /ImageB ]
/Font << /TT2 1236 0 R /TT4 1240 0 R /TT6 1243 0 R /TT8 1244 0 R /TT10 1246 0 R >>
/XObject << /Im1 1248 0 R >>
/ExtGState << /GS1 1249 0 R >>
/ColorSpace << /Cs5 1237 0 R >>
>>
endobj
1236 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 124
/Widths [ 278 0 0 556 0 0 722 0 333 333 0 0 278 333 278 278 556 556 556 556
556 556 556 0 556 556 333 0 0 584 0 611 0 722 722 722 722 667 611
778 722 278 0 722 611 833 722 778 667 778 722 667 611 722 667 944
667 667 0 333 0 333 0 556 0 556 611 556 611 556 333 611 611 278
0 556 278 889 611 611 611 0 389 556 333 611 556 778 556 556 500
0 280 ]
/Encoding /WinAnsiEncoding
/BaseFont /GECEFO+Arial-BoldMT
/FontDescriptor 1238 0 R
>>
endobj
1237 0 obj
[
/CalRGB << /WhitePoint [ 0.9505 1 1.089 ] /Gamma [ 2.22221 2.22221 2.22221 ]
/Matrix [ 0.4124 0.2126 0.0193 0.3576 0.71519 0.1192 0.1805 0.0722 0.9505 ] >>
]
endobj
1238 0 obj
<<
/Type /FontDescriptor
/Ascent 905
/CapHeight 0
/Descent -211
/Flags 32
/FontBBox [ -628 -376 2034 1048 ]
/FontName /GECEFO+Arial-BoldMT
/ItalicAngle 0
/StemV 133
/FontFile2 1250 0 R
>>
endobj
1239 0 obj
<< /Length 619 /Filter /FlateDecode >>
stream
|
»õ‡°S;.¡æL‰¶MAY7“6ç™LÔÑÒò8úRM\J8ĦÌEVSùâqGH'ŠuìÊì„hÔœŸÈ¸ª“ÕË„ødT›¶úüG5å¡pI5¶ià}–d5”Âe$3’—)Ö‹øÐÑü‹ùÂë÷é³Òóài8ÏÔ°þ¼”×,5ç›1¸·Ø×1#4Ï|á#¦‹Ép
…¡Ùü£æ"ØÌ”³ë¼÷JôRs…vø™¹ÇfJ2Äl†Ncî°£…|s×À§p†}˜mÈ×KÒKÍ-p½cl¦(=Ãœ+¡Í³\j&lM×Â0÷ƒ¯ŽÛo®Ò£æJæüî=·êM‹Â´ÎÛÈù}5yéPúºÙ O1w§(T¦×ñÏ›ï1už/¹{E5eéêô³§º™¹kýlþ?„L/|å¬z‰É˜Ëx@³‚mAS0´¦½8œ“¢"|y ¦ê ‹9°Â
endstream
endobj
1253 0 obj
1581
endobj
1151 0 obj
<<
/Type /Page
/Parent 1137 0 R
/Resources 1235 0 R
/Contents 1239 0 R
/MediaBox [ 0 0 612 792 ]
/CropBox [ 0 0 612 792 ]
/Rotate 0
>>
endobj
1152 0 obj
<<
/Count 82
/First 1153 0 R
/Last 1154 0 R
>>
endobj
1153 0 obj
<<
/Title (Introduction)
/Dest [ 196 0 R /FitH 608 ]
/Parent 1152 0 R
/Next 1188 0 R
/First 1232 0 R
/Last 1233 0 R
/Count 3
>>
endobj
1154 0 obj
<<
/Title (Core HW Configuration)
/Dest [ 1067 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1155 0 R
/First 1156 0 R
/Last 1156 0 R
/Count 1
>>
endobj
1155 0 obj
<<
/Title (Waveforms)
/Dest [ 1009 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1157 0 R
/Next 1154 0 R
/First 1158 0 R
/Last 1159 0 R
/Count 11
>>
endobj
1156 0 obj
<<
/Title (A.1 HW Configuration Parameters)
/Dest [ 1067 0 R /FitH 427 ]
/Parent 1154 0 R
>>
endobj
1157 0 obj
<<
/Title (IO Ports)
/Dest [ 997 0 R /FitH 607 ]
/Parent 1152 0 R
/Prev 1169 0 R
/Next 1155 0 R
/First 1170 0 R
/Last 1171 0 R
/Count 4
>>
endobj
1158 0 obj
<<
/Title (6.1 Wishbone Slave Unit)
/Dest [ 1009 0 R /FitH 483 ]
/Parent 1155 0 R
/Next 1159 0 R
/First 1163 0 R
/Last 1164 0 R
/Count 6
>>
endobj
1159 0 obj
<<
/Title (6.2 PCI Target Unit)
/Dest [ 1047 0 R /FitH 679 ]
/Parent 1155 0 R
/Prev 1158 0 R
/First 1160 0 R
/Last 1161 0 R
/Count 3
>>
endobj
1160 0 obj
<<
/Title (6.1.2 PCI Configuration Accesses)
/Dest [ 1047 0 R /FitH 588 ]
/Parent 1159 0 R
/Next 1162 0 R
>>
endobj
1161 0 obj
<<
/Title (6.2.3 WISHBONE Terminations)
/Dest [ 1061 0 R /FitH 679 ]
/Parent 1159 0 R
/Prev 1162 0 R
>>
endobj
1162 0 obj
<<
/Title (6.2.2 PCI to WISHBONE Accesses With WISHBONE Cycles)
/Dest [ 1052 0 R /FitH 679 ]
/Parent 1159 0 R
/Prev 1160 0 R
/Next 1161 0 R
>>
endobj
1163 0 obj
<<
/Title (6.1.1 WISHBONE Configuration Accesses)
/Dest [ 1009 0 R /FitH 391 ]
/Parent 1158 0 R
/Next 1168 0 R
>>
endobj
1164 0 obj
<<
/Title (6.1.4 PCI Terminations)
/Dest [ 1032 0 R /FitH 619 ]
/Parent 1158 0 R
/Prev 1165 0 R
/First 1166 0 R
/Last 1167 0 R
/Count 2
>>
endobj
1165 0 obj
<<
/Title (6.1.3 PCI Cycles)
/Dest [ 1018 0 R /FitH 148 ]
/Parent 1158 0 R
/Prev 1168 0 R
/Next 1164 0 R
>>
endobj
1166 0 obj
<<
/Title (6.1.4.1 Master Initiated Terminations)
/Dest [ 1032 0 R /FitH 584 ]
/Parent 1164 0 R
/Next 1167 0 R
>>
endobj
1167 0 obj
<<
/Title (6.1.4.2 Target Terminations Handled by PCI Master Module)
/Dest [ 1037 0 R /FitH 274 ]
/Parent 1164 0 R
/Prev 1166 0 R
>>
endobj
1168 0 obj
<<
/Title (6.1.2 WISHBONE to PCI Accesses)
/Dest [ 1018 0 R /FitH 679 ]
/Parent 1158 0 R
/Prev 1163 0 R
/Next 1165 0 R
>>
endobj
1169 0 obj
<<
/Title (Registers)
/Dest [ 905 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1174 0 R
/Next 1157 0 R
/First 1175 0 R
/Last 1176 0 R
/Count 13
>>
endobj
1170 0 obj
<<
/Title (5.1 PCI Interface)
/Dest [ 997 0 R /FitH 482 ]
/Parent 1157 0 R
/Next 1171 0 R
/First 1172 0 R
/Last 1173 0 R
/Count 2
>>
endobj
1171 0 obj
<<
/Title (5.2 WISHBONE Interface)
/Dest [ 1003 0 R /FitH 466 ]
/Parent 1157 0 R
/Prev 1170 0 R
>>
endobj
1172 0 obj
<<
/Title (5.1.1 Required PCI Interface Pins)
/Dest [ 997 0 R /FitH 397 ]
/Parent 1170 0 R
/Next 1173 0 R
>>
endobj
1173 0 obj
<<
/Title (5.1.2 Implemented Optional PCI Interface Pins)
/Dest [ 1000 0 R /FitH 195 ]
/Parent 1170 0 R
/Prev 1172 0 R
>>
endobj
1174 0 obj
<<
/Title (Operation)
/Dest [ 821 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1188 0 R
/Next 1169 0 R
/First 1189 0 R
/Last 1190 0 R
/Count 27
>>
endobj
1175 0 obj
<<
/Title (4.1 Register List and Description)
/Dest [ 905 0 R /FitH 427 ]
/Parent 1169 0 R
/Next 1176 0 R
/First 1177 0 R
/Last 1178 0 R
/Count 11
>>
endobj
1176 0 obj
<<
/Title (4.2 Software obligations)
/Dest [ 991 0 R /FitH 443 ]
/Parent 1169 0 R
/Prev 1175 0 R
>>
endobj
1177 0 obj
<<
/Title (4.1.1 WISHBONE Slave Unit Control & Status)
/Dest [ 914 0 R /FitH 453 ]
/Parent 1175 0 R
/Next 1180 0 R
/First 1186 0 R
/Last 1187 0 R
/Count 2
>>
endobj
1178 0 obj
<<
/Title (4.1.4 Interrupt Control & Status Registers)
/Dest [ 985 0 R /FitH 475 ]
/Parent 1175 0 R
/Prev 1179 0 R
>>
endobj
1179 0 obj
<<
/Title (4.1.3 Reporting Registers)
/Dest [ 967 0 R /FitH 281 ]
/Parent 1175 0 R
/Prev 1180 0 R
/Next 1178 0 R
/First 1181 0 R
/Last 1182 0 R
/Count 4
>>
endobj
1180 0 obj
<<
/Title (4.1.2 PCI Target Unit Control & Status)
/Dest [ 930 0 R /FitH 298 ]
/Parent 1175 0 R
/Prev 1177 0 R
/Next 1179 0 R
/First 1185 0 R
/Last 1185 0 R
/Count 1
>>
endobj
1181 0 obj
<<
/Title (4.1.3.1 WISHBONE Slave Unit Error Reporting Registers)
/Dest [ 967 0 R /FitH 173 ]
/Parent 1179 0 R
/Next 1184 0 R
>>
endobj
1182 0 obj
<<
/Title (4.1.3.4 Interrupt Acknowledge Cycle Generation Register)
/Dest [ 985 0 R /FitH 632 ]
/Parent 1179 0 R
/Prev 1183 0 R
>>
endobj
1183 0 obj
<<
/Title (4.1.3.3 Configuration Cycle Generation Registers)
/Dest [ 976 0 R /FitH 307 ]
/Parent 1179 0 R
/Prev 1184 0 R
/Next 1182 0 R
>>
endobj
1184 0 obj
<<
/Title (4.1.3.2 PCI Target Unit Error Reporting Registers)
/Dest [ 970 0 R /FitH 233 ]
/Parent 1179 0 R
/Prev 1181 0 R
/Next 1183 0 R
>>
endobj
1185 0 obj
<<
/Title (4.1.2.2 PCI Image Control and Address Registers)
/Dest [ 943 0 R /FitH 424 ]
/Parent 1180 0 R
>>
endobj
1186 0 obj
<<
/Title (4.1.1.1 WISHBONE Configuration Space BAR)
/Dest [ 914 0 R /FitH 333 ]
/Parent 1177 0 R
/Next 1187 0 R
>>
endobj
1187 0 obj
<<
/Title (4.1.1.2 WISHBONE Image Control and Address Registers)
/Dest [ 921 0 R /FitH 583 ]
/Parent 1177 0 R
/Prev 1186 0 R
>>
endobj
1188 0 obj
<<
/Title (Architecture)
/Dest [ 202 0 R /FitH 608 ]
/Parent 1152 0 R
/Prev 1153 0 R
/Next 1174 0 R
/First 1216 0 R
/Last 1217 0 R
/Count 16
>>
endobj
1189 0 obj
<<
/Title (3.1 Configuration Space)
/Dest [ 821 0 R /FitH 483 ]
/Parent 1174 0 R
/Next 1194 0 R
/First 1211 0 R
/Last 1212 0 R
/Count 5
>>
endobj
1190 0 obj
<<
/Title (3.6 Interrupts)
/Dest [ 899 0 R /FitH 133 ]
/Parent 1174 0 R
/Prev 1191 0 R
>>
endobj
1191 0 obj
<<
/Title (3.5 Parity)
/Dest [ 899 0 R /FitH 397 ]
/Parent 1174 0 R
/Prev 1192 0 R
/Next 1190 0 R
>>
endobj
1192 0 obj
<<
/Title (3.4 Transaction Ordering)
/Dest [ 895 0 R /FitH 145 ]
/Parent 1174 0 R
/Prev 1193 0 R
/Next 1191 0 R
>>
endobj
1193 0 obj
<<
/Title (3.3 PCI Target Unit)
/Dest [ 865 0 R /FitH 434 ]
/Parent 1174 0 R
/Prev 1194 0 R
/Next 1192 0 R
/First 1195 0 R
/Last 1196 0 R
/Count 8
>>
endobj
1194 0 obj
<<
/Title (3.2 WISHBONE Slave Unit)
/Dest [ 843 0 R /FitH 338 ]
/Parent 1174 0 R
/Prev 1189 0 R
/Next 1193 0 R
/First 1203 0 R
/Last 1204 0 R
/Count 8
>>
endobj
1195 0 obj
<<
/Title (3.3.1 PCI Target Unit Functionality)
/Dest [ 865 0 R /FitH 330 ]
/Parent 1193 0 R
/Next 1198 0 R
/First 1199 0 R
/Last 1200 0 R
/Count 4
>>
endobj
1196 0 obj
<<
/Title (3.3.4 PCI to WISHBONE Read Cycles)
/Dest [ 887 0 R /FitH 279 ]
/Parent 1193 0 R
/Prev 1197 0 R
>>
endobj
1197 0 obj
<<
/Title (3.3.3 PCI to WISHBONE Write Cycles)
/Dest [ 879 0 R /FitH 638 ]
/Parent 1193 0 R
/Prev 1198 0 R
/Next 1196 0 R
>>
endobj
1198 0 obj
<<
/Title (3.3.2 Addressing and Images of the PCI Target Unit)
/Dest [ 869 0 R /FitH 245 ]
/Parent 1193 0 R
/Prev 1195 0 R
/Next 1197 0 R
>>
endobj
1199 0 obj
<<
/Title (3.3.1.1 PCI Target Module)
/Dest [ 869 0 R /FitH 606 ]
/Parent 1195 0 R
/Next 1202 0 R
>>
endobj
1200 0 obj
<<
/Title (3.3.1.4 WISHBONE Master Module)
/Dest [ 869 0 R /FitH 351 ]
/Parent 1195 0 R
/Prev 1201 0 R
>>
endobj
1201 0 obj
<<
/Title (3.3.1.3 PCIR_FIFO)
/Dest [ 869 0 R /FitH 432 ]
/Parent 1195 0 R
/Prev 1202 0 R
/Next 1200 0 R
>>
endobj
1202 0 obj
<<
/Title (3.3.1.2 PCIW_FIFO)
/Dest [ 869 0 R /FitH 513 ]
/Parent 1195 0 R
/Prev 1199 0 R
/Next 1201 0 R
>>
endobj
1203 0 obj
<<
/Title (3.2.1 WISHBONE Slave Unit Functionality)
/Dest [ 846 0 R /FitH 667 ]
/Parent 1194 0 R
/Next 1206 0 R
/First 1207 0 R
/Last 1208 0 R
/Count 4
>>
endobj
1204 0 obj
<<
/Title (3.2.4 WISHBONE to PCI Read Cycles)
/Dest [ 859 0 R /FitH 613 ]
/Parent 1194 0 R
/Prev 1205 0 R
>>
endobj
1205 0 obj
<<
/Title (3.2.3 WISHBONE to PCI Write Cycles)
/Dest [ 853 0 R /FitH 483 ]
/Parent 1194 0 R
/Prev 1206 0 R
/Next 1204 0 R
>>
endobj
1206 0 obj
<<
/Title (3.2.2 Addressing and Images of the WISHBONE Slave Unit)
/Dest [ 849 0 R /FitH 625 ]
/Parent 1194 0 R
/Prev 1203 0 R
/Next 1205 0 R
>>
endobj
1207 0 obj
<<
/Title (3.2.1.1 WISHBONE Slave Module)
/Dest [ 846 0 R /FitH 403 ]
/Parent 1203 0 R
/Next 1210 0 R
>>
endobj
1208 0 obj
<<
/Title (3.2.1.4 PCI Master Module)
/Dest [ 846 0 R /FitH 136 ]
/Parent 1203 0 R
/Prev 1209 0 R
>>
endobj
1209 0 obj
<<
/Title (3.2.1.3 WBR_FIFO)
/Dest [ 846 0 R /FitH 217 ]
/Parent 1203 0 R
/Prev 1210 0 R
/Next 1208 0 R
>>
endobj
1210 0 obj
<<
/Title (3.2.1.2 WBW_FIFO)
/Dest [ 846 0 R /FitH 310 ]
/Parent 1203 0 R
/Prev 1207 0 R
/Next 1209 0 R
>>
endobj
1211 0 obj
<<
/Title (3.1.1 Configuration Space Access for Host Bus Bridges)
/Dest [ 824 0 R /FitH 217 ]
/Parent 1189 0 R
/Next 1215 0 R
>>
endobj
1212 0 obj
<<
/Title (3.1.5 Generating Interrupt Acknowledge Cycles)
/Dest [ 843 0 R /FitH 514 ]
/Parent 1189 0 R
/Prev 1213 0 R
>>
endobj
1213 0 obj
<<
/Title (3.1.4 Generating Configuration Cycles)
/Dest [ 836 0 R /FitH 544 ]
/Parent 1189 0 R
/Prev 1214 0 R
/Next 1212 0 R
>>
endobj
1214 0 obj
<<
/Title (3.1.3 Configuration Cycles)
/Dest [ 833 0 R /FitH 187 ]
/Parent 1189 0 R
/Prev 1215 0 R
/Next 1213 0 R
>>
endobj
1215 0 obj
<<
/Title (3.1.2 Configuration Space Access for Guest Bridges)
/Dest [ 830 0 R /FitH 250 ]
/Parent 1189 0 R
/Prev 1211 0 R
/Next 1214 0 R
>>
endobj
1216 0 obj
<<
/Title (2.1 Overview)
/Dest [ 202 0 R /FitH 483 ]
/Parent 1188 0 R
/Next 1222 0 R
>>
endobj
1217 0 obj
<<
/Title (2.6 Address Translation Logic)
/Dest [ 813 0 R /FitH 679 ]
/Parent 1188 0 R
/Prev 1218 0 R
/First 1219 0 R
/Last 1219 0 R
/Count 1
>>
endobj
1218 0 obj
<<
/Title (2.5 FIFO)
/Dest [ 803 0 R /FitH 415 ]
/Parent 1188 0 R
/Prev 1220 0 R
/Next 1217 0 R
>>
endobj
1219 0 obj
<<
/Title (2.6.1 Description of Address Translation Logic)
/Dest [ 813 0 R /FitH 514 ]
/Parent 1217 0 R
>>
endobj
1220 0 obj
<<
/Title (2.4 Clocks)
/Dest [ 803 0 R /FitH 532 ]
/Parent 1188 0 R
/Prev 1221 0 R
/Next 1218 0 R
>>
endobj
1221 0 obj
<<
/Title (2.3 PCI Target Unit)
/Dest [ 797 0 R /FitH 326 ]
/Parent 1188 0 R
/Prev 1222 0 R
/Next 1220 0 R
/First 1223 0 R
/Last 1223 0 R
/Count 4
>>
endobj
1222 0 obj
<<
/Title (2.2 WISHBONE Slave Unit)
/Dest [ 791 0 R /FitH 364 ]
/Parent 1188 0 R
/Prev 1216 0 R
/Next 1221 0 R
/First 1227 0 R
/Last 1227 0 R
/Count 5
>>
endobj
1223 0 obj
<<
/Title (2.3.1 PCI Target Unit Architecture)
/Dest [ 797 0 R /FitH 136 ]
/Parent 1221 0 R
/First 1224 0 R
/Last 1225 0 R
/Count 3
>>
endobj
1224 0 obj
<<
/Title (2.3.1.1 PCI Target Module)
/Dest [ 800 0 R /FitH 284 ]
/Parent 1223 0 R
/Next 1226 0 R
>>
endobj
1225 0 obj
<<
/Title (2.3.1.3 WISHBONE Master Module)
/Dest [ 803 0 R /FitH 649 ]
/Parent 1223 0 R
/Prev 1226 0 R
>>
endobj
1226 0 obj
<<
/Title (2.3.1.2 PCIR_FIFO)
/Dest [ 800 0 R /FitH 160 ]
/Parent 1223 0 R
/Prev 1224 0 R
/Next 1225 0 R
>>
endobj
1227 0 obj
<<
/Title (2.2.1 WISHBONE Slave Unit Architecture)
/Dest [ 794 0 R /FitH 532 ]
/Parent 1222 0 R
/First 1228 0 R
/Last 1229 0 R
/Count 4
>>
endobj
1228 0 obj
<<
/Title (2.2.1.1 WISHBONE Slave Module)
/Dest [ 794 0 R /FitH 193 ]
/Parent 1227 0 R
/Next 1231 0 R
>>
endobj
1229 0 obj
<<
/Title (2.2.1.4 PCI Master Module)
/Dest [ 797 0 R /FitH 431 ]
/Parent 1227 0 R
/Prev 1230 0 R
>>
endobj
1230 0 obj
<<
/Title (2.2.1.3 WBR_FIFO)
/Dest [ 797 0 R /FitH 543 ]
/Parent 1227 0 R
/Prev 1231 0 R
/Next 1229 0 R
>>
endobj
1231 0 obj
<<
/Title (2.2.1.2 WBW_FIFO)
/Dest [ 797 0 R /FitH 679 ]
/Parent 1227 0 R
/Prev 1228 0 R
/Next 1230 0 R
>>
endobj
1232 0 obj
<<
/Title (1.1 What is a PCI Bridge?)
/Dest [ 196 0 R /FitH 483 ]
/Parent 1153 0 R
/Next 1234 0 R
>>
endobj
1233 0 obj
<<
/Title (1.3 PCI IP Core Features)
/Dest [ 196 0 R /FitH 220 ]
/Parent 1153 0 R
/Prev 1234 0 R
>>
endobj
1234 0 obj
<<
/Title (1.2 PCI IP Core Introduction)
/Dest [ 196 0 R /FitH 355 ]
/Parent 1153 0 R
/Prev 1232 0 R
/Next 1233 0 R
>>
endobj
1235 0 obj
<<
/ProcSet [ /PDF /Text /ImageB ]
/Font << /TT2 1236 0 R /TT4 1240 0 R /TT6 1243 0 R /TT8 1244 0 R /TT10 1246 0 R >>
/XObject << /Im1 1248 0 R >>
/ExtGState << /GS1 1249 0 R >>
/ColorSpace << /Cs5 1237 0 R >>
>>
endobj
1236 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 124
/Widths [ 278 0 0 556 0 0 722 0 333 333 0 0 278 333 278 278 556 556 556 556
556 556 556 0 556 556 333 0 0 584 0 611 0 722 722 722 722 667 611
778 722 278 0 722 611 833 722 778 667 778 722 667 611 722 667 944
667 667 0 333 0 333 0 556 0 556 611 556 611 556 333 611 611 278
0 556 278 889 611 611 611 0 389 556 333 611 556 778 556 556 500
0 280 ]
/Encoding /WinAnsiEncoding
/BaseFont /GECEFO+Arial-BoldMT
/FontDescriptor 1238 0 R
>>
endobj
1237 0 obj
[
/CalRGB << /WhitePoint [ 0.9505 1 1.089 ] /Gamma [ 2.22221 2.22221 2.22221 ]
/Matrix [ 0.4124 0.2126 0.0193 0.3576 0.71519 0.1192 0.1805 0.0722 0.9505 ] >>
]
endobj
1238 0 obj
<<
/Type /FontDescriptor
/Ascent 905
/CapHeight 0
/Descent -211
/Flags 32
/FontBBox [ -628 -376 2034 1048 ]
/FontName /GECEFO+Arial-BoldMT
/ItalicAngle 0
/StemV 133
/FontFile2 1250 0 R
>>
endobj
1239 0 obj
<< /Length 619 /Filter /FlateDecode >>
stream
|
H‰lTMo1½ûWÌ íVìÄßörR„Z èÞ*Ñ6iSH¶dÛ"þ=3¶óÕ¢=xbÏ{3óžÉttÐ Ò7öbòùJÁí(¬@´¥Ul@¥A´š¼lby&$ðG°ß"oóÏ%¬ôŒA¡_‹ÉÅZÁù ¾‰˜t1B·-¶>áR $¡ã')e-â’ÊC׎dÝq]}mõP7uµØäu:äu»ëF)ÔMôN¢¯fÓ¸ ]M°YùŒÓU@CùÀ'ÕÕŽ¯_-9j«UAôóDzQJl
|
H‰lTMo1½ûWÌ íVìÄßörR„Z èÞ*Ñ6iSH¶dÛ"þ=3¶óÕ¢=xbÏ{3óžÉttÐ Ò7öbòùJÁí(¬@´¥Ul@¥A´š¼lby&$ðG°ß"oóÏ%¬ôŒA¡_‹ÉÅZÁù ¾‰˜t1B·-¶>áR $¡ã')e-â’ÊC׎dÝq]}mõP7uµØäu:äu»ëF)ÔMôN¢¯fÓ¸ ]M°YùŒÓU@CùÀ'ÕÕŽ¯_-9j«UAôóDzQJl
|
”²
|¤#*ÔRj¨t—âS'bDOc£Ð‚5c(è¤!kqªÀ^8åÐy_¦ÁyfªÔÝSØÐXŽT8/;ÝÙáH£±=œ½Î&ímÖžä‘Å´íj{¸Aª}Äá½ùOÅ×ANæ´bqÛÆTŽí:MŬ·\{ç3[Þ—Pg£“m³Z±Ûd;ÅⲊ‹Y¯Ë ¸—뺺b¦+"“Ÿ+²p5l2œšò¹)íw2äÈiÍ:80.¢Þ[p4žqÜÛÑx±êv^æH[Êõ4¤Ž¦0áÉ„>÷ùáéñnØŽïàKíóÓh«»9½—_‹Mo ›ß,îËñ¼–«íÏáyÕçYZ§›¯CL%vs$źf%ˆÙ "æ›÷Ã1“˜#ÛÛL#ÑÙØ&šèžƥ鹃—¨<½’»·ìè¥%K(HøÂ9iâ‰pÅêʲî(%¿z{ÐÊåA¾/ž±n,¿;Y_.ýw^“ø‰É$—óÍÓ|û—|yË®‚“GûO€ 0ÁÇ
|
”²
|¤#*ÔRj¨t—âS'bDOc£Ð‚5c(è¤!kqªÀ^8åÐy_¦ÁyfªÔÝSØÐXŽT8/;ÝÙáH£±=œ½Î&ímÖžä‘Å´íj{¸Aª}Äá½ùOÅ×ANæ´bqÛÆTŽí:MŬ·\{ç3[Þ—Pg£“m³Z±Ûd;ÅⲊ‹Y¯Ë ¸—뺺b¦+"“Ÿ+²p5l2œšò¹)íw2äÈiÍ:80.¢Þ[p4žqÜÛÑx±êv^æH[Êõ4¤Ž¦0áÉ„>÷ùáéñnØŽïàKíóÓh«»9½—_‹Mo ›ß,îËñ¼–«íÏáyÕçYZ§›¯CL%vs$źf%ˆÙ "æ›÷Ã1“˜#ÛÛL#ÑÙØ&šèžƥ鹃—¨<½’»·ìè¥%K(HøÂ9iâ‰pÅêʲî(%¿z{ÐÊåA¾/ž±n,¿;Y_.ýw^“ø‰É$—óÍÓ|û—|yË®‚“GûO€ 0ÁÇ
|
endstream
endobj
1240 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 151
/Widths [ 250 0 0 667 0 0 729 0 292 292 427 0 219 313 219 500 469 469 469 469
469 469 469 469 469 469 219 219 667 667 0 365 0 677 615 635 771
656 563 771 760 354 0 740 573 833 771 781 563 771 625 479 615 708
677 885 698 656 0 271 0 271 0 500 0 406 510 417 500 417 323 448
510 229 229 469 229 771 510 510 510 490 333 365 292 490 469 667
458 417 427 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 219 448
448 0 500 1000 ]
/Encoding /WinAnsiEncoding
/BaseFont /GECEHO+Garamond
/FontDescriptor 1241 0 R
>>
endobj
1241 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 34
/FontBBox [ -139 -307 1063 986 ]
/FontName /GECEHO+Garamond
/ItalicAngle 0
/StemV 0
/FontFile2 1251 0 R
>>
endobj
1242 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 34
/FontBBox [ -147 -372 1168 996 ]
/FontName /Garamond-Bold
/ItalicAngle 0
/StemV 133
>>
endobj
1243 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 150
/Widths [ 250 0 0 667 0 0 0 0 354 354 0 0 260 333 260 552 469 396 469 469 469
469 469 469 469 469 260 0 0 0 0 0 0 656 677 677 781 708 615 729
865 396 375 677 635 917 844 792 615 0 698 510 688 760 667 896 688
656 0 365 0 365 0 500 0 479 552 469 552 469 302 542 552 281 0 531
260 844 552 521 552 0 344 417 313 552 458 708 500 469 469 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 250 0 0 0 500 ]
/Encoding /WinAnsiEncoding
/BaseFont /Garamond-Bold
/FontDescriptor 1242 0 R
>>
endobj
1244 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 118
/Widths [ 278 0 0 0 0 0 667 0 0 0 0 0 0 0 278 0 0 0 0 0 0 0 0 0 0 0 278 0 0
0 0 0 1015 667 667 722 722 667 0 778 722 278 0 0 0 833 722 778 667
0 722 667 611 0 0 944 667 667 0 0 0 0 0 556 0 556 556 500 556 556
278 556 556 222 222 500 222 833 556 556 556 0 333 500 278 556 500
]
/Encoding /WinAnsiEncoding
/BaseFont /Arial-ItalicMT
/FontDescriptor 1245 0 R
>>
endobj
1245 0 obj
<<
/Type /FontDescriptor
/Ascent 905
/CapHeight 0
/Descent -211
/Flags 96
/FontBBox [ -517 -325 1082 1025 ]
/FontName /Arial-ItalicMT
/ItalicAngle -15
/StemV 0
>>
endobj
1246 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 121
/Widths [ 250 0 0 0 0 0 906 0 0 0 0 0 219 0 219 0 469 469 469 469 469 469 469
469 469 469 0 0 0 0 0 0 0 760 563 625 729 688 573 708 771 323 0
0 635 0 781 677 531 0 625 500 583 719 0 885 0 0 0 0 0 0 0 0 0 406
0 271 406 292 219 323 417 229 0 521 219 625 427 354 406 427 302
292 250 427 344 531 0 333 ]
/Encoding /WinAnsiEncoding
/BaseFont /Garamond-Italic
/FontDescriptor 1247 0 R
>>
endobj
1247 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 98
/FontBBox [ -217 -315 1129 993 ]
/FontName /Garamond-Italic
/ItalicAngle -15
/StemV 0
>>
endobj
1248 0 obj
<< /Type /XObject /Subtype /Image /Width 192 /Height 185 /BitsPerComponent 1
/ImageMask true /Length 287 /Filter /CCITTFaxDecode /DecodeParms << /K -1 /Columns 192 >> >>
stream
|
endstream
endobj
1240 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 151
/Widths [ 250 0 0 667 0 0 729 0 292 292 427 0 219 313 219 500 469 469 469 469
469 469 469 469 469 469 219 219 667 667 0 365 0 677 615 635 771
656 563 771 760 354 0 740 573 833 771 781 563 771 625 479 615 708
677 885 698 656 0 271 0 271 0 500 0 406 510 417 500 417 323 448
510 229 229 469 229 771 510 510 510 490 333 365 292 490 469 667
458 417 427 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 219 448
448 0 500 1000 ]
/Encoding /WinAnsiEncoding
/BaseFont /GECEHO+Garamond
/FontDescriptor 1241 0 R
>>
endobj
1241 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 34
/FontBBox [ -139 -307 1063 986 ]
/FontName /GECEHO+Garamond
/ItalicAngle 0
/StemV 0
/FontFile2 1251 0 R
>>
endobj
1242 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 34
/FontBBox [ -147 -372 1168 996 ]
/FontName /Garamond-Bold
/ItalicAngle 0
/StemV 133
>>
endobj
1243 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 150
/Widths [ 250 0 0 667 0 0 0 0 354 354 0 0 260 333 260 552 469 396 469 469 469
469 469 469 469 469 260 0 0 0 0 0 0 656 677 677 781 708 615 729
865 396 375 677 635 917 844 792 615 0 698 510 688 760 667 896 688
656 0 365 0 365 0 500 0 479 552 469 552 469 302 542 552 281 0 531
260 844 552 521 552 0 344 417 313 552 458 708 500 469 469 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 250 0 0 0 500 ]
/Encoding /WinAnsiEncoding
/BaseFont /Garamond-Bold
/FontDescriptor 1242 0 R
>>
endobj
1244 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 118
/Widths [ 278 0 0 0 0 0 667 0 0 0 0 0 0 0 278 0 0 0 0 0 0 0 0 0 0 0 278 0 0
0 0 0 1015 667 667 722 722 667 0 778 722 278 0 0 0 833 722 778 667
0 722 667 611 0 0 944 667 667 0 0 0 0 0 556 0 556 556 500 556 556
278 556 556 222 222 500 222 833 556 556 556 0 333 500 278 556 500
]
/Encoding /WinAnsiEncoding
/BaseFont /Arial-ItalicMT
/FontDescriptor 1245 0 R
>>
endobj
1245 0 obj
<<
/Type /FontDescriptor
/Ascent 905
/CapHeight 0
/Descent -211
/Flags 96
/FontBBox [ -517 -325 1082 1025 ]
/FontName /Arial-ItalicMT
/ItalicAngle -15
/StemV 0
>>
endobj
1246 0 obj
<<
/Type /Font
/Subtype /TrueType
/FirstChar 32
/LastChar 121
/Widths [ 250 0 0 0 0 0 906 0 0 0 0 0 219 0 219 0 469 469 469 469 469 469 469
469 469 469 0 0 0 0 0 0 0 760 563 625 729 688 573 708 771 323 0
0 635 0 781 677 531 0 625 500 583 719 0 885 0 0 0 0 0 0 0 0 0 406
0 271 406 292 219 323 417 229 0 521 219 625 427 354 406 427 302
292 250 427 344 531 0 333 ]
/Encoding /WinAnsiEncoding
/BaseFont /Garamond-Italic
/FontDescriptor 1247 0 R
>>
endobj
1247 0 obj
<<
/Type /FontDescriptor
/Ascent 861
/CapHeight 0
/Descent -263
/Flags 98
/FontBBox [ -217 -315 1129 993 ]
/FontName /Garamond-Italic
/ItalicAngle -15
/StemV 0
>>
endobj
1248 0 obj
<< /Type /XObject /Subtype /Image /Width 192 /Height 185 /BitsPerComponent 1
/ImageMask true /Length 287 /Filter /CCITTFaxDecode /DecodeParms << /K -1 /Columns 192 >> >>
stream
|
;IS§N:téÓ§N:téÁ¸7á¸n·
Û·nÝ»víÛ”°{‚Ü Û„ÓnwMºwM¿tî›~éßnû÷Nýöýû÷ïß¿~ýôýÚ¹P»¯ujééÕ«¯tÚN]{¦Òujé´CŠE6‰PT0ºa„
Ó7Q
Ón˜n›tÃtÛ¦Ý6÷{«
+iXiXe(iXd0•ƒV Ò²+ Î 4&•ÓJÒt®•¤¯WJéZ«ÕÒ½^®•ª½^¯W«Õêõn®Õêõv¯Vêí]«Õ¶®ÕêÛ!¦êᦴÕØM[
5pÂa‚¶FÇq·nÝ»víÛ·aÛ°ì;ò»d¶mÞZµjÕ«VZµjÕ«VZµ
|
;IS§N:téÓ§N:téÁ¸7á¸n·
Û·nÝ»víÛ”°{‚Ü Û„ÓnwMºwM¿tî›~éßnû÷Nýöýû÷ïß¿~ýôýÚ¹P»¯ujééÕ«¯tÚN]{¦Òujé´CŠE6‰PT0ºa„
Ó7Q
Ón˜n›tÃtÛ¦Ý6÷{«
+iXiXe(iXd0•ƒV Ò²+ Î 4&•ÓJÒt®•¤¯WJéZ«ÕÒ½^®•ª½^¯W«Õêõn®Õêõv¯Vêí]«Õ¶®ÕêÛ!¦êᦴÕØM[
5pÂa‚¶FÇq·nÝ»víÛ·aÛ°ì;ò»d¶mÞZµjÕ«VZµjÕ«VZµ
|
endstream
endobj
1249 0 obj
<<
/Type /ExtGState
/SA false
/SM 0.02
/TR /Identity
>>
endobj
1250 0 obj
<< /Filter /FlateDecode /Length 23778 /Length1 39540 >>
stream
|
endstream
endobj
1249 0 obj
<<
/Type /ExtGState
/SA false
/SM 0.02
/TR /Identity
>>
endobj
1250 0 obj
<< /Filter /FlateDecode /Length 23778 /Length1 39540 >>
stream
|
H‰|UtWþö9ç¿7ò yÒ?¹¤Fnh2%Aɽ!UI«‰Gç^I4AH+5˜¶©`Ì\:¥R£¥¦‚R¯ùC¦RÏÐ¥ÓªYTUµÍRªTºŒÇ0*÷Ÿ}/5ÌZÓsÖ¹wŸsöÙûÛÏ /C"wd~ïä §
|
H‰|UtWþö9ç¿7ò yÒ?¹¤Fnh2%Aɽ!UI«‰Gç^I4AH+5˜¶©`Ì\:¥R£¥¦‚R¯ùC¦RÏÐ¥ÓªYTUµÍRªTºŒÇ0*÷Ÿ}/5ÌZÓsÖ¹wŸsöÙûÛÏ /C"wd~ïä §
|
o\âÓœ¢rw…cëç©À²€vͨÔ
|